include/configs/PCI405.h

   1 /*
   2  * (C) Copyright 2007
   3  * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
   4  *
   5  * (C) Copyright 2001-2004
   6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * board/config.h - configuration options, board specific
  29  */
  30
  31 #ifndef __CONFIG_H
  32 #define __CONFIG_H
  33
  34 /*
  35  * High Level Configuration Options
  36  * (easy to change)
  37  */
  38 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  39 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  40 #define CONFIG_PCI405           1       /* ...on a PCI405 board         */
  41
  42 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  43 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r() on init   */
  44
  45 #define CONFIG_SYS_CLK_FREQ     25000000 /* external frequency to pll   */
  46
  47 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  48
  49 #define CONFIG_BAUDRATE         115200
  50 #define CONFIG_BOOTDELAY        0       /* autoboot after 0 seconds     */
  51
  52 #undef  CONFIG_BOOTARGS
  53 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  54         "mem_linux=14336k\0"                                            \
  55         "optargs=panic=0\0"                                             \
  56         "ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0"     \
  57         "addcons=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \
  58         ""
  59 #define CONFIG_BOOTCOMMAND      "run ramargs;run addcons;loadpci"
  60
  61 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  62
  63 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  64 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
  65
  66 #define CONFIG_MII              1       /* MII PHY management           */
  67 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  68
  69 #define CONFIG_RTC_M48T35A      1               /* ST Electronics M48 timekeeper */
  70
  71 #define CONFIG_COMMANDS       ( CONFIG_CMD_DFL  | \
  72                                 CFG_CMD_PCI     | \
  73                                 CFG_CMD_IRQ     | \
  74                                 CFG_CMD_ELF     | \
  75                                 CFG_CMD_DATE    | \
  76                                 CFG_CMD_I2C     | \
  77                                 CFG_CMD_BSP     | \
  78                                 CFG_CMD_EEPROM  )
  79
  80 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  81 #include <cmd_confdefs.h>
  82
  83 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  84
  85 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  86
  87 #define CONFIG_PRAM             2048    /* reserve 2 MB "protected RAM" */
  88
  89 /*
  90  * Miscellaneous configurable options
  91  */
  92 #define CFG_LONGHELP                    /* undef to save memory         */
  93 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
  94
  95 #define CFG_HUSH_PARSER                 /* use "hush" command parser    */
  96 #ifdef  CFG_HUSH_PARSER
  97 #define CFG_PROMPT_HUSH_PS2     "> "
  98 #endif
  99
 100 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 101 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 102 #else
 103 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 104 #endif
 105 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 106 #define CFG_MAXARGS     16              /* max number of command args   */
 107 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 108
 109 #define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
 110
 111 #define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
 112
 113 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 114 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 115
 116 #undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
 117 #define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
 118 #define CFG_BASE_BAUD       691200
 119
 120 /* The following table includes the supported baudrates */
 121 #define CFG_BAUDRATE_TABLE      \
 122         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 123          57600, 115200, 230400, 460800, 921600 }
 124
 125 #define CFG_LOAD_ADDR   0x100000        /* default load address */
 126 #define CFG_EXTBDINFO   1               /* To use extended board_into (bd_t) */
 127
 128 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 129
 130 #undef CONFIG_ZERO_BOOTDELAY_CHECK      /* check for keypress on bootdelay==0 */
 131
 132 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 133
 134 /*-----------------------------------------------------------------------
 135  * PCI stuff
 136  *-----------------------------------------------------------------------
 137  */
 138 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 139 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 140 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 141
 142 #define CONFIG_PCI                      /* include pci support          */
 143 #define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci host function    */
 144 #undef  CONFIG_PCI_PNP                  /* no pci plug-and-play         */
 145                                         /* resource configuration       */
 146
 147 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 148
 149 #define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 150 #define CFG_PCI_SUBSYS_DEVICEID 0x0407  /* PCI Device ID: PCI-405       */
 151 #define CFG_PCI_CLASSCODE       0x0280  /* PCI Class Code: Network/Other*/
 152 #define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
 153 #define CFG_PCI_PTM1MS  0xff000001      /* 16MB, enable hard-wired to 1 */
 154 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 155
 156 #if 0 /* test-only */
 157 #define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
 158 #define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
 159 #define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 160 #else
 161 #define CFG_PCI_PTM2LA  0xef600000      /* point to internal regs       */
 162 #define CFG_PCI_PTM2MS  0xffe00001      /* 2MB, enable                  */
 163 #define CFG_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
 164 #endif
 165
 166 /*-----------------------------------------------------------------------
 167  * Start addresses for the final memory configuration
 168  * (Set up by the startup code)
 169  * Please note that CFG_SDRAM_BASE _must_ start at 0
 170  */
 171 #define CFG_SDRAM_BASE          0x00000000
 172 #define CFG_FLASH_BASE          0xFFFD0000
 173 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 174 #define CFG_MONITOR_LEN         (192 * 1024)    /* Reserve 196 kB for Monitor   */
 175 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserve 128 kB for malloc()  */
 176
 177 /*
 178  * For booting Linux, the board info and command line data
 179  * have to be in the first 8 MB of memory, since this is
 180  * the maximum mapped by the Linux kernel during initialization.
 181  */
 182 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 183 /*-----------------------------------------------------------------------
 184  * FLASH organization
 185  */
 186 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 187 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
 188
 189 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 190 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 191
 192 #define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
 193 #define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
 194 #define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
 195 /*
 196  * The following defines are added for buggy IOP480 byte interface.
 197  * All other boards should use the standard values (CPCI405 etc.)
 198  */
 199 #define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
 200 #define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
 201 #define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
 202
 203 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 204
 205 #if 0 /* Use NVRAM for environment variables */
 206 /*-----------------------------------------------------------------------
 207  * NVRAM organization
 208  */
 209 #define CFG_ENV_IS_IN_NVRAM     1       /* use NVRAM for environment vars       */
 210 #define CFG_ENV_SIZE            0x0ff8          /* Size of Environment vars     */
 211 #define CFG_ENV_ADDR            \
 212         (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8))   /* Env  */
 213
 214 #else /* Use EEPROM for environment variables */
 215
 216 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 217 #define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
 218 #define CFG_ENV_SIZE            0x400   /* 1024 bytes may be used for env vars*/
 219                                    /* total size of a CAT24WC08 is 1024 bytes */
 220 #endif
 221
 222 #define CFG_NVRAM_BASE_ADDR     0xf0200000              /* NVRAM base address   */
 223 #define CFG_NVRAM_SIZE          (32*1024)               /* NVRAM size           */
 224
 225 /*-----------------------------------------------------------------------
 226  * I2C EEPROM (CAT24WC16) for environment
 227  */
 228 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 229 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 230 #define CFG_I2C_SLAVE           0x7F
 231
 232 #define CFG_I2C_EEPROM_ADDR     0x50    /* EEPROM CAT28WC08             */
 233 #define CFG_I2C_EEPROM_ADDR_LEN 1       /* Bytes of address             */
 234 /* mask of address bits that overflow into the "EEPROM chip address"    */
 235 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x07
 236 #define CFG_EEPROM_PAGE_WRITE_BITS 4    /* The Catalyst CAT24WC08 has   */
 237                                         /* 16 byte page write mode using*/
 238                                         /* last 4 bits of the address   */
 239 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10   /* and takes up to 10 msec */
 240 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 241
 242 /*-----------------------------------------------------------------------
 243  * Cache Configuration
 244  */
 245 #define CFG_DCACHE_SIZE         8192    /* For AMCC 405 CPUs                    */
 246 #define CFG_CACHELINE_SIZE      32      /* ...                  */
 247 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 248 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value        */
 249 #endif
 250
 251 /*
 252  * Init Memory Controller:
 253  *
 254  * BR0/1 and OR0/1 (FLASH)
 255  */
 256
 257 #define FLASH_BASE0_PRELIM      0xFFE00000      /* FLASH bank #0        */
 258
 259 /*-----------------------------------------------------------------------
 260  * External Bus Controller (EBC) Setup
 261  */
 262
 263 /* Memory Bank 0 (Flash Bank 0) initialization                                  */
 264 #define CFG_EBC_PB0AP           0x92015480
 265 #define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 266
 267 /* Memory Bank 1 (NVRAM/RTC) initialization                                     */
 268 #define CFG_EBC_PB1AP           0x01005280  /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1     */
 269 #define CFG_EBC_PB1CR           0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit  */
 270
 271 /* Memory Bank 2 (CAN0, 1) initialization                                       */
 272 #define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 273 /*#define CFG_EBC_PB2AP           0x038056C0  / * BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 274 #define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 275
 276 /* Memory Bank 3 (FPGA internal) initialization                                 */
 277 #define CFG_EBC_PB3AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 278 #define CFG_EBC_PB3CR           0xF041C000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
 279 #define CFG_FPGA_BASE_ADDR      0xF0400000
 280
 281 /*-----------------------------------------------------------------------
 282  * FPGA stuff
 283  */
 284 /* FPGA internal regs */
 285 #define CFG_FPGA_MODE           0x00
 286 #define CFG_FPGA_STATUS         0x02
 287 #define CFG_FPGA_TS             0x04
 288 #define CFG_FPGA_TS_LOW         0x06
 289 #define CFG_FPGA_TS_CAP0        0x10
 290 #define CFG_FPGA_TS_CAP0_LOW    0x12
 291 #define CFG_FPGA_TS_CAP1        0x14
 292 #define CFG_FPGA_TS_CAP1_LOW    0x16
 293 #define CFG_FPGA_TS_CAP2        0x18
 294 #define CFG_FPGA_TS_CAP2_LOW    0x1a
 295 #define CFG_FPGA_TS_CAP3        0x1c
 296 #define CFG_FPGA_TS_CAP3_LOW    0x1e
 297
 298 /* FPGA Mode Reg */
 299 #define CFG_FPGA_MODE_CF_RESET  0x0001
 300 #define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
 301 #define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
 302 #define CFG_FPGA_MODE_TS_CLEAR  0x2000
 303
 304 /* FPGA Status Reg */
 305 #define CFG_FPGA_STATUS_DIP0    0x0001
 306 #define CFG_FPGA_STATUS_DIP1    0x0002
 307 #define CFG_FPGA_STATUS_DIP2    0x0004
 308 #define CFG_FPGA_STATUS_FLASH   0x0008
 309 #define CFG_FPGA_STATUS_TS_IRQ  0x1000
 310
 311 #define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
 312 #define CFG_FPGA_MAX_SIZE       32*1024     /* 32kByte is enough for XC2S15  */
 313
 314 /* FPGA program pin configuration */
 315 #define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
 316 #define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
 317 #define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
 318 #define CFG_FPGA_INIT           0x00400000  /* FPGA init pin (ppc input)     */
 319 #define CFG_FPGA_DONE           0x00800000  /* FPGA done pin (ppc input)     */
 320 /* new INIT and DONE pins since board revision 1.2 (for PPC405GPr support)   */
 321 #define CFG_FPGA_INIT_V12       0x00008000  /* FPGA init pin (ppc input)     */
 322 #define CFG_FPGA_DONE_V12       0x00010000  /* FPGA done pin (ppc input)     */
 323
 324 /*-----------------------------------------------------------------------
 325  * Definitions for initial stack pointer and data area (in data cache)
 326  */
 327 #if 0 /* test-only */
 328 #define CFG_INIT_DCACHE_CS      7       /* use cs # 7 for data cache memory    */
 329 #define CFG_INIT_RAM_ADDR       0x40000000  /* use data cache                  */
 330 #define CFG_INIT_RAM_END        0x2000  /* End of used area in RAM             */
 331 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 332 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 333 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 334 #else
 335 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 336 #define CFG_TEMP_STACK_OCM        1
 337 /* On Chip Memory location */
 338 #define CFG_OCM_DATA_ADDR       0xF8000000
 339 #define CFG_OCM_DATA_SIZE       0x1000
 340 #define CFG_INIT_RAM_ADDR       CFG_OCM_DATA_ADDR /* inside of SDRAM            */
 341 #define CFG_INIT_RAM_END        CFG_OCM_DATA_SIZE /* End of used area in RAM    */
 342
 343 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 344 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 345 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 346 #endif
 347
 348 /*
 349  * Internal Definitions
 350  *
 351  * Boot Flags
 352  */
 353 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 354 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 355
 356 #endif  /* __CONFIG_H */