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Blackfin: unify default I2C settings for ADI boards
[people/ms/u-boot.git] / include / configs / PCIPPC2.h
1 /*
2 * (C) Copyright 2002-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 /*
25 *
26 * Configuration settings for the PCIPPC-2 board.
27 *
28 */
29
30 /* ------------------------------------------------------------------------- */
31
32 /*
33 * board/config.h - configuration options, board specific
34 */
35
36 #ifndef __CONFIG_H
37 #define __CONFIG_H
38
39 /*
40 * High Level Configuration Options
41 * (easy to change)
42 */
43
44 #define CONFIG_PCIPPC2 1 /* this is a PCIPPC2 board */
45
46 #define CONFIG_BOARD_EARLY_INIT_F 1
47 #define CONFIG_MISC_INIT_R 1
48
49 #define CONFIG_CONS_INDEX 1
50 #define CONFIG_BAUDRATE 9600
51 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
52
53 #define CONFIG_PREBOOT ""
54 #define CONFIG_BOOTDELAY 5
55
56 /*
57 * BOOTP options
58 */
59 #define CONFIG_BOOTP_SUBNETMASK
60 #define CONFIG_BOOTP_GATEWAY
61 #define CONFIG_BOOTP_HOSTNAME
62 #define CONFIG_BOOTP_BOOTPATH
63 #define CONFIG_BOOTP_BOOTFILESIZE
64
65 #define CONFIG_MAC_PARTITION
66 #define CONFIG_DOS_PARTITION
67
68
69 /*
70 * Command line configuration.
71 */
72 #include <config_cmd_default.h>
73
74 #define CONFIG_CMD_ASKENV
75 #define CONFIG_CMD_BSP
76 #define CONFIG_CMD_DATE
77 #define CONFIG_CMD_DHCP
78 #define CONFIG_CMD_ELF
79 #define CONFIG_CMD_NFS
80 #define CONFIG_CMD_PCI
81 #define CONFIG_CMD_SNTP
82
83 #define CONFIG_PCI 1
84 #define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
85
86 /*
87 * Miscellaneous configurable options
88 */
89 #define CONFIG_SYS_LONGHELP /* undef to save memory */
90 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
91
92 #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
93 #ifdef CONFIG_SYS_HUSH_PARSER
94 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
95 #endif
96 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
97
98 /* Print Buffer Size
99 */
100 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
101
102 #define CONFIG_SYS_MAXARGS 64 /* max number of command args */
103 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
104 #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
105
106 /*-----------------------------------------------------------------------
107 * Start addresses for the final memory configuration
108 * (Set up by the startup code)
109 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
110 */
111 #define CONFIG_SYS_SDRAM_BASE 0x00000000
112 #define CONFIG_SYS_FLASH_BASE 0xFFF00000
113 #define CONFIG_SYS_FLASH_MAX_SIZE 0x00100000
114 /* Maximum amount of RAM.
115 */
116 #define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 /* 512Mb */
117
118 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
119
120 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
121
122 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
123 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
124
125 #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_SDRAM_BASE && \
126 CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE
127 #define CONFIG_SYS_RAMBOOT
128 #else
129 #undef CONFIG_SYS_RAMBOOT
130 #endif
131
132 #define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
133 #define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
134
135 /*-----------------------------------------------------------------------
136 * Definitions for initial stack pointer and data area
137 */
138
139 /* Size in bytes reserved for initial data
140 */
141 #define CONFIG_SYS_GBL_DATA_SIZE 128
142
143 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
144 #define CONFIG_SYS_INIT_RAM_END 0x8000
145 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
146 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
147
148 #define CONFIG_SYS_INIT_RAM_LOCK
149
150 /*
151 * Temporary buffer for serial data until the real serial driver
152 * is initialised (memtest will destroy this buffer)
153 */
154 #define CONFIG_SYS_SCONSOLE_ADDR CONFIG_SYS_INIT_RAM_ADDR
155 #define CONFIG_SYS_SCONSOLE_SIZE 0x0002000
156
157 /* SDRAM 0 - 256MB
158 */
159 #define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
160 #define CONFIG_SYS_DBAT0U (CONFIG_SYS_SDRAM_BASE | \
161 BATU_BL_256M | BATU_VS | BATU_VP)
162 /* SDRAM 1 - 256MB
163 */
164 #define CONFIG_SYS_DBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \
165 BATL_PP_10 | BATL_MEMCOHERENCE)
166 #define CONFIG_SYS_DBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \
167 BATU_BL_256M | BATU_VS | BATU_VP)
168
169 /* Init RAM in the CPU DCache (no backing memory)
170 */
171 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_INIT_RAM_ADDR | \
172 BATL_PP_10 | BATL_MEMCOHERENCE)
173 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_INIT_RAM_ADDR | \
174 BATU_BL_128K | BATU_VS | BATU_VP)
175
176 /* I/O and PCI memory at 0xf0000000
177 */
178 #define CONFIG_SYS_DBAT3L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
179 #define CONFIG_SYS_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
180
181 #define CONFIG_SYS_IBAT0L CONFIG_SYS_DBAT0L
182 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
183 #define CONFIG_SYS_IBAT1L CONFIG_SYS_DBAT1L
184 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
185 #define CONFIG_SYS_IBAT2L CONFIG_SYS_DBAT2L
186 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
187 #define CONFIG_SYS_IBAT3L CONFIG_SYS_DBAT3L
188 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
189
190 /*
191 * Low Level Configuration Settings
192 * (address mappings, register initial values, etc.)
193 * You should know what you are doing if you make changes here.
194 * For the detail description refer to the PCIPPC2 user's manual.
195 */
196 #define CONFIG_SYS_HZ 1000
197 #define CONFIG_SYS_BUS_CLK 100000000 /* bus speed - 100 mhz */
198 #define CONFIG_SYS_CPU_CLK 300000000
199
200 /*
201 * For booting Linux, the board info and command line data
202 * have to be in the first 8 MB of memory, since this is
203 * the maximum mapped by the Linux kernel during initialization.
204 */
205 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
206
207 /*-----------------------------------------------------------------------
208 * FLASH organization
209 */
210 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
211 #define CONFIG_SYS_MAX_FLASH_SECT 16 /* Max number of sectors in one bank */
212
213 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
214 #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
215
216 /*
217 * Note: environment is not EMBEDDED in the U-Boot code.
218 * It's stored in flash separately.
219 */
220 #define CONFIG_ENV_IS_IN_FLASH 1
221 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x70000)
222 #define CONFIG_ENV_SIZE 0x1000 /* Size of the Environment */
223 #define CONFIG_ENV_SECT_SIZE 0x10000 /* Size of the Environment Sector */
224
225 /*-----------------------------------------------------------------------
226 * Cache Configuration
227 */
228 #define CONFIG_SYS_CACHELINE_SIZE 32
229 #if defined(CONFIG_CMD_KGDB)
230 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
231 #endif
232
233 /*
234 * L2 cache
235 */
236 #undef CONFIG_SYS_L2
237 #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
238 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
239 #define L2_ENABLE (L2_INIT | L2CR_L2E)
240
241 /*
242 * Internal Definitions
243 *
244 * Boot Flags
245 */
246 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
247 #define BOOTFLAG_WARM 0x02 /* Software reboot */
248
249 /*-----------------------------------------------------------------------
250 RTC m48t59
251 */
252 #define CONFIG_RTC_MK48T59
253
254 #define CONFIG_WATCHDOG
255
256 #define CONFIG_NET_MULTI /* Multi ethernet cards support */
257
258 #define CONFIG_EEPRO100
259 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
260 #define CONFIG_TULIP
261
262 #endif /* __CONFIG_H */