include/configs/PCIPPC2.h

   1 /*
   2  * (C) Copyright 2002-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  *
  26  * Configuration settings for the PCIPPC-2 board.
  27  *
  28  */
  29
  30 /* ------------------------------------------------------------------------- */
  31
  32 /*
  33  * board/config.h - configuration options, board specific
  34  */
  35
  36 #ifndef __CONFIG_H
  37 #define __CONFIG_H
  38
  39 /*
  40  * High Level Configuration Options
  41  * (easy to change)
  42  */
  43
  44 #define CONFIG_PCIPPC2          1       /* this is a PCIPPC2 board      */
  45
  46 #define CONFIG_BOARD_EARLY_INIT_F 1
  47 #define CONFIG_MISC_INIT_R      1
  48
  49 #define CONFIG_CONS_INDEX       1
  50 #define CONFIG_BAUDRATE         9600
  51 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
  52
  53 #define CONFIG_PREBOOT          ""
  54 #define CONFIG_BOOTDELAY        5
  55
  56 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | \
  57                                  CONFIG_BOOTP_BOOTFILESIZE)
  58
  59 #define CONFIG_MAC_PARTITION
  60 #define CONFIG_DOS_PARTITION
  61
  62
  63 /*
  64  * Command line configuration.
  65  */
  66 #include <config_cmd_default.h>
  67
  68 #define CONFIG_CMD_ASKENV
  69 #define CONFIG_CMD_BSP
  70 #define CONFIG_CMD_DATE
  71 #define CONFIG_CMD_DHCP
  72 #define CONFIG_CMD_DOC
  73 #define CONFIG_CMD_ELF
  74 #define CONFIG_CMD_NFS
  75 #define CONFIG_CMD_PCI
  76 #define CONFIG_CMD_SNTP
  77
  78 #define CONFIG_PCI              1
  79 #define CONFIG_PCI_PNP          1       /* PCI plug-and-play */
  80
  81 #define CFG_NAND_LEGACY
  82
  83 /*
  84  * Miscellaneous configurable options
  85  */
  86 #define CFG_LONGHELP                    /* undef to save memory         */
  87 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
  88
  89 #define CFG_HUSH_PARSER         1       /* use "hush" command parser    */
  90 #ifdef  CFG_HUSH_PARSER
  91 #define CFG_PROMPT_HUSH_PS2     "> "
  92 #endif
  93 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
  94
  95 /* Print Buffer Size
  96  */
  97 #define CFG_PBSIZE      (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
  98
  99 #define CFG_MAXARGS     64              /* max number of command args   */
 100 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 101 #define CFG_LOAD_ADDR   0x00100000      /* Default load address         */
 102
 103 /*-----------------------------------------------------------------------
 104  * Start addresses for the final memory configuration
 105  * (Set up by the startup code)
 106  * Please note that CFG_SDRAM_BASE _must_ start at 0
 107  */
 108 #define CFG_SDRAM_BASE      0x00000000
 109 #define CFG_FLASH_BASE      0xFFF00000
 110 #define CFG_FLASH_MAX_SIZE  0x00100000
 111 /* Maximum amount of RAM.
 112  */
 113 #define CFG_MAX_RAM_SIZE    0x20000000  /* 512Mb                        */
 114
 115 #define CFG_RESET_ADDRESS   0xFFF00100
 116
 117 #define CFG_MONITOR_BASE    TEXT_BASE
 118
 119 #define CFG_MONITOR_LEN     (256 << 10) /* Reserve 256 kB for Monitor   */
 120 #define CFG_MALLOC_LEN      (128 << 10) /* Reserve 128 kB for malloc()  */
 121
 122 #if CFG_MONITOR_BASE >= CFG_SDRAM_BASE && \
 123     CFG_MONITOR_BASE < CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE
 124 #define CFG_RAMBOOT
 125 #else
 126 #undef CFG_RAMBOOT
 127 #endif
 128
 129 #define CFG_MEMTEST_START   0x00004000  /* memtest works on             */
 130 #define CFG_MEMTEST_END     0x02000000  /* 0 ... 32 MB in DRAM          */
 131
 132 /*-----------------------------------------------------------------------
 133  * Definitions for initial stack pointer and data area
 134  */
 135
 136 /* Size in bytes reserved for initial data
 137  */
 138 #define CFG_GBL_DATA_SIZE    128
 139
 140 #define CFG_INIT_RAM_ADDR     0x40000000
 141 #define CFG_INIT_RAM_END      0x8000
 142 #define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 143 #define CFG_INIT_SP_OFFSET    CFG_GBL_DATA_OFFSET
 144
 145 #define CFG_INIT_RAM_LOCK
 146
 147 /*
 148  * Temporary buffer for serial data until the real serial driver
 149  * is initialised (memtest will destroy this buffer)
 150  */
 151 #define CFG_SCONSOLE_ADDR     CFG_INIT_RAM_ADDR
 152 #define CFG_SCONSOLE_SIZE     0x0002000
 153
 154 /* SDRAM 0 - 256MB
 155  */
 156 #define CFG_DBAT0L            (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 157 #define CFG_DBAT0U            (CFG_SDRAM_BASE | \
 158                                BATU_BL_256M | BATU_VS | BATU_VP)
 159 /* SDRAM 1 - 256MB
 160  */
 161 #define CFG_DBAT1L            ((CFG_SDRAM_BASE + 0x10000000) | \
 162                                BATL_PP_10 | BATL_MEMCOHERENCE)
 163 #define CFG_DBAT1U            ((CFG_SDRAM_BASE + 0x10000000) | \
 164                                BATU_BL_256M | BATU_VS | BATU_VP)
 165
 166 /* Init RAM in the CPU DCache (no backing memory)
 167  */
 168 #define CFG_DBAT2L            (CFG_INIT_RAM_ADDR | \
 169                                BATL_PP_10 | BATL_MEMCOHERENCE)
 170 #define CFG_DBAT2U            (CFG_INIT_RAM_ADDR | \
 171                                BATU_BL_128K | BATU_VS | BATU_VP)
 172
 173 /* I/O and PCI memory at 0xf0000000
 174  */
 175 #define CFG_DBAT3L            (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 176 #define CFG_DBAT3U            (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 177
 178 #define CFG_IBAT0L            CFG_DBAT0L
 179 #define CFG_IBAT0U            CFG_DBAT0U
 180 #define CFG_IBAT1L            CFG_DBAT1L
 181 #define CFG_IBAT1U            CFG_DBAT1U
 182 #define CFG_IBAT2L            CFG_DBAT2L
 183 #define CFG_IBAT2U            CFG_DBAT2U
 184 #define CFG_IBAT3L            CFG_DBAT3L
 185 #define CFG_IBAT3U            CFG_DBAT3U
 186
 187 /*
 188  * Low Level Configuration Settings
 189  * (address mappings, register initial values, etc.)
 190  * You should know what you are doing if you make changes here.
 191  * For the detail description refer to the PCIPPC2 user's manual.
 192  */
 193 #define CFG_HZ                1000
 194 #define CFG_BUS_HZ            100000000 /* bus speed - 100 mhz          */
 195 #define CFG_CPU_CLK           300000000
 196 #define CFG_BUS_CLK           100000000
 197
 198 /*
 199  * For booting Linux, the board info and command line data
 200  * have to be in the first 8 MB of memory, since this is
 201  * the maximum mapped by the Linux kernel during initialization.
 202  */
 203 #define CFG_BOOTMAPSZ         (8 << 20) /* Initial Memory map for Linux */
 204
 205 /*-----------------------------------------------------------------------
 206  * FLASH organization
 207  */
 208 #define CFG_MAX_FLASH_BANKS     1       /* Max number of flash banks            */
 209 #define CFG_MAX_FLASH_SECT      16      /* Max number of sectors in one bank    */
 210
 211 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 212 #define CFG_FLASH_WRITE_TOUT    1000    /* Timeout for Flash Write (in ms)      */
 213
 214 /*
 215  * Note: environment is not EMBEDDED in the U-Boot code.
 216  * It's stored in flash separately.
 217  */
 218 #define CFG_ENV_IS_IN_FLASH     1
 219 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x70000)
 220 #define CFG_ENV_SIZE            0x1000  /* Size of the Environment              */
 221 #define CFG_ENV_SECT_SIZE       0x10000 /* Size of the Environment Sector       */
 222
 223 /*-----------------------------------------------------------------------
 224  * Cache Configuration
 225  */
 226 #define CFG_CACHELINE_SIZE      32
 227 #if defined(CONFIG_CMD_KGDB)
 228 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value        */
 229 #endif
 230
 231 /*
 232  * L2 cache
 233  */
 234 #undef CFG_L2
 235 #define L2_INIT   (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
 236                    L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
 237 #define L2_ENABLE (L2_INIT | L2CR_L2E)
 238
 239 /*
 240  * Internal Definitions
 241  *
 242  * Boot Flags
 243  */
 244 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH     */
 245 #define BOOTFLAG_WARM           0x02    /* Software reboot                      */
 246
 247 /*-----------------------------------------------------------------------
 248  * Disk-On-Chip configuration
 249  */
 250
 251 #define CFG_MAX_DOC_DEVICE      1       /* Max number of DOC devices            */
 252
 253 #define CFG_DOC_SUPPORT_2000
 254 #undef CFG_DOC_SUPPORT_MILLENNIUM
 255
 256 /*-----------------------------------------------------------------------
 257   RTC m48t59
 258 */
 259 #define CONFIG_RTC_MK48T59
 260
 261 #define CONFIG_WATCHDOG
 262
 263 #define CONFIG_NET_MULTI                        /* Multi ethernet cards support */
 264
 265 #define CONFIG_EEPRO100
 266 #define CFG_RX_ETH_BUFFER       8               /* use 8 rx buffer on eepro100  */
 267 #define CONFIG_TULIP
 268
 269 #endif  /* __CONFIG_H */