include/configs/PCIPPC6.h

   1 /*
   2  * (C) Copyright 2002-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  *
  26  * Configuration settings for the PCIPPC-6 board.
  27  *
  28  */
  29
  30 /* ------------------------------------------------------------------------- */
  31
  32 /*
  33  * board/config.h - configuration options, board specific
  34  */
  35
  36 #ifndef __CONFIG_H
  37 #define __CONFIG_H
  38
  39 /*
  40  * High Level Configuration Options
  41  * (easy to change)
  42  */
  43
  44 #define CONFIG_PCIPPC2          1       /* this is a PCIPPC2 board      */
  45
  46 #define CONFIG_BOARD_EARLY_INIT_F 1
  47 #define CONFIG_MISC_INIT_R      1
  48
  49 #define CONFIG_CONS_INDEX       1
  50 #define CONFIG_BAUDRATE         9600
  51 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  52
  53 #define CONFIG_PREBOOT          ""
  54 #define CONFIG_BOOTDELAY        5
  55
  56 /*
  57  * BOOTP options
  58  */
  59 #define CONFIG_BOOTP_SUBNETMASK
  60 #define CONFIG_BOOTP_GATEWAY
  61 #define CONFIG_BOOTP_HOSTNAME
  62 #define CONFIG_BOOTP_BOOTPATH
  63 #define CONFIG_BOOTP_BOOTFILESIZE
  64
  65 #define CONFIG_MAC_PARTITION
  66 #define CONFIG_DOS_PARTITION
  67
  68
  69 /*
  70  * Command line configuration.
  71  */
  72 #include <config_cmd_default.h>
  73
  74 #define CONFIG_CMD_ASKENV
  75 #define CONFIG_CMD_BSP
  76 #define CONFIG_CMD_DATE
  77 #define CONFIG_CMD_DHCP
  78 #define CONFIG_CMD_ELF
  79 #define CONFIG_CMD_NFS
  80 #define CONFIG_CMD_PCI
  81 #define CONFIG_CMD_SCSI
  82 #define CONFIG_CMD_SNTP
  83
  84
  85 #define CONFIG_PCI              1
  86 #define CONFIG_PCI_PNP          1       /* PCI plug-and-play */
  87
  88 /*
  89  * Miscellaneous configurable options
  90  */
  91 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  92 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
  93
  94 #define CONFIG_SYS_HUSH_PARSER          1       /* use "hush" command parser    */
  95 #ifdef  CONFIG_SYS_HUSH_PARSER
  96 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
  97 #endif
  98 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  99
 100 /* Print Buffer Size
 101  */
 102 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 103
 104 #define CONFIG_SYS_MAXARGS      64              /* max number of command args   */
 105 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 106 #define CONFIG_SYS_LOAD_ADDR    0x00100000      /* Default load address         */
 107
 108 /*-----------------------------------------------------------------------
 109  * Start addresses for the final memory configuration
 110  * (Set up by the startup code)
 111  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 112  */
 113 #define CONFIG_SYS_SDRAM_BASE       0x00000000
 114 #define CONFIG_SYS_FLASH_BASE       0xFFF00000
 115 #define CONFIG_SYS_FLASH_MAX_SIZE  0x00100000
 116 /* Maximum amount of RAM.
 117  */
 118 #define CONFIG_SYS_MAX_RAM_SIZE    0x20000000   /* 512Mb                        */
 119
 120 #define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
 121
 122 #define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
 123
 124 #define CONFIG_SYS_MONITOR_LEN      (256 << 10) /* Reserve 256 kB for Monitor   */
 125 #define CONFIG_SYS_MALLOC_LEN       (128 << 10) /* Reserve 128 kB for malloc()  */
 126
 127 #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_SDRAM_BASE && \
 128     CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE
 129 #define CONFIG_SYS_RAMBOOT
 130 #else
 131 #undef CONFIG_SYS_RAMBOOT
 132 #endif
 133
 134 #define CONFIG_SYS_MEMTEST_START   0x00004000   /* memtest works on             */
 135 #define CONFIG_SYS_MEMTEST_END      0x02000000  /* 0 ... 32 MB in DRAM          */
 136
 137 /*-----------------------------------------------------------------------
 138  * Definitions for initial stack pointer and data area
 139  */
 140
 141 /* Size in bytes reserved for initial data
 142  */
 143 #define CONFIG_SYS_GBL_DATA_SIZE    128
 144
 145 #define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
 146 #define CONFIG_SYS_INIT_RAM_END      0x8000
 147 #define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 148 #define CONFIG_SYS_INIT_SP_OFFSET    CONFIG_SYS_GBL_DATA_OFFSET
 149
 150 #define CONFIG_SYS_INIT_RAM_LOCK
 151
 152 /*
 153  * Temporary buffer for serial data until the real serial driver
 154  * is initialised (memtest will destroy this buffer)
 155  */
 156 #define CONFIG_SYS_SCONSOLE_ADDR     CONFIG_SYS_INIT_RAM_ADDR
 157 #define CONFIG_SYS_SCONSOLE_SIZE     0x0002000
 158
 159 /* SDRAM 0 - 256MB
 160  */
 161 #define CONFIG_SYS_DBAT0L             (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 162 #define CONFIG_SYS_DBAT0U             (CONFIG_SYS_SDRAM_BASE | \
 163                                BATU_BL_256M | BATU_VS | BATU_VP)
 164 /* SDRAM 1 - 256MB
 165  */
 166 #define CONFIG_SYS_DBAT1L             ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \
 167                                BATL_PP_10 | BATL_MEMCOHERENCE)
 168 #define CONFIG_SYS_DBAT1U             ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \
 169                                BATU_BL_256M | BATU_VS | BATU_VP)
 170
 171 /* Init RAM in the CPU DCache (no backing memory)
 172  */
 173 #define CONFIG_SYS_DBAT2L             (CONFIG_SYS_INIT_RAM_ADDR | \
 174                                BATL_PP_10 | BATL_MEMCOHERENCE)
 175 #define CONFIG_SYS_DBAT2U             (CONFIG_SYS_INIT_RAM_ADDR | \
 176                                BATU_BL_128K | BATU_VS | BATU_VP)
 177
 178 /* I/O and PCI memory at 0xf0000000
 179  */
 180 #define CONFIG_SYS_DBAT3L             (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 181 #define CONFIG_SYS_DBAT3U             (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 182
 183 #define CONFIG_SYS_IBAT0L             CONFIG_SYS_DBAT0L
 184 #define CONFIG_SYS_IBAT0U             CONFIG_SYS_DBAT0U
 185 #define CONFIG_SYS_IBAT1L             CONFIG_SYS_DBAT1L
 186 #define CONFIG_SYS_IBAT1U             CONFIG_SYS_DBAT1U
 187 #define CONFIG_SYS_IBAT2L             CONFIG_SYS_DBAT2L
 188 #define CONFIG_SYS_IBAT2U             CONFIG_SYS_DBAT2U
 189 #define CONFIG_SYS_IBAT3L             CONFIG_SYS_DBAT3L
 190 #define CONFIG_SYS_IBAT3U             CONFIG_SYS_DBAT3U
 191
 192 /*
 193  * Low Level Configuration Settings
 194  * (address mappings, register initial values, etc.)
 195  * You should know what you are doing if you make changes here.
 196  * For the detail description refer to the PCIPPC2 user's manual.
 197  */
 198 #define CONFIG_SYS_HZ                 1000
 199 #define CONFIG_SYS_BUS_HZ             100000000 /* bus speed - 100 mhz          */
 200 #define CONFIG_SYS_CPU_CLK            300000000
 201 #define CONFIG_SYS_BUS_CLK            100000000
 202
 203 /*
 204  * For booting Linux, the board info and command line data
 205  * have to be in the first 8 MB of memory, since this is
 206  * the maximum mapped by the Linux kernel during initialization.
 207  */
 208 #define CONFIG_SYS_BOOTMAPSZ          (8 << 20) /* Initial Memory map for Linux */
 209
 210 /*-----------------------------------------------------------------------
 211  * FLASH organization
 212  */
 213 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* Max number of flash banks            */
 214 #define CONFIG_SYS_MAX_FLASH_SECT       16      /* Max number of sectors in one bank    */
 215
 216 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 217 #define CONFIG_SYS_FLASH_WRITE_TOUT     1000    /* Timeout for Flash Write (in ms)      */
 218
 219 /*
 220  * Note: environment is not EMBEDDED in the U-Boot code.
 221  * It's stored in flash separately.
 222  */
 223 #define CONFIG_ENV_IS_IN_FLASH  1
 224 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x70000)
 225 #define CONFIG_ENV_SIZE         0x1000  /* Size of the Environment              */
 226 #define CONFIG_ENV_SECT_SIZE    0x10000 /* Size of the Environment Sector       */
 227
 228 /*-----------------------------------------------------------------------
 229  * Cache Configuration
 230  */
 231 #define CONFIG_SYS_CACHELINE_SIZE       32
 232 #if defined(CONFIG_CMD_KGDB)
 233 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
 234 #endif
 235
 236 /*
 237  * L2 cache
 238  */
 239 #undef CONFIG_SYS_L2
 240 #define L2_INIT   (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
 241                    L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
 242 #define L2_ENABLE (L2_INIT | L2CR_L2E)
 243
 244 /*
 245  * Internal Definitions
 246  *
 247  * Boot Flags
 248  */
 249 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH     */
 250 #define BOOTFLAG_WARM           0x02    /* Software reboot                      */
 251
 252 /*-----------------------------------------------------------------------
 253   RTC m48t59
 254 */
 255 #define CONFIG_RTC_MK48T59
 256
 257 #define CONFIG_WATCHDOG
 258
 259 #define CONFIG_NET_MULTI                /* Multi ethernet cards support */
 260
 261 #define CONFIG_EEPRO100
 262 #define CONFIG_SYS_RX_ETH_BUFFER        8               /* use 8 rx buffer on eepro100  */
 263 #define CONFIG_TULIP
 264
 265
 266 #define CONFIG_SCSI_SYM53C8XX
 267 #define CONFIG_SCSI_DEV_ID      0x000B  /* 53c896 */
 268 #define CONFIG_SYS_SCSI_MAX_LUN 8       /* number of supported LUNs */
 269 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     15      /* maximum SCSI ID (0..6) */
 270 #define CONFIG_SYS_SCSI_MAX_DEVICE      CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN /* maximum Target devices */
 271 #define CONFIG_SYS_SCSI_SPIN_UP_TIME    2
 272 #define CONFIG_SYS_SCSI_SCAN_BUS_REVERSE 0
 273 #define CONFIG_DOS_PARTITION
 274 #define CONFIG_MAC_PARTITION
 275 #define CONFIG_ISO_PARTITION
 276
 277 #endif  /* __CONFIG_H */