include/configs/PIP405.h

   1 /*
   2  * (C) Copyright 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /***********************************************************
  32  * High Level Configuration Options
  33  * (easy to change)
  34  ***********************************************************/
  35 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  36 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  37 #define CONFIG_PIP405           1       /* ...on a PIP405 board         */
  38 /***********************************************************
  39  * Clock
  40  ***********************************************************/
  41 #define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
  42
  43 /***********************************************************
  44  * Command definitions
  45  ***********************************************************/
  46 #define CONFIG_COMMANDS         \
  47                        (CONFIG_CMD_DFL  | \
  48                         CFG_CMD_IDE     | \
  49                         CFG_CMD_DHCP    | \
  50                         CFG_CMD_PCI     | \
  51                         CFG_CMD_CACHE   | \
  52                         CFG_CMD_IRQ     | \
  53                         CFG_CMD_EEPROM  | \
  54                         CFG_CMD_I2C     | \
  55                         CFG_CMD_REGINFO | \
  56                         CFG_CMD_FDC     | \
  57                         CFG_CMD_SCSI    | \
  58                         CFG_CMD_DATE    | \
  59                         CFG_CMD_ELF     | \
  60                         CFG_CMD_USB     | \
  61                         CFG_CMD_MII     | \
  62                         CFG_CMD_SDRAM   | \
  63                         CFG_CMD_DOC     | \
  64                         CFG_CMD_SAVES   | \
  65                         CFG_CMD_BSP     )
  66 /* this must be included AFTER the definition of CONFIG_COMMANDS  (if any) */
  67 #include <cmd_confdefs.h>
  68
  69 #define  CFG_HUSH_PARSER
  70 #define  CFG_PROMPT_HUSH_PS2 "> "
  71 /**************************************************************
  72  * I2C Stuff:
  73  * the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address
  74  * 0x53.
  75  * Caution: on the same bus is the SPD (Serial Presens Detect
  76  * EEPROM of the SDRAM
  77  * The Atmel EEPROM uses 16Bit addressing.
  78  ***************************************************************/
  79 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
  80 #define CFG_I2C_SPEED           50000   /* I2C speed and slave address */
  81 #define CFG_I2C_SLAVE           0x7F
  82
  83 #define CFG_I2C_EEPROM_ADDR     0x53
  84 #define CFG_I2C_EEPROM_ADDR_LEN 2
  85 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
  86 #define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
  87 #define CFG_ENV_SIZE            0x800   /* 2 kBytes may be used for env vars */
  88
  89 #undef CFG_I2C_EEPROM_ADDR_OVERFLOW
  90 #define CFG_EEPROM_PAGE_WRITE_BITS 6    /* The Atmel 24C128/256 has     */
  91                                         /* 64 byte page write mode using*/
  92                                         /* last 6 bits of the address   */
  93 #define CFG_EEPROM_PAGE_WRITE_ENABLE    /* enable Page write */
  94 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10      /* and takes up to 10 msec */
  95
  96
  97 /***************************************************************
  98  * Definitions for Serial Presence Detect EEPROM address
  99  * (to get SDRAM settings)
 100  ***************************************************************/
 101 #define SPD_EEPROM_ADDRESS      0x50
 102
 103 #define CONFIG_BOARD_PRE_INIT
 104 /**************************************************************
 105  * Environment definitions
 106  **************************************************************/
 107 #define CONFIG_BAUDRATE         9600    /* STD Baudrate */
 108
 109
 110 #define CONFIG_BOOTDELAY        5
 111 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
 112 #define CONFIG_BOOT_RETRY_TIME  -10     /* feature is avaiable but not enabled */
 113 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check console even if bootdelay = 0 */
 114
 115
 116 #define CONFIG_BOOTCOMMAND      "diskboot 400000 0:1; bootm" /* autoboot command                */
 117 #define CONFIG_BOOTARGS         "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
 118
 119 #define CONFIG_IPADDR           10.0.0.100
 120 #define CONFIG_SERVERIP         10.0.0.1
 121 #define CONFIG_PREBOOT
 122 /***************************************************************
 123  * defines if the console is stored in the environment
 124  ***************************************************************/
 125 #define CFG_CONSOLE_IS_IN_ENV   /* stdin, stdout and stderr are in evironment */
 126 /***************************************************************
 127  * defines if an overwrite_console function exists
 128  *************************************************************/
 129 #define CFG_CONSOLE_OVERWRITE_ROUTINE
 130 #define CFG_CONSOLE_INFO_QUIET
 131 /***************************************************************
 132  * defines if the overwrite_console should be stored in the
 133  * environment
 134  **************************************************************/
 135 #undef CFG_CONSOLE_ENV_OVERWRITE
 136
 137 /**************************************************************
 138  * loads config
 139  *************************************************************/
 140 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 141 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 142
 143
 144 /***********************************************************
 145  * Miscellaneous configurable options
 146  **********************************************************/
 147 #define CFG_LONGHELP                    /* undef to save memory         */
 148 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 149 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 150 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 151 #else
 152 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 153 #endif
 154 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 155 #define CFG_MAXARGS     16              /* max number of command args   */
 156 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 157
 158 #define CFG_MEMTEST_START       0x0100000       /* memtest works on     */
 159 #define CFG_MEMTEST_END         0x0C00000       /* 1 ... 12 MB in DRAM  */
 160
 161 #undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
 162 #define CFG_BASE_BAUD       691200
 163
 164 /* The following table includes the supported baudrates */
 165 #define CFG_BAUDRATE_TABLE      \
 166         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 167          57600, 115200, 230400, 460800, 921600 }
 168
 169 #define CFG_LOAD_ADDR           0x400000        /* default load address */
 170 #define CFG_EXTBDINFO           1       /* To use extended board_into (bd_t) */
 171
 172 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 173
 174 /*-----------------------------------------------------------------------
 175  * PCI stuff
 176  *-----------------------------------------------------------------------
 177  */
 178 #define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
 179 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 180 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 181
 182 #define CONFIG_PCI                      /* include pci support          */
 183 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* configure as pci-host        */
 184 #define CONFIG_PCI_PNP                  /* pci plug-and-play            */
 185                                         /* resource configuration       */
 186 #define CFG_PCI_SUBSYS_VENDORID 0x0000  /* PCI Vendor ID: to-do!!!      */
 187 #define CFG_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: to-do!!!      */
 188 #define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
 189 #define CFG_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
 190 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 191 #define CFG_PCI_PTM2LA  0x00000000      /* disabled                     */
 192 #define CFG_PCI_PTM2MS  0x00000000      /* disabled                     */
 193 #define CFG_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
 194
 195 /*-----------------------------------------------------------------------
 196  * Start addresses for the final memory configuration
 197  * (Set up by the startup code)
 198  * Please note that CFG_SDRAM_BASE _must_ start at 0
 199  */
 200 #define CFG_SDRAM_BASE          0x00000000
 201 #define CFG_FLASH_BASE          0xFFF80000
 202 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 203 #define CFG_MONITOR_LEN         (512 * 1024)    /* Reserve 512 kB for Monitor   */
 204 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserve 128 kB for malloc()  */
 205
 206 /*
 207  * For booting Linux, the board info and command line data
 208  * have to be in the first 8 MB of memory, since this is
 209  * the maximum mapped by the Linux kernel during initialization.
 210  */
 211 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 212 /*-----------------------------------------------------------------------
 213  * FLASH organization
 214  */
 215 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 216 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
 217
 218 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 219 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 220
 221 /*-----------------------------------------------------------------------
 222  * Cache Configuration
 223  */
 224 #define CFG_DCACHE_SIZE         8192    /* For IBM 405 CPUs                     */
 225 #define CFG_CACHELINE_SIZE      32      /* ...                  */
 226 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 227 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value        */
 228 #endif
 229
 230 /*
 231  * Init Memory Controller:
 232  */
 233
 234 #define FLASH_BASE0_PRELIM      0xFFC00000      /* FLASH bank #0        */
 235 #define FLASH_BASE1_PRELIM      0               /* FLASH bank #1        */
 236
 237 /* Configuration Port location */
 238 #define CONFIG_PORT_ADDR        0xF4000000
 239 #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
 240
 241
 242 /*-----------------------------------------------------------------------
 243  * Definitions for initial stack pointer and data area (in On Chip SRAM)
 244  */
 245 #define CFG_TEMP_STACK_OCM      1
 246 #define CFG_OCM_DATA_ADDR       0xF0000000
 247 #define CFG_OCM_DATA_SIZE       0x1000
 248 #define CFG_INIT_RAM_ADDR       CFG_OCM_DATA_ADDR       /* inside of On Chip SRAM    */
 249 #define CFG_INIT_RAM_END        CFG_OCM_DATA_SIZE       /* End of On Chip SRAM         */
 250 #define CFG_GBL_DATA_SIZE       64              /* size in bytes reserved for initial data */
 251 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 252 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 253
 254 /*
 255  * Internal Definitions
 256  *
 257  * Boot Flags
 258  */
 259 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 260 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 261
 262
 263 /***********************************************************************
 264  * External peripheral base address
 265  ***********************************************************************/
 266 #define CFG_ISA_IO_BASE_ADDRESS 0xE8000000
 267
 268 /***********************************************************************
 269  * Last Stage Init
 270  ***********************************************************************/
 271 #define CONFIG_LAST_STAGE_INIT
 272 /************************************************************
 273  * Ethernet Stuff
 274  ***********************************************************/
 275 #define CONFIG_MII              1       /* MII PHY management           */
 276 #define CONFIG_PHY_ADDR         1       /* PHY address                  */
 277 #define CONFIG_CS8952_PHY       1       /* its a CS8952 PHY             */
 278 /************************************************************
 279  * RTC
 280  ***********************************************************/
 281 #define CONFIG_RTC_MC146818
 282 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 283
 284 /************************************************************
 285  * IDE/ATA stuff
 286  ************************************************************/
 287 #define CFG_IDE_MAXBUS          2   /* max. 2 IDE busses        */
 288 #define CFG_IDE_MAXDEVICE       (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 289
 290 #define CFG_ATA_BASE_ADDR       CFG_ISA_IO_BASE_ADDRESS /* base address */
 291 #define CFG_ATA_IDE0_OFFSET     0x01F0  /* ide0 offste */
 292 #define CFG_ATA_IDE1_OFFSET     0x0170  /* ide1 offset */
 293 #define CFG_ATA_DATA_OFFSET     0       /* data reg offset      */
 294 #define CFG_ATA_REG_OFFSET      0       /* reg offset */
 295 #define CFG_ATA_ALT_OFFSET      0x200   /* alternate register offset */
 296
 297 #undef  CONFIG_IDE_8xx_DIRECT           /* no pcmcia interface required */
 298 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 299 #define CONFIG_IDE_RESET                /* reset for ide supported...   */
 300 #define CONFIG_IDE_RESET_ROUTINE        /* with a special reset function */
 301
 302 /************************************************************
 303  * ATAPI support (experimental)
 304  ************************************************************/
 305 #define CONFIG_ATAPI                    /* enable ATAPI Support */
 306
 307 /************************************************************
 308  * SCSI support (experimental) only SYM53C8xx supported
 309  ************************************************************/
 310 #define CONFIG_SCSI_SYM53C8XX
 311 #define CFG_SCSI_MAX_LUN        8       /* number of supported LUNs */
 312 #define CFG_SCSI_MAX_SCSI_ID    7       /* maximum SCSI ID (0..6) */
 313 #define CFG_SCSI_MAX_DEVICE     CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
 314 #define CFG_SCSI_SPIN_UP_TIME   2
 315
 316 /************************************************************
 317  * Disk-On-Chip configuration
 318  ************************************************************/
 319 #define CFG_MAX_DOC_DEVICE      1       /* Max number of DOC devices            */
 320 #define CFG_DOC_SHORT_TIMEOUT
 321 #define CFG_DOC_SUPPORT_2000
 322 #define CFG_DOC_SUPPORT_MILLENNIUM
 323
 324 /************************************************************
 325  * DISK Partition support
 326  ************************************************************/
 327 #define CONFIG_DOS_PARTITION
 328 #define CONFIG_MAC_PARTITION
 329 #define CONFIG_ISO_PARTITION /* Experimental */
 330
 331 /************************************************************
 332  * Keyboard support
 333  ************************************************************/
 334 #define CONFIG_ISA_KEYBOARD
 335
 336 /************************************************************
 337  * Video support
 338  ************************************************************/
 339 #define CONFIG_VIDEO                    /*To enable video controller support */
 340 #define CONFIG_VIDEO_CT69000
 341 #define CONFIG_CFB_CONSOLE
 342 #define CONFIG_VIDEO_LOGO
 343 #define CONFIG_CONSOLE_EXTRA_INFO
 344 #define CONFIG_VGA_AS_SINGLE_DEVICE
 345 #define CONFIG_VIDEO_SW_CURSOR
 346 #define CONFIG_VIDEO_ONBOARD            /* Video controller is on-board */
 347
 348 /************************************************************
 349  * USB support
 350  ************************************************************/
 351 #define CONFIG_USB_UHCI
 352 #define CONFIG_USB_KEYBOARD
 353 #define CONFIG_USB_STORAGE
 354
 355 /* Enable needed helper functions */
 356 #define CFG_DEVICE_DEREGISTER           /* needs device_deregister */
 357
 358 /************************************************************
 359  * Debug support
 360  ************************************************************/
 361 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 362 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 363 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 364 #endif
 365
 366 /************************************************************
 367  * Ident
 368  ************************************************************/
 369 #define VERSION_TAG "released"
 370 #define CONFIG_ISO_STRING "MEV-10066-001"
 371 #define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
 372
 373
 374 #endif  /* __CONFIG_H */