include/configs/PK1C20.h

   1 /*
   2  * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
   3  * Scott McNutt <smcnutt@psyent.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*------------------------------------------------------------------------
  28  * BOARD/CPU
  29  *----------------------------------------------------------------------*/
  30 #define CONFIG_PK1C20           1               /* PK1C20 board         */
  31 #define CONFIG_SYS_CLK_FREQ     50000000        /* 50 MHz core clk      */
  32
  33 #define CONFIG_SYS_RESET_ADDR           0x00000000      /* Hard-reset address   */
  34 #define CONFIG_SYS_EXCEPTION_ADDR       0x01000020      /* Exception entry point*/
  35 #define CONFIG_SYS_NIOS_SYSID_BASE      0x021208b8      /* System id address    */
  36 #define CONFIG_BOARD_EARLY_INIT_F 1     /* enable early board-spec. init*/
  37
  38 /*------------------------------------------------------------------------
  39  * CACHE -- the following will support II/s and II/f. The II/s does not
  40  * have dcache, so the cache instructions will behave as NOPs.
  41  *----------------------------------------------------------------------*/
  42 #define CONFIG_SYS_ICACHE_SIZE          4096            /* 4 KByte total        */
  43 #define CONFIG_SYS_ICACHELINE_SIZE      32              /* 32 bytes/line        */
  44 #define CONFIG_SYS_DCACHE_SIZE          2048            /* 2 KByte (II/f)       */
  45 #define CONFIG_SYS_DCACHELINE_SIZE      4               /* 4 bytes/line (II/f)  */
  46
  47 /*------------------------------------------------------------------------
  48  * MEMORY BASE ADDRESSES
  49  *----------------------------------------------------------------------*/
  50 #define CONFIG_SYS_FLASH_BASE           0x00000000      /* FLASH base addr      */
  51 #define CONFIG_SYS_FLASH_SIZE           0x00800000      /* 8 MByte              */
  52 #define CONFIG_SYS_SDRAM_BASE           0x01000000      /* SDRAM base addr      */
  53 #define CONFIG_SYS_SDRAM_SIZE           0x01000000      /* 16 MByte             */
  54 #define CONFIG_SYS_SRAM_BASE            0x02000000      /* SRAM base addr       */
  55 #define CONFIG_SYS_SRAM_SIZE            0x00100000      /* 1 MB (only 1M mapped)*/
  56
  57 /*------------------------------------------------------------------------
  58  * MEMORY ORGANIZATION
  59  *      -Monitor at top.
  60  *      -The heap is placed below the monitor.
  61  *      -Global data is placed below the heap.
  62  *      -The stack is placed below global data (&grows down).
  63  *----------------------------------------------------------------------*/
  64 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 128k         */
  65 #define CONFIG_SYS_GBL_DATA_SIZE        128             /* Global data size rsvd*/
  66 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 128*1024)
  67
  68 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
  69 #define CONFIG_SYS_MALLOC_BASE          (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
  70 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
  71 #define CONFIG_SYS_INIT_SP              CONFIG_SYS_GBL_DATA_OFFSET
  72
  73 /*------------------------------------------------------------------------
  74  * FLASH (AM29LV065D)
  75  *----------------------------------------------------------------------*/
  76 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* Max # sects per bank */
  77 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* Max # of flash banks */
  78 #define CONFIG_SYS_FLASH_ERASE_TOUT     8000            /* Erase timeout (msec) */
  79 #define CONFIG_SYS_FLASH_WRITE_TOUT     100             /* Write timeout (msec) */
  80 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned char   /* flash word size      */
  81
  82 /*------------------------------------------------------------------------
  83  * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
  84  * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
  85  * reset address, no? This will keep the environment in user region
  86  * of flash. NOTE: the monitor length must be multiple of sector size
  87  * (which is common practice).
  88  *----------------------------------------------------------------------*/
  89 #define CONFIG_ENV_IS_IN_FLASH  1               /* Environment in flash */
  90 #define CONFIG_ENV_SIZE         (64 * 1024)     /* 64 KByte (1 sector)  */
  91 #define CONFIG_ENV_OVERWRITE                    /* Serial change Ok     */
  92 #define CONFIG_ENV_ADDR (CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN)
  93
  94 /*------------------------------------------------------------------------
  95  * CONSOLE
  96  *----------------------------------------------------------------------*/
  97 #define CONFIG_ALTERA_UART              1       /* Use altera uart */
  98 #if defined(CONFIG_ALTERA_JTAG_UART)
  99 #define CONFIG_SYS_NIOS_CONSOLE 0x021208b0      /* JTAG UART base addr  */
 100 #else
 101 #define CONFIG_SYS_NIOS_CONSOLE 0x02120840      /* UART base addr       */
 102 #endif
 103
 104 #define CONFIG_SYS_NIOS_FIXEDBAUD       1               /* Baudrate is fixed    */
 105 #define CONFIG_BAUDRATE         115200          /* Initial baudrate     */
 106 #define CONFIG_SYS_BAUDRATE_TABLE       {115200}        /* It's fixed ;-)       */
 107
 108 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1               /* Suppress console info*/
 109
 110 /*------------------------------------------------------------------------
 111  * EPCS Device -- wne CONFIG_SYS_NIOS_EPCSBASE is defined code/commands for
 112  * epcs device access is enabled. The base address is the epcs
 113  * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
 114  * The register base is currently at offset 0x600 from the memory base.
 115  *----------------------------------------------------------------------*/
 116 #define CONFIG_SYS_NIOS_EPCSBASE        0x02100200      /* EPCS register base   */
 117
 118 /*------------------------------------------------------------------------
 119  * DEBUG
 120  *----------------------------------------------------------------------*/
 121 #undef CONFIG_ROM_STUBS                         /* Stubs not in ROM     */
 122
 123 /*------------------------------------------------------------------------
 124  * TIMEBASE --
 125  *
 126  * The high res timer defaults to 1 msec. Since it includes the period
 127  * registers, the interrupt frequency can be reduced using TMRCNT.
 128  * If the default period is acceptable, TMRCNT can be left undefined.
 129  * TMRMS represents the desired mecs per tick (msecs per interrupt).
 130  *----------------------------------------------------------------------*/
 131 #define CONFIG_SYS_HZ                   1000    /* Always 1000 */
 132 #define CONFIG_SYS_NIOS_TMRBASE 0x02120820      /* Tick timer base addr */
 133 #define CONFIG_SYS_NIOS_TMRIRQ          3       /* Timer IRQ num */
 134 #define CONFIG_SYS_NIOS_TMRMS           10      /* Desired period */
 135 #define CONFIG_SYS_NIOS_TMRCNT \
 136                 (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
 137
 138 /*------------------------------------------------------------------------
 139  * STATUS LED -- Provides a simple blinking led. For Nios2 each board
 140  * must implement its own led routines -- leds are, after all,
 141  * board-specific, no?
 142  *----------------------------------------------------------------------*/
 143 #define CONFIG_SYS_LEDPIO_ADDR          0x02120870      /* LED PIO base addr    */
 144 #define CONFIG_STATUS_LED                       /* Enable status driver */
 145
 146 #define STATUS_LED_BIT          1               /* Bit-0 on PIO         */
 147 #define STATUS_LED_STATE        1               /* Blinking             */
 148 #define STATUS_LED_PERIOD       (500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec   */
 149
 150 /*------------------------------------------------------------------------
 151  * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
 152  * and really doesn't need any additional clutter. So I choose the lazy
 153  * way out to avoid changes there -- define the base address to ensure
 154  * cache bypass so there's no need to monkey with inx/outx macros.
 155  *----------------------------------------------------------------------*/
 156 #define CONFIG_SMC91111_BASE    0x82110300      /* Base addr (bypass)   */
 157 #define CONFIG_NET_MULTI
 158 #define CONFIG_SMC91111                 /* Using SMC91c111      */
 159 #undef  CONFIG_SMC91111_EXT_PHY                 /* Internal PHY         */
 160 #define CONFIG_SMC_USE_32_BIT                   /* 32-bit interface     */
 161
 162 #define CONFIG_ETHADDR          08:00:3e:26:0a:5b
 163 #define CONFIG_NETMASK          255.255.255.0
 164 #define CONFIG_IPADDR           192.168.2.21
 165 #define CONFIG_SERVERIP         192.168.2.16
 166
 167
 168 /*
 169  * BOOTP options
 170  */
 171 #define CONFIG_BOOTP_BOOTFILESIZE
 172 #define CONFIG_BOOTP_BOOTPATH
 173 #define CONFIG_BOOTP_GATEWAY
 174 #define CONFIG_BOOTP_HOSTNAME
 175
 176
 177 /*
 178  * Command line configuration.
 179  */
 180
 181 #define CONFIG_CMD_BDI
 182 #define CONFIG_CMD_DHCP
 183 #define CONFIG_CMD_ECHO
 184 #define CONFIG_CMD_SAVEENV
 185 #define CONFIG_CMD_FLASH
 186 #define CONFIG_CMD_IMI
 187 #define CONFIG_CMD_IRQ
 188 #define CONFIG_CMD_LOADS
 189 #define CONFIG_CMD_LOADB
 190 #define CONFIG_CMD_MEMORY
 191 #define CONFIG_CMD_MISC
 192 #define CONFIG_CMD_NET
 193 #define CONFIG_CMD_PING
 194 #define CONFIG_CMD_RUN
 195 #define CONFIG_CMD_SAVES
 196
 197
 198 /*------------------------------------------------------------------------
 199  * COMPACT FLASH
 200  *----------------------------------------------------------------------*/
 201 #if defined(CONFIG_CMD_IDE)
 202 #define CONFIG_IDE_PREINIT                      /* Implement id_preinit */
 203 #define CONFIG_SYS_IDE_MAXBUS           1               /* 1 IDE bus            */
 204 #define CONFIG_SYS_IDE_MAXDEVICE        1               /* 1 drive per IDE bus  */
 205
 206 #define CONFIG_SYS_ATA_BASE_ADDR        0x00900800      /* ATA base addr        */
 207 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000          /* IDE0 offset          */
 208 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0040          /* Data IO offset       */
 209 #define CONFIG_SYS_ATA_REG_OFFSET       0x0040          /* Register offset      */
 210 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100          /* Alternate reg offset */
 211 #define CONFIG_SYS_ATA_STRIDE          4                /* Width betwix addrs   */
 212 #define CONFIG_DOS_PARTITION
 213
 214 /* Board-specific cf regs */
 215 #define CONFIG_SYS_CF_PRESENT           0x00900880      /* CF Present PIO base  */
 216 #define CONFIG_SYS_CF_POWER             0x00900890      /* CF Power FET PIO base*/
 217 #define CONFIG_SYS_CF_ATASEL            0x009008a0      /* CF ATASEL PIO base   */
 218
 219 #endif
 220
 221 /*------------------------------------------------------------------------
 222  * JFFS2
 223  *----------------------------------------------------------------------*/
 224 #if defined(CONFIG_CMD_JFFS2)
 225 #define CONFIG_SYS_JFFS_CUSTOM_PART                     /* board defined part   */
 226 #endif
 227
 228 /*------------------------------------------------------------------------
 229  * MISC
 230  *----------------------------------------------------------------------*/
 231 #define CONFIG_SYS_LONGHELP                             /* Provide extended help*/
 232 #define CONFIG_SYS_PROMPT               "==> "          /* Command prompt       */
 233 #define CONFIG_SYS_CBSIZE               256             /* Console I/O buf size */
 234 #define CONFIG_SYS_MAXARGS              16              /* Max command args     */
 235 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot arg buf size    */
 236 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */
 237 #define CONFIG_SYS_LOAD_ADDR            CONFIG_SYS_SDRAM_BASE   /* Default load address */
 238 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE   /* Start addr for test  */
 239 #define CONFIG_SYS_MEMTEST_END          CONFIG_SYS_INIT_SP - 0x00020000
 240
 241 #define CONFIG_SYS_HUSH_PARSER
 242 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 243
 244 #endif  /* __CONFIG_H */