include/configs/PLU405.h

   1 /*
   2  * (C) Copyright 2001-2003
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  37 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  38 #define CONFIG_PLU405           1       /* ...on a PLU405 board         */
  39
  40 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  41 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  42
  43 #define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */
  44
  45 #define CONFIG_BAUDRATE         9600
  46
  47 #undef  CONFIG_BOOTARGS
  48 #undef  CONFIG_BOOTCOMMAND
  49
  50 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  51
  52 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
  53
  54 #define CONFIG_NET_MULTI        1
  55 #undef  CONFIG_HAS_ETH1
  56
  57 #define CONFIG_MII              1       /* MII PHY management           */
  58 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  59 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  60 #define CONFIG_RESET_PHY_R      1       /* use reset_phy()              */
  61
  62 #define CONFIG_PHY_CLK_FREQ     EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
  63
  64
  65 /*
  66  * BOOTP options
  67  */
  68 #define CONFIG_BOOTP_BOOTFILESIZE
  69 #define CONFIG_BOOTP_BOOTPATH
  70 #define CONFIG_BOOTP_GATEWAY
  71 #define CONFIG_BOOTP_HOSTNAME
  72
  73
  74 /*
  75  * Command line configuration.
  76  */
  77 #include <config_cmd_default.h>
  78
  79 #define CONFIG_CMD_DHCP
  80 #define CONFIG_CMD_PCI
  81 #define CONFIG_CMD_IRQ
  82 #define CONFIG_CMD_IDE
  83 #define CONFIG_CMD_FAT
  84 #define CONFIG_CMD_ELF
  85 #define CONFIG_CMD_NAND
  86 #define CONFIG_CMD_DATE
  87 #define CONFIG_CMD_I2C
  88 #define CONFIG_CMD_MII
  89 #define CONFIG_CMD_PING
  90 #define CONFIG_CMD_EEPROM
  91 #define CONFIG_CMD_USB
  92
  93 #define CONFIG_OF_LIBFDT
  94 #define CONFIG_OF_BOARD_SETUP
  95
  96 #define CONFIG_MAC_PARTITION
  97 #define CONFIG_DOS_PARTITION
  98
  99 #define CONFIG_SUPPORT_VFAT
 100
 101 #define CONFIG_AUTO_UPDATE      1       /* autoupdate via compactflash  */
 102
 103 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 104
 105 #define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
 106 #define CFG_RTC_REG_BASE_ADDR    0xF0000500 /* RTC Base Address         */
 107
 108 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
 109
 110 /*
 111  * Miscellaneous configurable options
 112  */
 113 #define CFG_LONGHELP                    /* undef to save memory         */
 114 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 115
 116 #undef  CFG_HUSH_PARSER                 /* use "hush" command parser    */
 117 #ifdef  CFG_HUSH_PARSER
 118 #define CFG_PROMPT_HUSH_PS2     "> "
 119 #endif
 120
 121 #if defined(CONFIG_CMD_KGDB)
 122 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 123 #else
 124 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 125 #endif
 126 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 127 #define CFG_MAXARGS     16              /* max number of command args   */
 128 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 129
 130 #define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
 131
 132 #define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
 133
 134 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
 135
 136 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 137 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 138
 139 #undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
 140 #define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
 141 #define CFG_BASE_BAUD       691200
 142 #undef  CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
 143
 144 /* The following table includes the supported baudrates */
 145 #define CFG_BAUDRATE_TABLE      \
 146         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 147          57600, 115200, 230400, 460800, 921600 }
 148
 149 #define CFG_LOAD_ADDR   0x100000        /* default load address */
 150 #define CFG_EXTBDINFO   1               /* To use extended board_into (bd_t) */
 151
 152 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 153
 154 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 155 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 156 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
 157
 158 /* Only interrupt boot if space is pressed */
 159 /* If a long serial cable is connected but */
 160 /* other end is dead, garbage will be read */
 161 #define CONFIG_AUTOBOOT_KEYED   1
 162 #define CONFIG_AUTOBOOT_PROMPT  \
 163         "Press SPACE to abort autoboot in %d seconds\n", bootdelay
 164 #undef CONFIG_AUTOBOOT_DELAY_STR
 165 #define CONFIG_AUTOBOOT_STOP_STR " "
 166
 167 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 168
 169 #define CFG_RX_ETH_BUFFER       16      /* use 16 rx buffer on 405 emac */
 170
 171 /*
 172  * NAND-FLASH stuff
 173  */
 174 #define CFG_NAND_BASE_LIST      {CFG_NAND_BASE}
 175 #define NAND_MAX_CHIPS          1
 176 #define CFG_MAX_NAND_DEVICE     1         /* Max number of NAND devices */
 177 #define NAND_BIG_DELAY_US       25
 178
 179 #define CFG_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
 180 #define CFG_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
 181 #define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
 182 #define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 183
 184 #define CFG_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
 185 #define CFG_NAND_QUIET          1
 186
 187 /*
 188  * PCI stuff
 189  */
 190 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 191 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 192 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 193
 194 #define CONFIG_PCI                      /* include pci support          */
 195 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 196 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 197                                         /* resource configuration       */
 198
 199 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 200
 201 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 202
 203 #define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 204 #define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
 205 #define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
 206 #define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
 207 #define CFG_PCI_PTM1MS  0xf8000001      /* 128MB, enable hard-wired to 1 */
 208 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 209 #define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
 210 #define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
 211 #define CFG_PCI_PTM2PCI 0x08000000      /* Host: use this pci address   */
 212
 213 /*
 214  * IDE/ATA stuff
 215  */
 216 #undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
 217 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 218 #define CONFIG_IDE_RESET        1       /* reset for ide supported      */
 219
 220 #define CFG_IDE_MAXBUS          1               /* max. 1 IDE busses    */
 221 /* max. 1 drives per IDE bus */
 222 #define CFG_IDE_MAXDEVICE       (CFG_IDE_MAXBUS*1)
 223
 224 #define CFG_ATA_BASE_ADDR       0xF0100000
 225 #define CFG_ATA_IDE0_OFFSET     0x0000
 226
 227 #define CFG_ATA_DATA_OFFSET     0x0000  /* Offset for data I/O */
 228 #define CFG_ATA_REG_OFFSET      0x0000  /* Offset for normal register access */
 229 #define CFG_ATA_ALT_OFFSET      0x0000  /* Offset for alternate registers */
 230
 231 /*
 232  * For booting Linux, the board info and command line data
 233  * have to be in the first 8 MB of memory, since this is
 234  * the maximum mapped by the Linux kernel during initialization.
 235  */
 236 #define CFG_BOOTMAPSZ           (8 << 20) /* Initial Memory map for Linux */
 237
 238 /*
 239  * FLASH organization
 240  */
 241 #define FLASH_BASE0_PRELIM      0xFFC00000 /* FLASH bank #0 */
 242
 243 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks */
 244 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip */
 245
 246 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms) */
 247 #define CFG_FLASH_WRITE_TOUT    1000    /* Timeout for Flash Write (in ms) */
 248
 249 #define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width) */
 250 #define CFG_FLASH_ADDR0         0x5555  /* 1st addr for flash config cycles */
 251 #define CFG_FLASH_ADDR1         0x2AAA  /* 2nd addr for flash config cycles */
 252 /*
 253  * The following defines are added for buggy IOP480 byte interface.
 254  * All other boards should use the standard values (CPCI405 etc.)
 255  */
 256 #define CFG_FLASH_READ0         0x0000  /* 0 is standard */
 257 #define CFG_FLASH_READ1         0x0001  /* 1 is standard */
 258 #define CFG_FLASH_READ2         0x0002  /* 2 is standard */
 259
 260 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector */
 261
 262 /*
 263  * Start addresses for the final memory configuration
 264  * (Set up by the startup code)
 265  * Please note that CFG_SDRAM_BASE _must_ start at 0
 266  */
 267 #define CFG_SDRAM_BASE          0x00000000
 268 #define CFG_FLASH_BASE          0xFFFA0000
 269 #define CFG_MONITOR_BASE        TEXT_BASE
 270 #define CFG_MONITOR_LEN         (384 * 1024)    /* Reserve 384kB for Monitor */
 271 #define CFG_MALLOC_LEN          (384 * 1024)    /* Reserve 384kB for malloc() */
 272
 273 /*
 274  * Environment Variable setup
 275  */
 276 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 277 #define CFG_ENV_OFFSET          0x100   /* reseve 0x100 bytes for strapping */
 278 #define CFG_ENV_SIZE            0x700
 279
 280 /*
 281  * I2C EEPROM (24WC16) for environment
 282  */
 283 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 284 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 285 #define CFG_I2C_SLAVE           0x7F
 286
 287 #define CFG_I2C_EEPROM_ADDR     0x50    /* EEPROM 24WC16 */
 288 #define CFG_EEPROM_WREN         1
 289
 290 /* 24WC16 */
 291 #define CFG_I2C_EEPROM_ADDR_LEN 1       /* Bytes of address             */
 292 /* mask of address bits that overflow into the "EEPROM chip address"    */
 293 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x07
 294 #define CFG_EEPROM_PAGE_WRITE_BITS 4    /* The 24WC16 has   */
 295                                         /* 16 byte page write mode using */
 296                                         /* last 4 bits of the address   */
 297 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10   /* and takes up to 10 msec */
 298 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 299
 300 /*
 301  * External Bus Controller (EBC) Setup
 302  */
 303 #define CAN_BA          0xF0000000          /* CAN Base Address         */
 304 #define DUART0_BA       0xF0000400          /* DUART Base Address       */
 305 #define DUART1_BA       0xF0000408          /* DUART Base Address       */
 306 #define RTC_BA          0xF0000500          /* RTC Base Address         */
 307 #define VGA_BA          0xF1000000          /* Epson VGA Base Address   */
 308 #define CFG_NAND_BASE   0xF4000000          /* NAND FLASH Base Address  */
 309
 310 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
 311 /* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
 312 #define CFG_EBC_PB0AP           0x92015480
 313 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 314 #define CFG_EBC_PB0CR           0xFFC5A000
 315
 316 /* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
 317 #define CFG_EBC_PB1AP           0x92015480
 318 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
 319 #define CFG_EBC_PB1CR           0xF4018000
 320
 321 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
 322 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 323 #define CFG_EBC_PB2AP           0x010053C0
 324 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
 325 #define CFG_EBC_PB2CR           0xF0018000
 326
 327 /* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
 328 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 329 #define CFG_EBC_PB3AP           0x010053C0
 330 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 331 #define CFG_EBC_PB3CR           0xF011A000
 332
 333 /*
 334  * FPGA stuff
 335  */
 336 #define CFG_FPGA_BASE_ADDR 0xF0100100       /* FPGA internal Base Address */
 337
 338 /* FPGA internal regs */
 339 #define CFG_FPGA_CTRL           0x000
 340
 341 /* FPGA Control Reg */
 342 #define CFG_FPGA_CTRL_CF_RESET  0x0001
 343 #define CFG_FPGA_CTRL_WDI       0x0002
 344 #define CFG_FPGA_CTRL_PS2_RESET 0x0020
 345
 346 #define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now */
 347 #define CFG_FPGA_MAX_SIZE       128*1024    /* 128kByte is enough for XC2S50E*/
 348
 349 /* FPGA program pin configuration */
 350 #define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
 351 #define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output) */
 352 #define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output) */
 353 #define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input) */
 354 #define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input) */
 355
 356 /*
 357  * Definitions for initial stack pointer and data area (in data cache)
 358  */
 359 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 360 #define CFG_TEMP_STACK_OCM        1
 361
 362 /* On Chip Memory location */
 363 #define CFG_OCM_DATA_ADDR       0xF8000000
 364 #define CFG_OCM_DATA_SIZE       0x1000
 365 #define CFG_INIT_RAM_ADDR       CFG_OCM_DATA_ADDR /* inside of SDRAM */
 366 #define CFG_INIT_RAM_END        CFG_OCM_DATA_SIZE /* End of used area in RAM  */
 367
 368 #define CFG_GBL_DATA_SIZE      128 /* size in bytes reserved for initial data */
 369 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 370 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 371
 372 /*
 373  * Definitions for GPIO setup (PPC405EP specific)
 374  *
 375  * GPIO0[0]     - External Bus Controller BLAST output
 376  * GPIO0[1-9]   - Instruction trace outputs -> GPIO
 377  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 378  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 379  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 380  * GPIO0[24-27] - UART0 control signal inputs/outputs
 381  * GPIO0[28-29] - UART1 data signal input/output
 382  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 383  */
 384 #define CFG_GPIO0_OSRH          0x00000550
 385 #define CFG_GPIO0_OSRL          0x00000110
 386 #define CFG_GPIO0_ISR1H         0x00000000
 387 #define CFG_GPIO0_ISR1L         0x15555445
 388 #define CFG_GPIO0_TSRH          0x00000000
 389 #define CFG_GPIO0_TSRL          0x00000000
 390 #define CFG_GPIO0_TCR           0x77FE0014
 391
 392 #define CFG_DUART_RST           (0x80000000 >> 14)
 393 #define CFG_EEPROM_WP           (0x80000000 >> 0)
 394
 395 /*
 396  * Internal Definitions
 397  *
 398  * Boot Flags
 399  */
 400 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 401 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 402
 403 /*
 404  * Default speed selection (cpu_plb_opb_ebc) in MHz.
 405  * This value will be set if iic boot eprom is disabled.
 406  */
 407 #if 1
 408 #define PLLMR0_DEFAULT   PLLMR0_266_133_66_33
 409 #define PLLMR1_DEFAULT   PLLMR1_266_133_66_33
 410 #endif
 411 #if 0
 412 #define PLLMR0_DEFAULT   PLLMR0_200_100_50_33
 413 #define PLLMR1_DEFAULT   PLLMR1_200_100_50_33
 414 #endif
 415 #if 0
 416 #define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
 417 #define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
 418 #endif
 419
 420 /*
 421  * PCI OHCI controller
 422  */
 423 #define CONFIG_USB_OHCI_NEW     1
 424 #define CONFIG_PCI_OHCI         1
 425 #define CFG_OHCI_SWAP_REG_ACCESS 1
 426 #define CFG_USB_OHCI_MAX_ROOT_PORTS 15
 427 #define CFG_USB_OHCI_SLOT_NAME  "ohci_pci"
 428 #define CONFIG_USB_STORAGE      1
 429
 430 #endif  /* __CONFIG_H */