include/configs/PM520.h

   1 /*
   2  * (C) Copyright 2003-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * High Level Configuration Options
  29  * (easy to change)
  30  */
  31
  32 #define CONFIG_MPC5200
  33 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU */
  34 #define CONFIG_PM520            1       /* ... on PM520 board */
  35
  36 #define CFG_MPC5XXX_CLKIN       33000000 /* ... running at 33MHz */
  37
  38 #define CONFIG_MISC_INIT_R
  39
  40 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH  */
  41 #define BOOTFLAG_WARM           0x02    /* Software reboot           */
  42
  43 /*
  44  * Serial console configuration
  45  */
  46 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  47 #define CONFIG_BAUDRATE         9600    /* ... at 9600 bps */
  48 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
  49
  50
  51 #ifdef CONFIG_MPC5200   /* MPC5100 PCI is not supported yet. */
  52 /*
  53  * PCI Mapping:
  54  * 0x40000000 - 0x4fffffff - PCI Memory
  55  * 0x50000000 - 0x50ffffff - PCI IO Space
  56  */
  57 #define CONFIG_PCI              1
  58 #define CONFIG_PCI_PNP          1
  59 #define CONFIG_PCI_SCAN_SHOW    1
  60 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  61
  62 #define CONFIG_PCI_MEM_BUS      0x40000000
  63 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  64 #define CONFIG_PCI_MEM_SIZE     0x10000000
  65
  66 #define CONFIG_PCI_IO_BUS       0x50000000
  67 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  68 #define CONFIG_PCI_IO_SIZE      0x01000000
  69
  70 #define CONFIG_NET_MULTI        1
  71 #define CONFIG_MII              1
  72 #define CONFIG_EEPRO100         1
  73 #define CFG_RX_ETH_BUFFER       8  /* use 8 rx buffer on eepro100  */
  74 #undef  CONFIG_NS8382X
  75
  76 #endif
  77
  78 /* Partitions */
  79 #define CONFIG_DOS_PARTITION
  80
  81 /* USB */
  82 #if 1
  83 #define CONFIG_USB_OHCI
  84 #define CONFIG_USB_STORAGE
  85 #endif
  86
  87 #if !defined(CONFIG_BOOT_ROM)
  88 /* DoC requires legacy NAND for now */
  89 #define CFG_NAND_LEGACY
  90 #endif
  91
  92
  93 /*
  94  * BOOTP options
  95  */
  96 #define CONFIG_BOOTP_BOOTFILESIZE
  97 #define CONFIG_BOOTP_BOOTPATH
  98 #define CONFIG_BOOTP_GATEWAY
  99 #define CONFIG_BOOTP_HOSTNAME
 100
 101
 102 /*
 103  * Command line configuration.
 104  */
 105 #include <config_cmd_default.h>
 106
 107 #define CONFIG_CMD_BEDBUG
 108 #define CONFIG_CMD_DATE
 109 #define CONFIG_CMD_DHCP
 110 #define CONFIG_CMD_EEPROM
 111 #define CONFIG_CMD_FAT
 112 #define CONFIG_CMD_I2C
 113 #define CONFIG_CMD_IDE
 114 #define CONFIG_CMD_NFS
 115 #define CONFIG_CMD_SNTP
 116 #define CONFIG_CMD_USB
 117
 118 #if !defined(CONFIG_BOOT_ROM)
 119 #define CONFIG_CMD_DOC
 120 #endif
 121
 122 #if defined(CONFIG_MPC5200)
 123 #define CONFIG_CMD_PCI
 124 #endif
 125
 126
 127 /*
 128  * Autobooting
 129  */
 130 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 131
 132 #define CONFIG_PREBOOT  "echo;" \
 133         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 134         "echo"
 135
 136 #undef  CONFIG_BOOTARGS
 137
 138 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 139         "netdev=eth0\0"                                                 \
 140         "hostname=pm520\0"                                                      \
 141         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 142                 "nfsroot=${serverip}:${rootpath}\0"                     \
 143         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 144         "addip=setenv bootargs ${bootargs} "                            \
 145                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 146                 ":${hostname}:${netdev}:off panic=1\0"                  \
 147         "flash_nfs=run nfsargs addip;"                                  \
 148                 "bootm ${kernel_addr}\0"                                \
 149         "flash_self=run ramargs addip;"                                 \
 150                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 151         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
 152         "rootpath=/opt/eldk30/ppc_82xx\0"                                       \
 153         "bootfile=/tftpboot/PM520/uImage\0"                             \
 154         ""
 155
 156 #define CONFIG_BOOTCOMMAND      "run flash_self"
 157
 158 #if defined(CONFIG_MPC5200)
 159 /*
 160  * IPB Bus clocking configuration.
 161  */
 162 #undef CFG_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
 163 #endif
 164 /*
 165  * I2C configuration
 166  */
 167 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 168 #define CFG_I2C_MODULE          2       /* Select I2C module #1 or #2 */
 169
 170 #define CFG_I2C_SPEED           100000 /* 100 kHz */
 171 #define CFG_I2C_SLAVE           0x7F
 172
 173 /*
 174  * EEPROM configuration
 175  */
 176 #define CFG_I2C_EEPROM_ADDR             0x58
 177 #define CFG_I2C_EEPROM_ADDR_LEN         1
 178 #define CFG_EEPROM_PAGE_WRITE_BITS      4
 179 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10
 180
 181 /*
 182  * RTC configuration
 183  */
 184 #define CONFIG_RTC_PCF8563
 185 #define CFG_I2C_RTC_ADDR                0x51
 186
 187 /*
 188  * Disk-On-Chip configuration
 189  */
 190
 191 #define CFG_DOC_SHORT_TIMEOUT
 192 #define CFG_MAX_DOC_DEVICE      1       /* Max number of DOC devices    */
 193
 194 #define CFG_DOC_SUPPORT_2000
 195 #define CFG_DOC_SUPPORT_MILLENNIUM
 196 #define CFG_DOC_BASE            0xE0000000
 197 #define CFG_DOC_SIZE            0x00100000
 198
 199 #if defined(CONFIG_BOOT_ROM)
 200 /*
 201  * Flash configuration (8,16 or 32 MB)
 202  * TEXT base always at 0xFFF00000
 203  * ENV_ADDR always at  0xFFF40000
 204  * FLASH_BASE at 0xFA000000 for 64 MB
 205  *               0xFC000000 for 32 MB
 206  *               0xFD000000 for 16 MB
 207  *               0xFD800000 for  8 MB
 208  */
 209 #define CFG_FLASH_BASE          0xFA000000
 210 #define CFG_FLASH_SIZE          0x04000000
 211 #define CFG_BOOTROM_BASE        0xFFF00000
 212 #define CFG_BOOTROM_SIZE        0x00080000
 213 #define CFG_ENV_ADDR            (0xFDF00000 + 0x40000)
 214 #else
 215 /*
 216  * Flash configuration (8,16 or 32 MB)
 217  * TEXT base always at 0xFFF00000
 218  * ENV_ADDR always at  0xFFF40000
 219  * FLASH_BASE at 0xFC000000 for 64 MB
 220  *               0xFE000000 for 32 MB
 221  *               0xFF000000 for 16 MB
 222  *               0xFF800000 for  8 MB
 223  */
 224 #define CFG_FLASH_BASE          0xFC000000
 225 #define CFG_FLASH_SIZE          0x04000000
 226 #define CFG_ENV_ADDR            (0xFFF00000 + 0x40000)
 227 #endif
 228 #define CFG_MAX_FLASH_BANKS     1       /* max num of memory banks      */
 229
 230 #define CFG_MAX_FLASH_SECT      256     /* max num of sects on one chip */
 231
 232 #define CFG_FLASH_ERASE_TOUT    240000  /* Flash Erase Timeout (in ms)  */
 233 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 234 #define CFG_FLASH_LOCK_TOUT     5       /* Timeout for Flash Set Lock Bit (in ms) */
 235 #define CFG_FLASH_UNLOCK_TOUT   10000   /* Timeout for Flash Clear Lock Bits (in ms) */
 236 #define CFG_FLASH_PROTECTION            /* "Real" (hardware) sectors protection */
 237
 238 #define PHYS_FLASH_SECT_SIZE    0x00040000 /* 256 KB sectors (x2) */
 239
 240 #undef CONFIG_FLASH_16BIT       /* Flash is 32-bit */
 241
 242
 243 /*
 244  * Environment settings
 245  */
 246 #define CFG_ENV_IS_IN_FLASH     1
 247 #define CFG_ENV_SIZE            0x10000
 248 #define CFG_ENV_SECT_SIZE       0x40000
 249 #define CONFIG_ENV_OVERWRITE    1
 250
 251 /*
 252  * Memory map
 253  */
 254 #define CFG_MBAR                0xf0000000
 255 #define CFG_SDRAM_BASE          0x00000000
 256 #define CFG_DEFAULT_MBAR        0x80000000
 257
 258 /* Use SRAM until RAM will be available */
 259 #define CFG_INIT_RAM_ADDR       MPC5XXX_SRAM
 260 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_SIZE       /* End of used area in DPRAM */
 261
 262
 263 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 264 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 265 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 266
 267 #define CFG_MONITOR_BASE    TEXT_BASE
 268 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 269 #   define CFG_RAMBOOT          1
 270 #endif
 271
 272 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 273 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 274 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 275
 276 /*
 277  * Ethernet configuration
 278  */
 279 #define CONFIG_MPC5xxx_FEC      1
 280 /*
 281  * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 282  */
 283 /* #define CONFIG_FEC_10MBIT 1 */
 284 #define CONFIG_PHY_ADDR         0x00
 285
 286 /*
 287  * GPIO configuration
 288  */
 289 #define CFG_GPS_PORT_CONFIG     0x10000004
 290
 291 /*
 292  * Miscellaneous configurable options
 293  */
 294 #define CFG_LONGHELP                    /* undef to save memory     */
 295 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt   */
 296 #if defined(CONFIG_CMD_KGDB)
 297 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size  */
 298 #else
 299 #define CFG_CBSIZE              256     /* Console I/O Buffer Size  */
 300 #endif
 301 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size */
 302 #define CFG_MAXARGS             16              /* max number of command args   */
 303 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 304
 305 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 306 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
 307
 308 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 309
 310 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 311
 312 #define CFG_CACHELINE_SIZE      32      /* For MPC5xxx CPUs */
 313 #if defined(CONFIG_CMD_KGDB)
 314 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
 315 #endif
 316
 317 /*
 318  * Various low-level settings
 319  */
 320 #if defined(CONFIG_MPC5200)
 321 #define CFG_HID0_INIT           HID0_ICE | HID0_ICFI
 322 #define CFG_HID0_FINAL          HID0_ICE
 323 #else
 324 #define CFG_HID0_INIT           0
 325 #define CFG_HID0_FINAL          0
 326 #endif
 327
 328 #if defined(CONFIG_BOOT_ROM)
 329 #define CFG_BOOTCS_START        CFG_BOOTROM_BASE
 330 #define CFG_BOOTCS_SIZE         CFG_BOOTROM_SIZE
 331 #define CFG_BOOTCS_CFG          0x00047800
 332 #define CFG_CS0_START           CFG_BOOTROM_BASE
 333 #define CFG_CS0_SIZE            CFG_BOOTROM_SIZE
 334 #define CFG_CS1_START           CFG_FLASH_BASE
 335 #define CFG_CS1_SIZE            CFG_FLASH_SIZE
 336 #define CFG_CS1_CFG             0x0004FF00
 337 #else
 338 #define CFG_BOOTCS_START        CFG_FLASH_BASE
 339 #define CFG_BOOTCS_SIZE         CFG_FLASH_SIZE
 340 #define CFG_BOOTCS_CFG          0x0004FF00
 341 #define CFG_CS0_START           CFG_FLASH_BASE
 342 #define CFG_CS0_SIZE            CFG_FLASH_SIZE
 343 #define CFG_CS1_START           CFG_DOC_BASE
 344 #define CFG_CS1_SIZE            CFG_DOC_SIZE
 345 #define CFG_CS1_CFG             0x00047800
 346 #endif
 347
 348 #define CFG_CS_BURST            0x00000000
 349 #define CFG_CS_DEADCYCLE        0x33333333
 350
 351 #define CFG_RESET_ADDRESS       0xff000000
 352
 353 /*-----------------------------------------------------------------------
 354  * USB stuff
 355  *-----------------------------------------------------------------------
 356  */
 357 #define CONFIG_USB_CLOCK        0x0001BBBB
 358 #define CONFIG_USB_CONFIG       0x00005000
 359
 360 /*-----------------------------------------------------------------------
 361  * IDE/ATA stuff Supports IDE harddisk
 362  *-----------------------------------------------------------------------
 363  */
 364
 365 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 366
 367 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 368 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 369
 370 #undef  CONFIG_IDE_RESET                /* reset for ide supported      */
 371 #define CONFIG_IDE_PREINIT
 372
 373 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 374 #define CFG_IDE_MAXDEVICE       2       /* max. 2 drive per IDE bus     */
 375
 376 #define CFG_ATA_IDE0_OFFSET     0x0000
 377
 378 #define CFG_ATA_BASE_ADDR       MPC5XXX_ATA
 379
 380 /* Offset for data I/O                  */
 381 #define CFG_ATA_DATA_OFFSET     (0x0060)
 382
 383 /* Offset for normal register accesses  */
 384 #define CFG_ATA_REG_OFFSET      (CFG_ATA_DATA_OFFSET)
 385
 386 /* Offset for alternate registers       */
 387 #define CFG_ATA_ALT_OFFSET      (0x005C)
 388
 389 /* Interval between registers                                                */
 390 #define CFG_ATA_STRIDE          4
 391
 392 #endif /* __CONFIG_H */