include/configs/PM828.h

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 #undef CONFIG_SYS_RAMBOOT
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37
  38 #define CONFIG_MPC8260          1       /* This is a MPC8260 CPU        */
  39 #define CONFIG_PM828            1       /* ...on a PM828 module */
  40 #define CONFIG_CPM2             1       /* Has a CPM2 */
  41
  42 #ifndef CONFIG_SYS_TEXT_BASE
  43 #define CONFIG_SYS_TEXT_BASE    0x40000000      /* Standard: boot 64-bit flash */
  44 #endif
  45
  46 #undef CONFIG_DB_CR826_J30x_ON          /* J30x jumpers on D.B. carrier */
  47
  48 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  49
  50 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  51
  52 #undef  CONFIG_BOOTARGS
  53 #define CONFIG_BOOTCOMMAND                                                      \
  54         "bootp;"                                                                \
  55         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
  56         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"    \
  57         "bootm"
  58
  59 /* enable I2C and select the hardware/software driver */
  60 #define CONFIG_SYS_I2C
  61 #define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
  62 #define CONFIG_SYS_I2C_SOFT_SPEED       50000
  63 #define CONFIG_SYS_I2C_SOFT_SLAVE       0xFE
  64 /*
  65  * Software (bit-bang) I2C driver configuration
  66  */
  67 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
  68 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
  69 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
  70 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
  71 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
  72                         else    iop->pdat &= ~0x00010000
  73 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
  74                         else    iop->pdat &= ~0x00020000
  75 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
  76
  77
  78 #define CONFIG_RTC_PCF8563
  79 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
  80
  81 /*
  82  * select serial console configuration
  83  *
  84  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  85  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  86  * for SCC).
  87  *
  88  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  89  * defined elsewhere (for example, on the cogent platform, there are serial
  90  * ports on the motherboard which are used for the serial console - see
  91  * cogent/cma101/serial.[ch]).
  92  */
  93 #define CONFIG_CONS_ON_SMC              /* define if console on SMC */
  94 #undef  CONFIG_CONS_ON_SCC              /* define if console on SCC */
  95 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
  96 #define CONFIG_CONS_INDEX       2       /* which serial channel for console */
  97
  98 /*
  99  * select ethernet configuration
 100  *
 101  * if CONFIG_ETHER_ON_SCC is selected, then
 102  *   - CONFIG_ETHER_INDEX must be set to the channel number (1-4)
 103  *
 104  * if CONFIG_ETHER_ON_FCC is selected, then
 105  *   - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected
 106  *
 107  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 108  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 109  */
 110 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 111
 112 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
 113 #define CONFIG_ETHER_INDEX    1         /* which SCC channel for ethernet */
 114
 115 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
 116 /*
 117  * - Rx-CLK is CLK11
 118  * - Tx-CLK is CLK10
 119  */
 120 #define CONFIG_ETHER_ON_FCC1
 121 # define CONFIG_SYS_CMXFCR_MASK1        (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
 122 #ifndef CONFIG_DB_CR826_J30x_ON
 123 # define CONFIG_SYS_CMXFCR_VALUE1       (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
 124 #else
 125 # define CONFIG_SYS_CMXFCR_VALUE1       (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
 126 #endif
 127 /*
 128  * - Rx-CLK is CLK15
 129  * - Tx-CLK is CLK14
 130  */
 131 #define CONFIG_ETHER_ON_FCC2
 132 # define CONFIG_SYS_CMXFCR_MASK2        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
 133 # define CONFIG_SYS_CMXFCR_VALUE2       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 134 /*
 135  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 136  * - Enable Full Duplex in FSMR
 137  */
 138 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
 139 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
 140
 141 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 142 #define CONFIG_8260_CLKIN       100000000       /* in Hz */
 143
 144 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
 145 #define CONFIG_BAUDRATE         230400
 146 #else
 147 #define CONFIG_BAUDRATE         9600
 148 #endif
 149
 150 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 151 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
 152
 153 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 154
 155 /*
 156  * BOOTP options
 157  */
 158 #define CONFIG_BOOTP_SUBNETMASK
 159 #define CONFIG_BOOTP_GATEWAY
 160 #define CONFIG_BOOTP_HOSTNAME
 161 #define CONFIG_BOOTP_BOOTPATH
 162 #define CONFIG_BOOTP_BOOTFILESIZE
 163
 164
 165 /*
 166  * Command line configuration.
 167  */
 168 #include <config_cmd_default.h>
 169
 170 #define CONFIG_CMD_BEDBUG
 171 #define CONFIG_CMD_DATE
 172 #define CONFIG_CMD_DHCP
 173 #define CONFIG_CMD_EEPROM
 174 #define CONFIG_CMD_I2C
 175 #define CONFIG_CMD_NFS
 176 #define CONFIG_CMD_SNTP
 177
 178 #ifdef CONFIG_PCI
 179 #define CONFIG_PCI_INDIRECT_BRIDGE
 180 #define CONFIG_CMD_PCI
 181 #endif
 182
 183 /*
 184  * Miscellaneous configurable options
 185  */
 186 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 187 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 188 #if defined(CONFIG_CMD_KGDB)
 189 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 190 #else
 191 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 192 #endif
 193 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 194 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 195 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 196
 197 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 198 #define CONFIG_SYS_MEMTEST_END 0x0C00000        /* 4 ... 12 MB in DRAM  */
 199
 200 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 201
 202 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 203
 204 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC     /* "bad" address                */
 205
 206 /*
 207  * For booting Linux, the board info and command line data
 208  * have to be in the first 8 MB of memory, since this is
 209  * the maximum mapped by the Linux kernel during initialization.
 210  */
 211 #define CONFIG_SYS_BOOTMAPSZ         (8 << 20)       /* Initial Memory map for Linux */
 212
 213 /*-----------------------------------------------------------------------
 214  * Flash and Boot ROM mapping
 215  */
 216
 217 #define CONFIG_SYS_BOOTROM_BASE 0xFF800000
 218 #define CONFIG_SYS_BOOTROM_SIZE 0x00080000
 219 #define CONFIG_SYS_FLASH0_BASE          0x40000000
 220 #define CONFIG_SYS_FLASH0_SIZE          0x02000000
 221 #define CONFIG_SYS_DOC_BASE             0xFF800000
 222 #define CONFIG_SYS_DOC_SIZE             0x00100000
 223
 224
 225 /* Flash bank size (for preliminary settings)
 226  */
 227 #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
 228
 229 /*-----------------------------------------------------------------------
 230  * FLASH organization
 231  */
 232 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks      */
 233 #define CONFIG_SYS_MAX_FLASH_SECT       135     /* max num of sects on one chip */
 234
 235 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 236 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 237
 238 #if 0
 239 /* Start port with environment in flash; switch to EEPROM later */
 240 #define CONFIG_ENV_IS_IN_FLASH  1
 241 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE+0x40000)
 242 #define CONFIG_ENV_SIZE         0x40000
 243 #define CONFIG_ENV_SECT_SIZE    0x40000
 244 #else
 245 /* Final version: environment in EEPROM */
 246 #define CONFIG_ENV_IS_IN_EEPROM 1
 247 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x58
 248 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 249 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 250 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 251 #define CONFIG_ENV_OFFSET               512
 252 #define CONFIG_ENV_SIZE         (2048 - 512)
 253 #endif
 254
 255 /*-----------------------------------------------------------------------
 256  * Hard Reset Configuration Words
 257  *
 258  * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 259  * defines for the various registers affected by the HRCW e.g. changing
 260  * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 261  */
 262 #if defined(CONFIG_BOOT_ROM)
 263 #define CONFIG_SYS_HRCW_MASTER          (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
 264 #else
 265 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
 266 #endif
 267
 268 /* no slaves so just fill with zeros */
 269 #define CONFIG_SYS_HRCW_SLAVE1          0
 270 #define CONFIG_SYS_HRCW_SLAVE2          0
 271 #define CONFIG_SYS_HRCW_SLAVE3          0
 272 #define CONFIG_SYS_HRCW_SLAVE4          0
 273 #define CONFIG_SYS_HRCW_SLAVE5          0
 274 #define CONFIG_SYS_HRCW_SLAVE6          0
 275 #define CONFIG_SYS_HRCW_SLAVE7          0
 276
 277 /*-----------------------------------------------------------------------
 278  * Internal Memory Mapped Register
 279  */
 280 #define CONFIG_SYS_IMMR         0xF0000000
 281
 282 /*-----------------------------------------------------------------------
 283  * Definitions for initial stack pointer and data area (in DPRAM)
 284  */
 285 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 286 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000  /* Size of used area in DPRAM   */
 287 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 288 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 289
 290 /*-----------------------------------------------------------------------
 291  * Start addresses for the final memory configuration
 292  * (Set up by the startup code)
 293  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 294  *
 295  * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM
 296  * is mapped at SDRAM_BASE2_PRELIM.
 297  */
 298 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 299 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_FLASH0_BASE
 300 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 301 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 302 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()*/
 303
 304 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 305 # define CONFIG_SYS_RAMBOOT
 306 #endif
 307
 308 #ifdef  CONFIG_PCI
 309 #define CONFIG_PCI_PNP
 310 #define CONFIG_EEPRO100
 311 #define CONFIG_SYS_RX_ETH_BUFFER        8               /* use 8 rx buffer on eepro100  */
 312 #endif
 313
 314 /*-----------------------------------------------------------------------
 315  * Cache Configuration
 316  */
 317 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPU              */
 318 #if defined(CONFIG_CMD_KGDB)
 319 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 320 #endif
 321
 322 /*-----------------------------------------------------------------------
 323  * HIDx - Hardware Implementation-dependent Registers                    2-11
 324  *-----------------------------------------------------------------------
 325  * HID0 also contains cache control - initially enable both caches and
 326  * invalidate contents, then the final state leaves only the instruction
 327  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 328  * but Soft reset does not.
 329  *
 330  * HID1 has only read-only information - nothing to set.
 331  */
 332 #define CONFIG_SYS_HID0_INIT    (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 333                                 HID0_IFEM|HID0_ABE)
 334 #define CONFIG_SYS_HID0_FINAL   (HID0_ICE|HID0_IFEM|HID0_ABE)
 335 #define CONFIG_SYS_HID2 0
 336
 337 /*-----------------------------------------------------------------------
 338  * RMR - Reset Mode Register                                     5-5
 339  *-----------------------------------------------------------------------
 340  * turn on Checkstop Reset Enable
 341  */
 342 #define CONFIG_SYS_RMR          RMR_CSRE
 343
 344 /*-----------------------------------------------------------------------
 345  * BCR - Bus Configuration                                       4-25
 346  *-----------------------------------------------------------------------
 347  */
 348
 349 #define BCR_APD01       0x10000000
 350 #define CONFIG_SYS_BCR          (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
 351
 352 /*-----------------------------------------------------------------------
 353  * SIUMCR - SIU Module Configuration                             4-31
 354  *-----------------------------------------------------------------------
 355  */
 356 #if 0
 357 #define CONFIG_SYS_SIUMCR       (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01)
 358 #else
 359 #define CONFIG_SYS_SIUMCR       (SIUMCR_DPPC10|SIUMCR_APPC10)
 360 #endif
 361
 362
 363 /*-----------------------------------------------------------------------
 364  * SYPCR - System Protection Control                             4-35
 365  * SYPCR can only be written once after reset!
 366  *-----------------------------------------------------------------------
 367  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 368  */
 369 #if defined(CONFIG_WATCHDOG)
 370 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 371                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 372 #else
 373 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 374                          SYPCR_SWRI|SYPCR_SWP)
 375 #endif /* CONFIG_WATCHDOG */
 376
 377 /*-----------------------------------------------------------------------
 378  * TMCNTSC - Time Counter Status and Control                     4-40
 379  *-----------------------------------------------------------------------
 380  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 381  * and enable Time Counter
 382  */
 383 #define CONFIG_SYS_TMCNTSC      (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 384
 385 /*-----------------------------------------------------------------------
 386  * PISCR - Periodic Interrupt Status and Control                 4-42
 387  *-----------------------------------------------------------------------
 388  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 389  * Periodic timer
 390  */
 391 #define CONFIG_SYS_PISCR        (PISCR_PS|PISCR_PTF|PISCR_PTE)
 392
 393 /*-----------------------------------------------------------------------
 394  * SCCR - System Clock Control                                   9-8
 395  *-----------------------------------------------------------------------
 396  */
 397 #define CONFIG_SYS_SCCR (SCCR_DFBRG00)
 398
 399 /*-----------------------------------------------------------------------
 400  * RCCR - RISC Controller Configuration                         13-7
 401  *-----------------------------------------------------------------------
 402  */
 403 #define CONFIG_SYS_RCCR 0
 404
 405 /*
 406  * Init Memory Controller:
 407  *
 408  * Bank Bus     Machine PortSz  Device
 409  * ---- ---     ------- ------  ------
 410  *  0   60x     GPCM    64 bit  FLASH
 411  *  1   60x     SDRAM   64 bit  SDRAM
 412  *
 413  */
 414
 415         /* Initialize SDRAM on local bus
 416          */
 417 #define CONFIG_SYS_INIT_LOCAL_SDRAM
 418
 419
 420 /* Minimum mask to separate preliminary
 421  * address ranges for CS[0:2]
 422  */
 423 #define CONFIG_SYS_MIN_AM_MASK 0xC0000000
 424
 425 /*
 426  * we use the same values for 32 MB and 128 MB SDRAM
 427  * refresh rate = 7.68 uS (100 MHz Bus Clock)
 428  */
 429 #define CONFIG_SYS_MPTPR        0x2000
 430 #define CONFIG_SYS_PSRT 0x16
 431
 432 #define CONFIG_SYS_MRS_OFFS     0x00000000
 433
 434
 435 #if defined(CONFIG_BOOT_ROM)
 436 /*
 437  * Bank 0 - Boot ROM (8 bit wide)
 438  */
 439 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 440                          BRx_PS_8                       |\
 441                          BRx_MS_GPCM_P                  |\
 442                          BRx_V)
 443
 444 #define CONFIG_SYS_OR0_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)    |\
 445                          ORxG_CSNT                      |\
 446                          ORxG_ACS_DIV1                  |\
 447                          ORxG_SCY_5_CLK                 |\
 448                          ORxG_EHTR                      |\
 449                          ORxG_TRLX)
 450
 451 /*
 452  * Bank 1 - Flash (64 bit wide)
 453  */
 454 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)   |\
 455                          BRx_PS_64                      |\
 456                          BRx_MS_GPCM_P                  |\
 457                          BRx_V)
 458
 459 #define CONFIG_SYS_OR1_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
 460                          ORxG_CSNT                      |\
 461                          ORxG_ACS_DIV1                  |\
 462                          ORxG_SCY_5_CLK                 |\
 463                          ORxG_EHTR                      |\
 464                          ORxG_TRLX)
 465
 466 #else   /* ! CONFIG_BOOT_ROM */
 467
 468 /*
 469  * Bank 0 - Flash (64 bit wide)
 470  */
 471 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)   |\
 472                          BRx_PS_64                      |\
 473                          BRx_MS_GPCM_P                  |\
 474                          BRx_V)
 475
 476 #define CONFIG_SYS_OR0_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
 477                          ORxG_CSNT                      |\
 478                          ORxG_ACS_DIV1                  |\
 479                          ORxG_SCY_5_CLK                 |\
 480                          ORxG_EHTR                      |\
 481                          ORxG_TRLX)
 482
 483 /*
 484  * Bank 1 - Disk-On-Chip
 485  */
 486 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK)     |\
 487                          BRx_PS_8                       |\
 488                          BRx_MS_GPCM_P                  |\
 489                          BRx_V)
 490
 491 #define CONFIG_SYS_OR1_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE)        |\
 492                          ORxG_CSNT                      |\
 493                          ORxG_ACS_DIV1                  |\
 494                          ORxG_SCY_5_CLK                 |\
 495                          ORxG_EHTR                      |\
 496                          ORxG_TRLX)
 497
 498 #endif /* CONFIG_BOOT_ROM */
 499
 500 /* Bank 2 - SDRAM
 501  */
 502
 503 #ifndef CONFIG_SYS_RAMBOOT
 504 #define CONFIG_SYS_BR2_PRELIM   ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)   |\
 505                          BRx_PS_64                      |\
 506                          BRx_MS_SDRAM_P                 |\
 507                          BRx_V)
 508
 509         /* SDRAM initialization values for 8-column chips
 510          */
 511 #define CONFIG_SYS_OR2_8COL     (CONFIG_SYS_MIN_AM_MASK         |\
 512                          ORxS_BPD_4                     |\
 513                          ORxS_ROWST_PBI0_A9             |\
 514                          ORxS_NUMR_12)
 515
 516 #define CONFIG_SYS_PSDMR_8COL   (PSDMR_SDAM_A13_IS_A5           |\
 517                          PSDMR_BSMA_A14_A16             |\
 518                          PSDMR_SDA10_PBI0_A10           |\
 519                          PSDMR_RFRC_7_CLK               |\
 520                          PSDMR_PRETOACT_2W              |\
 521                          PSDMR_ACTTORW_2W               |\
 522                          PSDMR_LDOTOPRE_1C              |\
 523                          PSDMR_WRC_1C                   |\
 524                          PSDMR_CL_2)
 525
 526         /* SDRAM initialization values for 9-column chips
 527          */
 528 #define CONFIG_SYS_OR2_9COL     (CONFIG_SYS_MIN_AM_MASK         |\
 529                          ORxS_BPD_4                     |\
 530                          ORxS_ROWST_PBI0_A7             |\
 531                          ORxS_NUMR_13)
 532
 533 #define CONFIG_SYS_PSDMR_9COL   (PSDMR_SDAM_A14_IS_A5           |\
 534                          PSDMR_BSMA_A13_A15             |\
 535                          PSDMR_SDA10_PBI0_A9            |\
 536                          PSDMR_RFRC_7_CLK               |\
 537                          PSDMR_PRETOACT_2W              |\
 538                          PSDMR_ACTTORW_2W               |\
 539                          PSDMR_LDOTOPRE_1C              |\
 540                          PSDMR_WRC_1C                   |\
 541                          PSDMR_CL_2)
 542
 543 #define CONFIG_SYS_OR2_PRELIM    CONFIG_SYS_OR2_9COL
 544 #define CONFIG_SYS_PSDMR         CONFIG_SYS_PSDMR_9COL
 545
 546 #endif /* CONFIG_SYS_RAMBOOT */
 547
 548 #endif  /* __CONFIG_H */