include/configs/PM854.h

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  * (C) Copyright 2002,2003 Motorola,Inc.
   4  * Xianghua Xiao <X.Xiao@motorola.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * pm854 board configuration file
  27  *
  28  * Please refer to doc/README.mpc85xx for more info.
  29  *
  30  * Make sure you change the MAC address and other network params first,
  31  * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
  32  */
  33
  34 #ifndef __CONFIG_H
  35 #define __CONFIG_H
  36
  37 /* High Level Configuration Options */
  38 #define CONFIG_BOOKE            1       /* BOOKE */
  39 #define CONFIG_E500             1       /* BOOKE e500 family */
  40 #define CONFIG_MPC85xx          1       /* MPC8540/MPC8560 */
  41 #define CONFIG_MPC8540          1       /* MPC8540 specific */
  42 #define CONFIG_PM854            1       /* PM854 board specific */
  43
  44 #define CONFIG_PCI
  45 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  46 #define CONFIG_ENV_OVERWRITE
  47
  48 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  49
  50 /*
  51  * sysclk for MPC85xx
  52  *
  53  * Two valid values are:
  54  *    33000000
  55  *    66000000
  56  *
  57  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  58  * is likely the desired value here, so that is now the default.
  59  * The board, however, can run at 66MHz.  In any event, this value
  60  * must match the settings of some switches.  Details can be found
  61  * in the README.mpc85xxads.
  62  */
  63
  64 #ifndef CONFIG_SYS_CLK_FREQ
  65 #define CONFIG_SYS_CLK_FREQ     66000000
  66 #endif
  67
  68
  69 /*
  70  * These can be toggled for performance analysis, otherwise use default.
  71  */
  72 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  73 #define CONFIG_BTB                      /* toggle branch predition */
  74 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming */
  75
  76 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  77
  78 #undef  CFG_DRAM_TEST                   /* memory test, takes time */
  79 #define CFG_MEMTEST_START       0x00200000      /* memtest region */
  80 #define CFG_MEMTEST_END         0x00400000
  81
  82
  83 /*
  84  * Base addresses -- Note these are effective addresses where the
  85  * actual resources get mapped (not physical addresses)
  86  */
  87 #define CFG_CCSRBAR_DEFAULT     0xff700000      /* CCSRBAR Default */
  88 #define CFG_CCSRBAR             0xe0000000      /* relocated CCSRBAR */
  89 #define CFG_CCSRBAR_PHYS        CFG_CCSRBAR     /* physical addr of CCSRBAR */
  90 #define CFG_IMMR                CFG_CCSRBAR     /* PQII uses CFG_IMMR */
  91
  92
  93 /* DDR Setup */
  94 #define CONFIG_FSL_DDR1
  95 #undef CONFIG_FSL_DDR_INTERACTIVE
  96 #undef CONFIG_SPD_EEPROM                /* Use SPD EEPROM for DDR setup */
  97 #undef CONFIG_DDR_SPD
  98 #define CONFIG_DDR_DLL                      /* possible DLL fix needed */
  99 #define CONFIG_DDR_ECC                      /* only for ECC DDR module */
 100
 101 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 102
 103 #define CFG_DDR_SDRAM_BASE      0x00000000
 104 #define CFG_SDRAM_BASE          CFG_DDR_SDRAM_BASE
 105 #define CONFIG_VERY_BIG_RAM
 106
 107 #define CONFIG_NUM_DDR_CONTROLLERS      1
 108 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 109 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 110
 111 /* I2C addresses of SPD EEPROMs */
 112 #define SPD_EEPROM_ADDRESS      0x58    /* CTLR 0 DIMM 0 */
 113
 114 /* Manually set up DDR parameters */
 115 #define CFG_SDRAM_SIZE  256             /* DDR is 256 MB */
 116 #define CFG_DDR_CS0_BNDS        0x0000000f      /* 0-256MB */
 117 #define CFG_DDR_CS0_CONFIG      0x80000102
 118 #define CFG_DDR_TIMING_1        0x47444321
 119 #define CFG_DDR_TIMING_2        0x00000800      /* P9-45,may need tuning */
 120 #define CFG_DDR_CONTROL 0xc2008000      /* unbuffered,no DYN_PWR */
 121 #define CFG_DDR_MODE    0x00000062      /* DLL,normal,seq,4/2.5 */
 122 #define CFG_DDR_INTERVAL        0x045b0100      /* autocharge,no open page */
 123
 124 /*
 125  * SDRAM on the Local Bus
 126  */
 127 #define CFG_LBC_SDRAM_BASE      0xf0000000      /* Localbus SDRAM */
 128 #define CFG_LBC_SDRAM_SIZE      0               /* LBC SDRAM is 0 MB */
 129
 130 #define CFG_FLASH_BASE          0xfe000000      /* start of 32 MB FLASH */
 131 #define CFG_BR0_PRELIM          0xfe001801      /* port size 32bit */
 132
 133 #define CFG_OR0_PRELIM          0xfe006f67      /* 32 MB Flash */
 134 #define CFG_MAX_FLASH_BANKS     1               /* number of banks */
 135 #define CFG_MAX_FLASH_SECT      128             /* sectors per device */
 136 #undef  CFG_FLASH_CHECKSUM
 137 #define CFG_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
 138 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
 139
 140 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor */
 141
 142
 143 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 144 #define CFG_RAMBOOT
 145 #else
 146 #undef  CFG_RAMBOOT
 147 #endif
 148
 149 #define CONFIG_FLASH_CFI_DRIVER
 150 #define CFG_FLASH_CFI
 151 #define CFG_FLASH_EMPTY_INFO
 152
 153 #undef CONFIG_CLOCKS_IN_MHZ
 154
 155 /*
 156  * Local Bus Definitions
 157  */
 158 #define CFG_LBC_LCRR            0x00030004    /* LB clock ratio reg */
 159 #define CFG_LBC_LBCR            0x00000000    /* LB config reg */
 160 #define CFG_LBC_LSRT            0x20000000    /* LB sdram refresh timer */
 161 #define CFG_LBC_MRTPR           0x20000000    /* LB refresh timer prescal*/
 162
 163
 164 #define CONFIG_L1_INIT_RAM
 165 #define CFG_INIT_RAM_LOCK       1
 166 #define CFG_INIT_RAM_ADDR       0xe4010000      /* Initial RAM address */
 167 #define CFG_INIT_RAM_END        0x4000          /* End of used area in RAM */
 168
 169 #define CFG_GBL_DATA_SIZE       128             /* num bytes initial data */
 170 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 171 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 172
 173 #define CFG_MONITOR_LEN         (512 * 1024)    /* Reserve 512 kB for Mon */
 174 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserved for malloc */
 175
 176 /* Serial Port */
 177 #define CONFIG_CONS_INDEX     1
 178 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 179 #define CFG_NS16550
 180 #define CFG_NS16550_SERIAL
 181 #define CFG_NS16550_REG_SIZE    1
 182 #define CFG_NS16550_CLK         get_bus_freq(0)
 183
 184 #define CFG_BAUDRATE_TABLE  \
 185         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 186
 187 #define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
 188 #define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
 189
 190 /* Use the HUSH parser */
 191 #define CFG_HUSH_PARSER
 192 #ifdef  CFG_HUSH_PARSER
 193 #define CFG_PROMPT_HUSH_PS2 "> "
 194 #endif
 195
 196 /*
 197  * I2C
 198  */
 199 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 200 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 201 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 202 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 203 #define CFG_I2C_SLAVE           0x7F
 204 #define CFG_I2C_NOPROBES        {0x69}  /* Don't probe these addrs */
 205 #define CFG_I2C_OFFSET          0x3000
 206
 207 /*
 208  * EEPROM configuration
 209  */
 210 #define CFG_I2C_EEPROM_ADDR             0x58
 211 #define CFG_I2C_EEPROM_ADDR_LEN         1
 212 #define CFG_EEPROM_PAGE_WRITE_BITS      4
 213 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10
 214
 215 /*
 216  * RTC configuration
 217  */
 218 #define CONFIG_RTC_PCF8563
 219 #define CFG_I2C_RTC_ADDR                0x51
 220
 221 /* RapidIO MMU */
 222 #define CFG_RIO_MEM_BASE        0xc0000000      /* base address */
 223 #define CFG_RIO_MEM_PHYS        CFG_RIO_MEM_BASE
 224 #define CFG_RIO_MEM_SIZE        0x20000000      /* 128M */
 225
 226 /*
 227  * General PCI
 228  * Addresses are mapped 1-1.
 229  */
 230 #define CFG_PCI1_MEM_BASE       0x80000000
 231 #define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
 232 #define CFG_PCI1_MEM_SIZE       0x20000000      /* 512M */
 233 #define CFG_PCI1_IO_BASE        0xe2000000
 234 #define CFG_PCI1_IO_PHYS        CFG_PCI1_IO_BASE
 235 #define CFG_PCI1_IO_SIZE        0x1000000       /* 16M */
 236
 237 #if defined(CONFIG_PCI)
 238
 239 #define CONFIG_NET_MULTI
 240 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 241
 242 #define CONFIG_EEPRO100
 243 #define CONFIG_E1000
 244 #undef  CONFIG_TULIP
 245
 246 #if !defined(CONFIG_PCI_PNP)
 247     #define PCI_ENET0_IOADDR    0xe0000000
 248     #define PCI_ENET0_MEMADDR   0xe0000000
 249     #define PCI_IDSEL_NUMBER    0x0c    /* slot0->3(IDSEL)=12->15 */
 250 #endif
 251
 252 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 253 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 254
 255 #endif  /* CONFIG_PCI */
 256
 257
 258 #if defined(CONFIG_TSEC_ENET)
 259
 260 #ifndef CONFIG_NET_MULTI
 261 #define CONFIG_NET_MULTI        1
 262 #endif
 263
 264 #define CONFIG_MII              1       /* MII PHY management */
 265 #define CONFIG_TSEC1    1
 266 #define CONFIG_TSEC1_NAME       "TSEC0"
 267 #define CONFIG_TSEC2    1
 268 #define CONFIG_TSEC2_NAME       "TSEC1"
 269 #define TSEC1_PHY_ADDR          0
 270 #define TSEC2_PHY_ADDR          1
 271 #define TSEC1_PHYIDX            0
 272 #define TSEC2_PHYIDX            0
 273 #define TSEC1_FLAGS             TSEC_GIGABIT
 274 #define TSEC2_FLAGS             TSEC_GIGABIT
 275
 276 #define CONFIG_MPC85XX_FEC      1
 277 #define CONFIG_MPC85XX_FEC_NAME         "FEC"
 278 #define FEC_PHY_ADDR            3
 279 #define FEC_PHYIDX              0
 280 #define FEC_FLAGS               0
 281
 282 /* Options are: TSEC[0-1] */
 283 #define CONFIG_ETHPRIME         "TSEC0"
 284
 285 #define CONFIG_HAS_ETH0
 286 #define CONFIG_HAS_ETH1         1
 287 #define CONFIG_HAS_ETH2         1
 288
 289 #endif  /* CONFIG_TSEC_ENET */
 290
 291
 292 /*
 293  * Environment
 294  */
 295 #ifndef CFG_RAMBOOT
 296   #define CONFIG_ENV_IS_IN_FLASH        1
 297   #define CONFIG_ENV_ADDR               (CFG_MONITOR_BASE - 0x80000)
 298   #define CONFIG_ENV_SECT_SIZE  0x40000 /* 256K(one sector) for env */
 299   #define CONFIG_ENV_SIZE               0x2000
 300 #else
 301   #define CFG_NO_FLASH          1       /* Flash is not usable now */
 302   #define CONFIG_ENV_IS_NOWHERE 1       /* Store ENV in memory only */
 303   #define CONFIG_ENV_ADDR               (CFG_MONITOR_BASE - 0x1000)
 304   #define CONFIG_ENV_SIZE               0x2000
 305 #endif
 306
 307 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 308 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 309
 310
 311 /*
 312  * BOOTP options
 313  */
 314 #define CONFIG_BOOTP_BOOTFILESIZE
 315 #define CONFIG_BOOTP_BOOTPATH
 316 #define CONFIG_BOOTP_GATEWAY
 317 #define CONFIG_BOOTP_HOSTNAME
 318
 319
 320 /*
 321  * Command line configuration.
 322  */
 323 #include <config_cmd_default.h>
 324
 325 #define CONFIG_CMD_PING
 326 #define CONFIG_CMD_I2C
 327 #define CONFIG_CMD_MII
 328 #define CONFIG_CMD_DATE
 329 #define CONFIG_CMD_EEPROM
 330
 331 #if defined(CONFIG_PCI)
 332     #define CONFIG_CMD_PCI
 333 #endif
 334
 335 #if defined(CFG_RAMBOOT)
 336     #undef CONFIG_CMD_ENV
 337     #undef CONFIG_CMD_LOADS
 338 #endif
 339
 340
 341 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 342
 343 /*
 344  * Miscellaneous configurable options
 345  */
 346 #define CFG_LONGHELP                    /* undef to save memory */
 347 #define CFG_LOAD_ADDR   0x2000000       /* default load address */
 348 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt */
 349
 350 #if defined(CONFIG_CMD_KGDB)
 351     #define CFG_CBSIZE  1024            /* Console I/O Buffer Size */
 352 #else
 353     #define CFG_CBSIZE  256             /* Console I/O Buffer Size */
 354 #endif
 355
 356 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 357 #define CFG_MAXARGS     16              /* max number of command args */
 358 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 359 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks */
 360 #define CONFIG_LOOPW
 361
 362 /*
 363  * For booting Linux, the board info and command line data
 364  * have to be in the first 8 MB of memory, since this is
 365  * the maximum mapped by the Linux kernel during initialization.
 366  */
 367 #define CFG_BOOTMAPSZ   (8 << 20)       /* Initial Memory map for Linux*/
 368
 369 /*
 370  * Internal Definitions
 371  *
 372  * Boot Flags
 373  */
 374 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 375 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 376
 377 #if defined(CONFIG_CMD_KGDB)
 378 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 379 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 380 #endif
 381
 382
 383 /*
 384  * Environment Configuration
 385  */
 386
 387 /* The mac addresses for all ethernet interface */
 388 #if defined(CONFIG_TSEC_ENET)
 389 #define CONFIG_ETHADDR   00:40:42:01:00:00
 390 #define CONFIG_ETH1ADDR  00:40:42:01:00:01
 391 #define CONFIG_ETH2ADDR  00:40:42:01:00:02
 392 #endif
 393
 394
 395 #define CONFIG_ROOTPATH         /opt/eldk/ppc_85xx
 396 #define CONFIG_BOOTFILE         pm854/uImage
 397
 398 #define CONFIG_HOSTNAME         pm854
 399 #define CONFIG_IPADDR    192.168.0.103
 400 #define CONFIG_SERVERIP  192.168.0.64
 401 #define CONFIG_GATEWAYIP 192.168.0.1
 402 #define CONFIG_NETMASK   255.255.255.0
 403
 404 #define CONFIG_LOADADDR  200000 /* default location for tftp and bootm */
 405
 406 #define CONFIG_BOOTDELAY 5      /* -1 disables auto-boot */
 407 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 408
 409 #define CONFIG_BAUDRATE 9600
 410
 411 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 412    "netdev=eth0\0"                                                      \
 413    "consoledev=ttyS0\0"                                                 \
 414    "ramdiskaddr=400000\0"                                               \
 415    "ramdiskfile=pm854/uRamdisk\0"
 416
 417 #define CONFIG_NFSBOOTCOMMAND                                           \
 418    "setenv bootargs root=/dev/nfs rw "                                  \
 419       "nfsroot=$serverip:$rootpath "                                    \
 420       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 421       "console=$consoledev,$baudrate $othbootargs;"                     \
 422    "tftp $loadaddr $bootfile;"                                          \
 423    "bootm $loadaddr"
 424
 425 #define CONFIG_RAMBOOTCOMMAND \
 426    "setenv bootargs root=/dev/ram rw "                                  \
 427       "console=$consoledev,$baudrate $othbootargs;"                     \
 428    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 429    "tftp $loadaddr $bootfile;"                                          \
 430    "bootm $loadaddr $ramdiskaddr"
 431
 432 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 433
 434 #endif  /* __CONFIG_H */