include/configs/PM854.h

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  * (C) Copyright 2002,2003 Motorola,Inc.
   4  * Xianghua Xiao <X.Xiao@motorola.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * pm854 board configuration file
  27  *
  28  * Please refer to doc/README.mpc85xx for more info.
  29  *
  30  * Make sure you change the MAC address and other network params first,
  31  * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
  32  */
  33
  34 #ifndef __CONFIG_H
  35 #define __CONFIG_H
  36
  37 /* High Level Configuration Options */
  38 #define CONFIG_BOOKE            1       /* BOOKE */
  39 #define CONFIG_E500             1       /* BOOKE e500 family */
  40 #define CONFIG_MPC85xx          1       /* MPC8540/MPC8560 */
  41 #define CONFIG_MPC8540          1       /* MPC8540 specific */
  42 #define CONFIG_PM854            1       /* PM854 board specific */
  43
  44 #define CONFIG_PCI
  45 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  46 #define CONFIG_ENV_OVERWRITE
  47
  48 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  49
  50 /*
  51  * sysclk for MPC85xx
  52  *
  53  * Two valid values are:
  54  *    33000000
  55  *    66000000
  56  *
  57  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  58  * is likely the desired value here, so that is now the default.
  59  * The board, however, can run at 66MHz.  In any event, this value
  60  * must match the settings of some switches.  Details can be found
  61  * in the README.mpc85xxads.
  62  */
  63
  64 #ifndef CONFIG_SYS_CLK_FREQ
  65 #define CONFIG_SYS_CLK_FREQ     66000000
  66 #endif
  67
  68
  69 /*
  70  * These can be toggled for performance analysis, otherwise use default.
  71  */
  72 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  73 #define CONFIG_BTB                      /* toggle branch predition */
  74
  75 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  76
  77 #undef  CONFIG_SYS_DRAM_TEST                    /* memory test, takes time */
  78 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  79 #define CONFIG_SYS_MEMTEST_END          0x00400000
  80
  81
  82 /*
  83  * Base addresses -- Note these are effective addresses where the
  84  * actual resources get mapped (not physical addresses)
  85  */
  86 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  87 #define CONFIG_SYS_CCSRBAR              0xe0000000      /* relocated CCSRBAR */
  88 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
  89 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  90
  91
  92 /* DDR Setup */
  93 #define CONFIG_FSL_DDR1
  94 #undef CONFIG_FSL_DDR_INTERACTIVE
  95 #undef CONFIG_SPD_EEPROM                /* Use SPD EEPROM for DDR setup */
  96 #undef CONFIG_DDR_SPD
  97 #define CONFIG_DDR_DLL                      /* possible DLL fix needed */
  98 #define CONFIG_DDR_ECC                      /* only for ECC DDR module */
  99 #define CONFIG_FSL_DMA                      /* use DMA to init DDR ECC  */
 100
 101 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 102
 103 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 104 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 105 #define CONFIG_VERY_BIG_RAM
 106
 107 #define CONFIG_NUM_DDR_CONTROLLERS      1
 108 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 109 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 110
 111 /* I2C addresses of SPD EEPROMs */
 112 #define SPD_EEPROM_ADDRESS      0x58    /* CTLR 0 DIMM 0 */
 113
 114 /* Manually set up DDR parameters */
 115 #define CONFIG_SYS_SDRAM_SIZE   256             /* DDR is 256 MB */
 116 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f      /* 0-256MB */
 117 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80000102
 118 #define CONFIG_SYS_DDR_TIMING_1 0x47444321
 119 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
 120 #define CONFIG_SYS_DDR_CONTROL  0xc2008000      /* unbuffered,no DYN_PWR */
 121 #define CONFIG_SYS_DDR_MODE     0x00000062      /* DLL,normal,seq,4/2.5 */
 122 #define CONFIG_SYS_DDR_INTERVAL 0x045b0100      /* autocharge,no open page */
 123
 124 /*
 125  * SDRAM on the Local Bus
 126  */
 127 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 128 #define CONFIG_SYS_LBC_SDRAM_SIZE       0               /* LBC SDRAM is 0 MB */
 129
 130 #define CONFIG_SYS_FLASH_BASE           0xfe000000      /* start of 32 MB FLASH */
 131 #define CONFIG_SYS_BR0_PRELIM           0xfe001801      /* port size 32bit */
 132
 133 #define CONFIG_SYS_OR0_PRELIM           0xfe006f67      /* 32 MB Flash */
 134 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 135 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 136 #undef  CONFIG_SYS_FLASH_CHECKSUM
 137 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 138 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 139
 140 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 141
 142
 143 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 144 #define CONFIG_SYS_RAMBOOT
 145 #else
 146 #undef  CONFIG_SYS_RAMBOOT
 147 #endif
 148
 149 #define CONFIG_FLASH_CFI_DRIVER
 150 #define CONFIG_SYS_FLASH_CFI
 151 #define CONFIG_SYS_FLASH_EMPTY_INFO
 152
 153 #undef CONFIG_CLOCKS_IN_MHZ
 154
 155 /*
 156  * Local Bus Definitions
 157  */
 158 #define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg */
 159 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 160 #define CONFIG_SYS_LBC_LSRT             0x20000000    /* LB sdram refresh timer */
 161 #define CONFIG_SYS_LBC_MRTPR            0x20000000    /* LB refresh timer prescal*/
 162
 163
 164 #define CONFIG_SYS_INIT_RAM_LOCK        1
 165 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 166 #define CONFIG_SYS_INIT_RAM_END 0x4000          /* End of used area in RAM */
 167
 168 #define CONFIG_SYS_GBL_DATA_SIZE        128             /* num bytes initial data */
 169 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 170 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 171
 172 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 kB for Mon */
 173 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 174
 175 /* Serial Port */
 176 #define CONFIG_CONS_INDEX     1
 177 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 178 #define CONFIG_SYS_NS16550
 179 #define CONFIG_SYS_NS16550_SERIAL
 180 #define CONFIG_SYS_NS16550_REG_SIZE     1
 181 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 182
 183 #define CONFIG_SYS_BAUDRATE_TABLE  \
 184         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 185
 186 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 187 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 188
 189 /* Use the HUSH parser */
 190 #define CONFIG_SYS_HUSH_PARSER
 191 #ifdef  CONFIG_SYS_HUSH_PARSER
 192 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 193 #endif
 194
 195 /*
 196  * I2C
 197  */
 198 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 199 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 200 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 201 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 202 #define CONFIG_SYS_I2C_SLAVE            0x7F
 203 #define CONFIG_SYS_I2C_NOPROBES {0x69}  /* Don't probe these addrs */
 204 #define CONFIG_SYS_I2C_OFFSET           0x3000
 205
 206 /*
 207  * EEPROM configuration
 208  */
 209 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x58
 210 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 211 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 212 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 213
 214 /*
 215  * RTC configuration
 216  */
 217 #define CONFIG_RTC_PCF8563
 218 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
 219
 220 /* RapidIO MMU */
 221 #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000      /* base address */
 222 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
 223 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 128M */
 224
 225 /*
 226  * General PCI
 227  * Addresses are mapped 1-1.
 228  */
 229 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 230 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 231 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 232 #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
 233 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
 234 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000       /* 16M */
 235
 236 #if defined(CONFIG_PCI)
 237
 238 #define CONFIG_NET_MULTI
 239 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 240
 241 #define CONFIG_EEPRO100
 242 #define CONFIG_E1000
 243 #undef  CONFIG_TULIP
 244
 245 #if !defined(CONFIG_PCI_PNP)
 246     #define PCI_ENET0_IOADDR    0xe0000000
 247     #define PCI_ENET0_MEMADDR   0xe0000000
 248     #define PCI_IDSEL_NUMBER    0x0c    /* slot0->3(IDSEL)=12->15 */
 249 #endif
 250
 251 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 252 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057   /* Motorola */
 253
 254 #endif  /* CONFIG_PCI */
 255
 256
 257 #if defined(CONFIG_TSEC_ENET)
 258
 259 #ifndef CONFIG_NET_MULTI
 260 #define CONFIG_NET_MULTI        1
 261 #endif
 262
 263 #define CONFIG_MII              1       /* MII PHY management */
 264 #define CONFIG_TSEC1    1
 265 #define CONFIG_TSEC1_NAME       "TSEC0"
 266 #define CONFIG_TSEC2    1
 267 #define CONFIG_TSEC2_NAME       "TSEC1"
 268 #define TSEC1_PHY_ADDR          0
 269 #define TSEC2_PHY_ADDR          1
 270 #define TSEC1_PHYIDX            0
 271 #define TSEC2_PHYIDX            0
 272 #define TSEC1_FLAGS             TSEC_GIGABIT
 273 #define TSEC2_FLAGS             TSEC_GIGABIT
 274
 275 #define CONFIG_MPC85XX_FEC      1
 276 #define CONFIG_MPC85XX_FEC_NAME         "FEC"
 277 #define FEC_PHY_ADDR            3
 278 #define FEC_PHYIDX              0
 279 #define FEC_FLAGS               0
 280
 281 /* Options are: TSEC[0-1] */
 282 #define CONFIG_ETHPRIME         "TSEC0"
 283
 284 #define CONFIG_HAS_ETH0
 285 #define CONFIG_HAS_ETH1         1
 286 #define CONFIG_HAS_ETH2         1
 287
 288 #endif  /* CONFIG_TSEC_ENET */
 289
 290
 291 /*
 292  * Environment
 293  */
 294 #ifndef CONFIG_SYS_RAMBOOT
 295   #define CONFIG_ENV_IS_IN_FLASH        1
 296   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE - 0x80000)
 297   #define CONFIG_ENV_SECT_SIZE  0x40000 /* 256K(one sector) for env */
 298   #define CONFIG_ENV_SIZE               0x2000
 299 #else
 300   #define CONFIG_SYS_NO_FLASH           1       /* Flash is not usable now */
 301   #define CONFIG_ENV_IS_NOWHERE 1       /* Store ENV in memory only */
 302   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE - 0x1000)
 303   #define CONFIG_ENV_SIZE               0x2000
 304 #endif
 305
 306 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 307 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 308
 309
 310 /*
 311  * BOOTP options
 312  */
 313 #define CONFIG_BOOTP_BOOTFILESIZE
 314 #define CONFIG_BOOTP_BOOTPATH
 315 #define CONFIG_BOOTP_GATEWAY
 316 #define CONFIG_BOOTP_HOSTNAME
 317
 318
 319 /*
 320  * Command line configuration.
 321  */
 322 #include <config_cmd_default.h>
 323
 324 #define CONFIG_CMD_PING
 325 #define CONFIG_CMD_I2C
 326 #define CONFIG_CMD_MII
 327 #define CONFIG_CMD_DATE
 328 #define CONFIG_CMD_EEPROM
 329
 330 #if defined(CONFIG_PCI)
 331     #define CONFIG_CMD_PCI
 332 #endif
 333
 334 #if defined(CONFIG_SYS_RAMBOOT)
 335     #undef CONFIG_CMD_SAVEENV
 336     #undef CONFIG_CMD_LOADS
 337 #endif
 338
 339
 340 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 341
 342 /*
 343  * Miscellaneous configurable options
 344  */
 345 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 346 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 347 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 348
 349 #if defined(CONFIG_CMD_KGDB)
 350     #define CONFIG_SYS_CBSIZE   1024            /* Console I/O Buffer Size */
 351 #else
 352     #define CONFIG_SYS_CBSIZE   256             /* Console I/O Buffer Size */
 353 #endif
 354
 355 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 356 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 357 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 358 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 359 #define CONFIG_LOOPW
 360
 361 /*
 362  * For booting Linux, the board info and command line data
 363  * have to be in the first 8 MB of memory, since this is
 364  * the maximum mapped by the Linux kernel during initialization.
 365  */
 366 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 367
 368 /*
 369  * Internal Definitions
 370  *
 371  * Boot Flags
 372  */
 373 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 374 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 375
 376 #if defined(CONFIG_CMD_KGDB)
 377 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 378 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 379 #endif
 380
 381
 382 /*
 383  * Environment Configuration
 384  */
 385
 386 /* The mac addresses for all ethernet interface */
 387 #if defined(CONFIG_TSEC_ENET)
 388 #define CONFIG_ETHADDR   00:40:42:01:00:00
 389 #define CONFIG_ETH1ADDR  00:40:42:01:00:01
 390 #define CONFIG_ETH2ADDR  00:40:42:01:00:02
 391 #endif
 392
 393
 394 #define CONFIG_ROOTPATH         /opt/eldk/ppc_85xx
 395 #define CONFIG_BOOTFILE         pm854/uImage
 396
 397 #define CONFIG_HOSTNAME         pm854
 398 #define CONFIG_IPADDR    192.168.0.103
 399 #define CONFIG_SERVERIP  192.168.0.64
 400 #define CONFIG_GATEWAYIP 192.168.0.1
 401 #define CONFIG_NETMASK   255.255.255.0
 402
 403 #define CONFIG_LOADADDR  200000 /* default location for tftp and bootm */
 404
 405 #define CONFIG_BOOTDELAY 5      /* -1 disables auto-boot */
 406 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 407
 408 #define CONFIG_BAUDRATE 9600
 409
 410 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 411    "netdev=eth0\0"                                                      \
 412    "consoledev=ttyS0\0"                                                 \
 413    "ramdiskaddr=400000\0"                                               \
 414    "ramdiskfile=pm854/uRamdisk\0"
 415
 416 #define CONFIG_NFSBOOTCOMMAND                                           \
 417    "setenv bootargs root=/dev/nfs rw "                                  \
 418       "nfsroot=$serverip:$rootpath "                                    \
 419       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 420       "console=$consoledev,$baudrate $othbootargs;"                     \
 421    "tftp $loadaddr $bootfile;"                                          \
 422    "bootm $loadaddr"
 423
 424 #define CONFIG_RAMBOOTCOMMAND \
 425    "setenv bootargs root=/dev/ram rw "                                  \
 426       "console=$consoledev,$baudrate $othbootargs;"                     \
 427    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 428    "tftp $loadaddr $bootfile;"                                          \
 429    "bootm $loadaddr $ramdiskaddr"
 430
 431 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 432
 433 #endif  /* __CONFIG_H */