include/configs/PM854.h

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  * (C) Copyright 2002,2003 Motorola,Inc.
   4  * Xianghua Xiao <X.Xiao@motorola.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * pm854 board configuration file
  27  *
  28  * Please refer to doc/README.mpc85xx for more info.
  29  *
  30  * Make sure you change the MAC address and other network params first,
  31  * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
  32  */
  33
  34 #ifndef __CONFIG_H
  35 #define __CONFIG_H
  36
  37 /* High Level Configuration Options */
  38 #define CONFIG_BOOKE            1       /* BOOKE */
  39 #define CONFIG_E500             1       /* BOOKE e500 family */
  40 #define CONFIG_MPC85xx          1       /* MPC8540/MPC8560 */
  41 #define CONFIG_MPC8540          1       /* MPC8540 specific */
  42 #define CONFIG_PM854            1       /* PM854 board specific */
  43
  44 #define CONFIG_PCI
  45 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  46 #define CONFIG_ENV_OVERWRITE
  47 #undef  CONFIG_SPD_EEPROM               /* do not use SPD EEPROM for DDR setup*/
  48 #define CONFIG_DDR_DLL                  /* possible DLL fix needed */
  49 #define CONFIG_DDR_2T_TIMING            /* Sets the 2T timing bit */
  50
  51 #define CONFIG_DDR_ECC                  /* only for ECC DDR module */
  52 #define CONFIG_MEM_INIT_VALUE           0xDEADBEEF
  53
  54
  55 /*
  56  * sysclk for MPC85xx
  57  *
  58  * Two valid values are:
  59  *    33000000
  60  *    66000000
  61  *
  62  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  63  * is likely the desired value here, so that is now the default.
  64  * The board, however, can run at 66MHz.  In any event, this value
  65  * must match the settings of some switches.  Details can be found
  66  * in the README.mpc85xxads.
  67  */
  68
  69 #ifndef CONFIG_SYS_CLK_FREQ
  70 #define CONFIG_SYS_CLK_FREQ     66000000
  71 #endif
  72
  73
  74 /*
  75  * These can be toggled for performance analysis, otherwise use default.
  76  */
  77 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  78 #define CONFIG_BTB                      /* toggle branch predition */
  79 #define CONFIG_ADDR_STREAMING           /* toggle addr streaming */
  80
  81 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  82
  83 #undef  CFG_DRAM_TEST                   /* memory test, takes time */
  84 #define CFG_MEMTEST_START       0x00200000      /* memtest region */
  85 #define CFG_MEMTEST_END         0x00400000
  86
  87
  88 /*
  89  * Base addresses -- Note these are effective addresses where the
  90  * actual resources get mapped (not physical addresses)
  91  */
  92 #define CFG_CCSRBAR_DEFAULT     0xff700000      /* CCSRBAR Default */
  93 #define CFG_CCSRBAR             0xe0000000      /* relocated CCSRBAR */
  94 #define CFG_IMMR                CFG_CCSRBAR     /* PQII uses CFG_IMMR */
  95
  96
  97 /*
  98  * DDR Setup
  99  */
 100 #define CFG_DDR_SDRAM_BASE      0x00000000      /* DDR is system memory*/
 101 #define CFG_SDRAM_BASE          CFG_DDR_SDRAM_BASE
 102
 103 #if defined(CONFIG_SPD_EEPROM)
 104     /*
 105      * Determine DDR configuration from I2C interface.
 106      */
 107     #define SPD_EEPROM_ADDRESS  0x58            /* DDR DIMM */
 108
 109 #else
 110     /*
 111      * Manually set up DDR parameters
 112      */
 113     #define CFG_SDRAM_SIZE      256             /* DDR is 256 MB */
 114     #define CFG_DDR_CS0_BNDS    0x0000000f      /* 0-256MB */
 115     #define CFG_DDR_CS0_CONFIG  0x80000102
 116     #define CFG_DDR_TIMING_1    0x47444321
 117     #define CFG_DDR_TIMING_2    0x00000800      /* P9-45,may need tuning */
 118     #define CFG_DDR_CONTROL     0xc2008000      /* unbuffered,no DYN_PWR */
 119     #define CFG_DDR_MODE        0x00000062      /* DLL,normal,seq,4/2.5 */
 120     #define CFG_DDR_INTERVAL    0x045b0100      /* autocharge,no open page */
 121 #endif
 122
 123
 124 /*
 125  * SDRAM on the Local Bus
 126  */
 127 #define CFG_LBC_SDRAM_BASE      0xf0000000      /* Localbus SDRAM */
 128 #define CFG_LBC_SDRAM_SIZE      0               /* LBC SDRAM is 0 MB */
 129
 130 #define CFG_FLASH_BASE          0xfe000000      /* start of 32 MB FLASH */
 131 #define CFG_BR0_PRELIM          0xfe001801      /* port size 32bit */
 132
 133 #define CFG_OR0_PRELIM          0xfe006f67      /* 32 MB Flash */
 134 #define CFG_MAX_FLASH_BANKS     1               /* number of banks */
 135 #define CFG_MAX_FLASH_SECT      128             /* sectors per device */
 136 #undef  CFG_FLASH_CHECKSUM
 137 #define CFG_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
 138 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
 139
 140 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor */
 141
 142
 143 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 144 #define CFG_RAMBOOT
 145 #else
 146 #undef  CFG_RAMBOOT
 147 #endif
 148
 149 #define CFG_FLASH_CFI_DRIVER
 150 #define CFG_FLASH_CFI
 151 #define CFG_FLASH_EMPTY_INFO
 152
 153 #undef CONFIG_CLOCKS_IN_MHZ
 154
 155 /*
 156  * Local Bus Definitions
 157  */
 158 #define CFG_LBC_LCRR            0x00030004    /* LB clock ratio reg */
 159 #define CFG_LBC_LBCR            0x00000000    /* LB config reg */
 160 #define CFG_LBC_LSRT            0x20000000    /* LB sdram refresh timer */
 161 #define CFG_LBC_MRTPR           0x20000000    /* LB refresh timer prescal*/
 162
 163
 164 #define CONFIG_L1_INIT_RAM
 165 #define CFG_INIT_RAM_LOCK       1
 166 #define CFG_INIT_RAM_ADDR       0xe4010000      /* Initial RAM address */
 167 #define CFG_INIT_RAM_END        0x4000          /* End of used area in RAM */
 168
 169 #define CFG_GBL_DATA_SIZE       128             /* num bytes initial data */
 170 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 171 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 172
 173 #define CFG_MONITOR_LEN         (512 * 1024)    /* Reserve 512 kB for Mon */
 174 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserved for malloc */
 175
 176 /* Serial Port */
 177 #define CONFIG_CONS_INDEX     1
 178 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 179 #define CFG_NS16550
 180 #define CFG_NS16550_SERIAL
 181 #define CFG_NS16550_REG_SIZE    1
 182 #define CFG_NS16550_CLK         get_bus_freq(0)
 183
 184 #define CFG_BAUDRATE_TABLE  \
 185         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 186
 187 #define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
 188 #define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
 189
 190 /* Use the HUSH parser */
 191 #define CFG_HUSH_PARSER
 192 #ifdef  CFG_HUSH_PARSER
 193 #define CFG_PROMPT_HUSH_PS2 "> "
 194 #endif
 195
 196 /* I2C */
 197 #define  CONFIG_HARD_I2C                /* I2C with hardware support*/
 198 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 199 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 200 #define CFG_I2C_SLAVE           0x7F
 201 #define CFG_I2C_NOPROBES        {0x69}  /* Don't probe these addrs */
 202
 203 /*
 204  * EEPROM configuration
 205  */
 206 #define CFG_I2C_EEPROM_ADDR             0x58
 207 #define CFG_I2C_EEPROM_ADDR_LEN         1
 208 #define CFG_EEPROM_PAGE_WRITE_BITS      4
 209 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10
 210
 211 /*
 212  * RTC configuration
 213  */
 214 #define CONFIG_RTC_PCF8563
 215 #define CFG_I2C_RTC_ADDR                0x51
 216
 217 /* RapidIO MMU */
 218 #define CFG_RIO_MEM_BASE        0xc0000000      /* base address */
 219 #define CFG_RIO_MEM_PHYS        CFG_RIO_MEM_BASE
 220 #define CFG_RIO_MEM_SIZE        0x20000000      /* 128M */
 221
 222 /*
 223  * General PCI
 224  * Addresses are mapped 1-1.
 225  */
 226 #define CFG_PCI1_MEM_BASE       0x80000000
 227 #define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
 228 #define CFG_PCI1_MEM_SIZE       0x20000000      /* 512M */
 229 #define CFG_PCI1_IO_BASE        0xe2000000
 230 #define CFG_PCI1_IO_PHYS        CFG_PCI1_IO_BASE
 231 #define CFG_PCI1_IO_SIZE        0x1000000       /* 16M */
 232
 233 #if defined(CONFIG_PCI)
 234
 235 #define CONFIG_NET_MULTI
 236 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 237
 238 /* #define CONFIG_EEPRO100      XXX - FIXME: conflicts when CONFIG_MII is enabled */
 239 #define CONFIG_E1000
 240 #undef  CONFIG_TULIP
 241
 242 #if !defined(CONFIG_PCI_PNP)
 243     #define PCI_ENET0_IOADDR    0xe0000000
 244     #define PCI_ENET0_MEMADDR   0xe0000000
 245     #define PCI_IDSEL_NUMBER    0x0c    /* slot0->3(IDSEL)=12->15 */
 246 #endif
 247
 248 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 249 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 250
 251 #endif  /* CONFIG_PCI */
 252
 253
 254 #if defined(CONFIG_TSEC_ENET)
 255
 256 #ifndef CONFIG_NET_MULTI
 257 #define CONFIG_NET_MULTI        1
 258 #endif
 259
 260 #define CONFIG_MII              1       /* MII PHY management */
 261 #define CONFIG_MPC85XX_TSEC1    1
 262 #define CONFIG_MPC85XX_TSEC1_NAME       "TSEC0"
 263 #define CONFIG_MPC85XX_TSEC2    1
 264 #define CONFIG_MPC85XX_TSEC2_NAME       "TSEC1"
 265 #define TSEC1_PHY_ADDR          0
 266 #define TSEC2_PHY_ADDR          1
 267 #define TSEC1_PHYIDX            0
 268 #define TSEC2_PHYIDX            0
 269
 270 #define CONFIG_MPC85XX_FEC      1
 271 #define CONFIG_MPC85XX_FEC_NAME         "FEC"
 272 #define FEC_PHY_ADDR            3
 273 #define FEC_PHYIDX              0
 274
 275 /* Options are: TSEC[0-1] */
 276 #define CONFIG_ETHPRIME         "TSEC0"
 277
 278 #define CONFIG_HAS_ETH1         1
 279 #define CONFIG_HAS_ETH2         1
 280
 281 #endif  /* CONFIG_TSEC_ENET */
 282
 283
 284 /*
 285  * Environment
 286  */
 287 #ifndef CFG_RAMBOOT
 288   #define CFG_ENV_IS_IN_FLASH   1
 289   #define CFG_ENV_ADDR          (CFG_MONITOR_BASE - 0x80000)
 290   #define CFG_ENV_SECT_SIZE     0x40000 /* 256K(one sector) for env */
 291   #define CFG_ENV_SIZE          0x2000
 292 #else
 293   #define CFG_NO_FLASH          1       /* Flash is not usable now */
 294   #define CFG_ENV_IS_NOWHERE    1       /* Store ENV in memory only */
 295   #define CFG_ENV_ADDR          (CFG_MONITOR_BASE - 0x1000)
 296   #define CFG_ENV_SIZE          0x2000
 297 #endif
 298
 299 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 300 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
 301
 302 #if defined(CFG_RAMBOOT)
 303   #if defined(CONFIG_PCI)
 304     #define  CONFIG_COMMANDS    ((CONFIG_CMD_DFL        \
 305                                  | CFG_CMD_PING         \
 306                                  | CFG_CMD_PCI          \
 307                                  | CFG_CMD_I2C)         \
 308                                 &                       \
 309                                  ~(CFG_CMD_ENV          \
 310                                   | CFG_CMD_LOADS))
 311   #else
 312     #define  CONFIG_COMMANDS    ((CONFIG_CMD_DFL        \
 313                                  | CFG_CMD_PING         \
 314                                  | CFG_CMD_I2C)         \
 315                                 &                       \
 316                                  ~(CFG_CMD_ENV          \
 317                                   | CFG_CMD_LOADS))
 318   #endif
 319 #else
 320   #if defined(CONFIG_PCI)
 321     #define  CONFIG_COMMANDS    (CONFIG_CMD_DFL         \
 322                                 | CFG_CMD_EEPROM        \
 323                                 | CFG_CMD_DATE          \
 324                                 | CFG_CMD_MII           \
 325                                 | CFG_CMD_PCI           \
 326                                 | CFG_CMD_PING          \
 327                                 | CFG_CMD_I2C)
 328   #else
 329     #define  CONFIG_COMMANDS    (CONFIG_CMD_DFL         \
 330                                 | CFG_CMD_EEPROM        \
 331                                 | CFG_CMD_DATE          \
 332                                 | CFG_CMD_MII           \
 333                                 | CFG_CMD_PING          \
 334                                 | CFG_CMD_I2C)
 335   #endif
 336 #endif
 337
 338 #include <cmd_confdefs.h>
 339
 340 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 341
 342 /*
 343  * Miscellaneous configurable options
 344  */
 345 #define CFG_LONGHELP                    /* undef to save memory */
 346 #define CFG_LOAD_ADDR   0x2000000       /* default load address */
 347 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt */
 348
 349 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 350     #define CFG_CBSIZE  1024            /* Console I/O Buffer Size */
 351 #else
 352     #define CFG_CBSIZE  256             /* Console I/O Buffer Size */
 353 #endif
 354
 355 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 356 #define CFG_MAXARGS     16              /* max number of command args */
 357 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 358 #define CFG_HZ          1000            /* decrementer freq: 1ms ticks */
 359 #define CONFIG_LOOPW
 360
 361 /*
 362  * For booting Linux, the board info and command line data
 363  * have to be in the first 8 MB of memory, since this is
 364  * the maximum mapped by the Linux kernel during initialization.
 365  */
 366 #define CFG_BOOTMAPSZ   (8 << 20)       /* Initial Memory map for Linux*/
 367
 368 /* Cache Configuration */
 369 #define CFG_DCACHE_SIZE         32768
 370 #define CFG_CACHELINE_SIZE      32
 371 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 372 #define CFG_CACHELINE_SHIFT     5       /*log base 2 of the above value*/
 373 #endif
 374
 375 /*
 376  * Internal Definitions
 377  *
 378  * Boot Flags
 379  */
 380 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 381 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 382
 383 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 384 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 385 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 386 #endif
 387
 388
 389 /*
 390  * Environment Configuration
 391  */
 392
 393 /* The mac addresses for all ethernet interface */
 394 #if defined(CONFIG_TSEC_ENET)
 395 #define CONFIG_ETHADDR   00:40:42:01:00:00
 396 #define CONFIG_ETH1ADDR  00:40:42:01:00:01
 397 #define CONFIG_ETH2ADDR  00:40:42:01:00:02
 398 #endif
 399
 400
 401 #define CONFIG_ROOTPATH         /opt/eldk/ppc_85xx
 402 #define CONFIG_BOOTFILE         pm854/uImage
 403
 404 #define CONFIG_HOSTNAME         pm854
 405 #define CONFIG_IPADDR    192.168.0.103
 406 #define CONFIG_SERVERIP  192.168.0.64
 407 #define CONFIG_GATEWAYIP 192.168.0.1
 408 #define CONFIG_NETMASK   255.255.255.0
 409
 410 #define CONFIG_LOADADDR  200000 /* default location for tftp and bootm */
 411
 412 #define CONFIG_BOOTDELAY 5      /* -1 disables auto-boot */
 413 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 414
 415 #define CONFIG_BAUDRATE 9600
 416
 417 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 418    "netdev=eth0\0"                                                      \
 419    "consoledev=ttyS0\0"                                                 \
 420    "ramdiskaddr=400000\0"                                               \
 421    "ramdiskfile=pm854/uRamdisk\0"
 422
 423 #define CONFIG_NFSBOOTCOMMAND                                           \
 424    "setenv bootargs root=/dev/nfs rw "                                  \
 425       "nfsroot=$serverip:$rootpath "                                    \
 426       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 427       "console=$consoledev,$baudrate $othbootargs;"                     \
 428    "tftp $loadaddr $bootfile;"                                          \
 429    "bootm $loadaddr"
 430
 431 #define CONFIG_RAMBOOTCOMMAND \
 432    "setenv bootargs root=/dev/ram rw "                                  \
 433       "console=$consoledev,$baudrate $othbootargs;"                     \
 434    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 435    "tftp $loadaddr $bootfile;"                                          \
 436    "bootm $loadaddr $ramdiskaddr"
 437
 438 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 439
 440 #endif  /* __CONFIG_H */