include/configs/PM856.h

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  * (C) Copyright 2002,2003 Motorola,Inc.
   4  * Xianghua Xiao <X.Xiao@motorola.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * MicroSys PM856 board configuration file
  27  *
  28  * Please refer to doc/README.mpc85xx for more info.
  29  *
  30  * Make sure you change the MAC address and other network params first,
  31  * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
  32  */
  33
  34 #ifndef __CONFIG_H
  35 #define __CONFIG_H
  36
  37 /* High Level Configuration Options */
  38 #define CONFIG_BOOKE            1       /* BOOKE */
  39 #define CONFIG_E500             1       /* BOOKE e500 family */
  40 #define CONFIG_MPC85xx          1       /* MPC8540/MPC8560 */
  41 #define CONFIG_MPC8560          1       /* MPC8560 specific */
  42 #define CONFIG_CPM2             1       /* Has a CPM2 */
  43 #define CONFIG_PM856            1       /* PM856 board specific */
  44
  45 #define CONFIG_PCI
  46 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  47 #define CONFIG_ENV_OVERWRITE
  48
  49 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  50
  51 /*
  52  * sysclk for MPC85xx
  53  *
  54  * Two valid values are:
  55  *    33000000
  56  *    66000000
  57  *
  58  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  59  * is likely the desired value here, so that is now the default.
  60  * The board, however, can run at 66MHz.  In any event, this value
  61  * must match the settings of some switches.  Details can be found
  62  * in the README.mpc85xxads.
  63  */
  64
  65 #ifndef CONFIG_SYS_CLK_FREQ
  66 #define CONFIG_SYS_CLK_FREQ     66000000
  67 #endif
  68
  69
  70 /*
  71  * These can be toggled for performance analysis, otherwise use default.
  72  */
  73 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  74 #define CONFIG_BTB                      /* toggle branch predition */
  75
  76 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  77
  78 #define CONFIG_SYS_INIT_DBCR DBCR_IDM           /* Enable Debug Exceptions */
  79
  80 #undef  CONFIG_SYS_DRAM_TEST                    /* memory test, takes time */
  81 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  82 #define CONFIG_SYS_MEMTEST_END          0x00400000
  83
  84
  85 /*
  86  * Base addresses -- Note these are effective addresses where the
  87  * actual resources get mapped (not physical addresses)
  88  */
  89 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
  90 #define CONFIG_SYS_CCSRBAR              0xe0000000      /* relocated CCSRBAR */
  91 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
  92 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  93
  94 /* DDR Setup */
  95 #define CONFIG_FSL_DDR1
  96 #undef CONFIG_FSL_DDR_INTERACTIVE
  97 #undef CONFIG_SPD_EEPROM                /* Use SPD EEPROM for DDR setup */
  98 #undef CONFIG_DDR_SPD
  99 #define CONFIG_DDR_DLL                      /* possible DLL fix needed */
 100 #define CONFIG_DDR_ECC                      /* only for ECC DDR module */
 101 #define CONFIG_FSL_DMA                      /* use DMA to init DDR ECC  */
 102
 103 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 104
 105 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 106 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 107 #define CONFIG_VERY_BIG_RAM
 108
 109 #define CONFIG_NUM_DDR_CONTROLLERS      1
 110 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 111 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 112
 113 /* I2C addresses of SPD EEPROMs */
 114 #define SPD_EEPROM_ADDRESS      0x58    /* CTLR 0 DIMM 0 */
 115
 116 /* Manually set up DDR parameters */
 117 #define CONFIG_SYS_SDRAM_SIZE   256             /* DDR is 256 MB */
 118 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f      /* 0-256MB */
 119 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80000102
 120 #define CONFIG_SYS_DDR_TIMING_1 0x47444321
 121 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
 122 #define CONFIG_SYS_DDR_CONTROL  0xc2008000      /* unbuffered,no DYN_PWR */
 123 #define CONFIG_SYS_DDR_MODE     0x00000062      /* DLL,normal,seq,4/2.5 */
 124 #define CONFIG_SYS_DDR_INTERVAL 0x045b0100      /* autocharge,no open page */
 125
 126 /*
 127  * SDRAM on the Local Bus
 128  */
 129 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 130 #define CONFIG_SYS_LBC_SDRAM_SIZE       0               /* LBC SDRAM is 0 MB */
 131
 132 #define CONFIG_SYS_FLASH_BASE           0xfe000000      /* start of FLASH 32M */
 133 #define CONFIG_SYS_BR0_PRELIM           0xfe001801      /* port size 32bit */
 134
 135 #define CONFIG_SYS_OR0_PRELIM           0xfe006f67      /* 32MB Flash */
 136 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 137 #define CONFIG_SYS_MAX_FLASH_SECT       128             /* sectors per device */
 138 #undef  CONFIG_SYS_FLASH_CHECKSUM
 139 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 140 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 141
 142 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 143
 144 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 145 #define CONFIG_SYS_RAMBOOT
 146 #else
 147 #undef  CONFIG_SYS_RAMBOOT
 148 #endif
 149
 150 #define CONFIG_FLASH_CFI_DRIVER
 151 #define CONFIG_SYS_FLASH_CFI
 152 #define CONFIG_SYS_FLASH_EMPTY_INFO
 153
 154 #undef CONFIG_CLOCKS_IN_MHZ
 155
 156
 157 /*
 158  * Local Bus Definitions
 159  */
 160
 161 #define CONFIG_SYS_LBC_LCRR             0x00030004    /* LB clock ratio reg */
 162 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 163 #define CONFIG_SYS_LBC_LSRT             0x20000000    /* LB sdram refresh timer */
 164 #define CONFIG_SYS_LBC_MRTPR            0x20000000    /* LB refresh timer prescal*/
 165
 166
 167 #define CONFIG_SYS_INIT_RAM_LOCK        1
 168 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 169 #define CONFIG_SYS_INIT_RAM_END 0x4000          /* End of used area in RAM */
 170
 171 #define CONFIG_SYS_GBL_DATA_SIZE        128             /* num bytes initial data */
 172 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 173 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 174
 175 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 kB for Mon */
 176 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 177
 178 /* Serial Port */
 179 #define CONFIG_CONS_ON_SCC      /* define if console on SCC */
 180 #undef  CONFIG_CONS_NONE        /* define if console on something else */
 181 #define CONFIG_CONS_INDEX       1  /* which serial channel for console */
 182
 183 #define CONFIG_SYS_BAUDRATE_TABLE  \
 184         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 185
 186 /* Use the HUSH parser */
 187 #define CONFIG_SYS_HUSH_PARSER
 188 #ifdef  CONFIG_SYS_HUSH_PARSER
 189 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 190 #endif
 191
 192 /*
 193  * I2C
 194  */
 195 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 196 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 197 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 198 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 199 #define CONFIG_SYS_I2C_SLAVE            0x7F
 200 #define CONFIG_SYS_I2C_NOPROBES        {0x69}   /* Don't probe these addrs */
 201 #define CONFIG_SYS_I2C_OFFSET           0x3000
 202
 203 /*
 204  * EEPROM configuration
 205  */
 206 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x58
 207 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 208 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 209 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 210
 211 /*
 212  * RTC configuration
 213  */
 214 #define CONFIG_RTC_PCF8563
 215 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
 216
 217 /* RapidIO MMU */
 218 #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000      /* base address */
 219 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
 220 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 128M */
 221
 222 /*
 223  * General PCI
 224  * Addresses are mapped 1-1.
 225  */
 226 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 227 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 228 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 229 #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
 230 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
 231 #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000       /* 16M */
 232
 233 #if defined(CONFIG_PCI)
 234
 235 #define CONFIG_NET_MULTI
 236 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 237
 238 #undef CONFIG_EEPRO100
 239 #undef CONFIG_TULIP
 240
 241 #if !defined(CONFIG_PCI_PNP)
 242     #define PCI_ENET0_IOADDR    0xe0000000
 243     #define PCI_ENET0_MEMADDR   0xe0000000
 244     #define PCI_IDSEL_NUMBER    0x0c    /* slot0->3(IDSEL)=12->15 */
 245 #endif
 246
 247 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 248 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 249
 250 #endif  /* CONFIG_PCI */
 251
 252
 253 #if defined(CONFIG_TSEC_ENET)
 254
 255 #ifndef CONFIG_NET_MULTI
 256 #define CONFIG_NET_MULTI        1
 257 #endif
 258
 259 #define CONFIG_MII              1       /* MII PHY management */
 260 #define CONFIG_TSEC1    1
 261 #define CONFIG_TSEC1_NAME       "TSEC0"
 262 #define CONFIG_TSEC2    1
 263 #define CONFIG_TSEC2_NAME       "TSEC1"
 264 #define TSEC1_PHY_ADDR          0
 265 #define TSEC2_PHY_ADDR          1
 266 #define TSEC1_PHYIDX            0
 267 #define TSEC2_PHYIDX            0
 268 #define TSEC1_FLAGS             TSEC_GIGABIT
 269 #define TSEC2_FLAGS             TSEC_GIGABIT
 270
 271 #endif  /* CONFIG_TSEC_ENET */
 272
 273 #define CONFIG_ETHPRIME         "TSEC0"
 274
 275 #define CONFIG_ETHER_ON_FCC     /* define if ether on FCC   */
 276 #undef  CONFIG_ETHER_NONE       /* define if ether on something else */
 277
 278
 279 /*
 280    * - Rx-CLK is CLK15
 281    * - Tx-CLK is CLK14
 282    * - Select bus for bd/buffers
 283    * - Full duplex
 284  */
 285 #define CONFIG_ETHER_ON_FCC3
 286 #define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
 287 #define CONFIG_SYS_CMXFCR_VALUE3        (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
 288 #define CONFIG_SYS_CPMFCR_RAMTYPE       0
 289 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE)
 290
 291 /*
 292  * Environment
 293  */
 294 #ifndef CONFIG_SYS_RAMBOOT
 295   #define CONFIG_ENV_IS_IN_FLASH        1
 296   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE - 0x80000)
 297   #define CONFIG_ENV_SECT_SIZE  0x40000 /* 256K(one sector) for env */
 298   #define CONFIG_ENV_SIZE               0x2000
 299 #else
 300   #define CONFIG_SYS_NO_FLASH           1       /* Flash is not usable now */
 301   #define CONFIG_ENV_IS_NOWHERE 1       /* Store ENV in memory only */
 302   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE - 0x1000)
 303   #define CONFIG_ENV_SIZE               0x2000
 304 #endif
 305
 306 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 307 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 308
 309
 310 /*
 311  * BOOTP options
 312  */
 313 #define CONFIG_BOOTP_BOOTFILESIZE
 314 #define CONFIG_BOOTP_BOOTPATH
 315 #define CONFIG_BOOTP_GATEWAY
 316 #define CONFIG_BOOTP_HOSTNAME
 317
 318
 319 /*
 320  * Command line configuration.
 321  */
 322 #include <config_cmd_default.h>
 323
 324 #define CONFIG_CMD_PING
 325 #define CONFIG_CMD_I2C
 326 #define CONFIG_CMD_DATE
 327 #define CONFIG_CMD_EEPROM
 328
 329 #if defined(CONFIG_PCI)
 330     #define CONFIG_CMD_PCI
 331 #endif
 332
 333 #if defined(CONFIG_SYS_RAMBOOT)
 334     #undef CONFIG_CMD_SAVEENV
 335     #undef CONFIG_CMD_LOADS
 336 #endif
 337
 338
 339 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 340
 341 /*
 342  * Miscellaneous configurable options
 343  */
 344 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 345 #define CONFIG_SYS_LOAD_ADDR    0x1000000       /* default load address */
 346 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 347
 348 #if defined(CONFIG_CMD_KGDB)
 349     #define CONFIG_SYS_CBSIZE   1024            /* Console I/O Buffer Size */
 350 #else
 351     #define CONFIG_SYS_CBSIZE   256             /* Console I/O Buffer Size */
 352 #endif
 353
 354 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 355 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 356 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 357 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 358 #define CONFIG_LOOPW
 359
 360 /*
 361  * For booting Linux, the board info and command line data
 362  * have to be in the first 8 MB of memory, since this is
 363  * the maximum mapped by the Linux kernel during initialization.
 364  */
 365 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 366
 367 /*
 368  * Internal Definitions
 369  *
 370  * Boot Flags
 371  */
 372 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 373 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 374
 375 #if defined(CONFIG_CMD_KGDB)
 376 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 377 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 378 #endif
 379
 380
 381 /*
 382  * Environment Configuration
 383  */
 384
 385 /* The mac addresses for all ethernet interface */
 386 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 387 #define CONFIG_HAS_ETH0
 388 #define CONFIG_ETHADDR   00:40:42:01:00:00
 389 #define CONFIG_HAS_ETH1
 390 #define CONFIG_ETH1ADDR  00:40:42:01:00:01
 391 #define CONFIG_HAS_ETH2
 392 #define CONFIG_ETH2ADDR  00:40:42:01:00:02
 393 #endif
 394
 395
 396 #define CONFIG_ROOTPATH         /opt/eldk/ppc_85xx
 397 #define CONFIG_BOOTFILE         pm856/uImage
 398
 399 #define CONFIG_HOSTNAME         pm856
 400 #define CONFIG_IPADDR    192.168.0.103
 401 #define CONFIG_SERVERIP  192.168.0.64
 402 #define CONFIG_GATEWAYIP 192.168.0.1
 403 #define CONFIG_NETMASK   255.255.255.0
 404
 405 #define CONFIG_LOADADDR  200000 /* default location for tftp and bootm */
 406
 407 #define CONFIG_BOOTDELAY 5      /* -1 disables auto-boot */
 408 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 409
 410 #define CONFIG_BAUDRATE 9600
 411
 412 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 413    "netdev=eth0\0"                                                      \
 414    "consoledev=ttyS0\0"                                                 \
 415    "ramdiskaddr=400000\0"                                               \
 416    "ramdiskfile=pm856/uRamdisk\0"
 417
 418 #define CONFIG_NFSBOOTCOMMAND                                           \
 419    "setenv bootargs root=/dev/nfs rw "                                  \
 420       "nfsroot=$serverip:$rootpath "                                    \
 421       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 422       "console=$consoledev,$baudrate $othbootargs;"                     \
 423    "tftp $loadaddr $bootfile;"                                          \
 424    "bootm $loadaddr"
 425
 426 #define CONFIG_RAMBOOTCOMMAND \
 427    "setenv bootargs root=/dev/ram rw "                                  \
 428       "console=$consoledev,$baudrate $othbootargs;"                     \
 429    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 430    "tftp $loadaddr $bootfile;"                                          \
 431    "bootm $loadaddr $ramdiskaddr"
 432
 433 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
 434
 435 #endif  /* __CONFIG_H */