include/configs/PMC405.h

   1 /*
   2  * (C) Copyright 2001-2004
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  */
  14
  15 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  16 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  17 #define CONFIG_PMC405           1       /* ...on a PMC405 board         */
  18
  19 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  20
  21 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  22 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  23
  24 #define CONFIG_SYS_CLK_FREQ     33330000 /* external frequency to pll   */
  25
  26 #define CONFIG_BAUDRATE         9600
  27 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  28
  29 /* Only interrupt boot if space is pressed. */
  30 #define CONFIG_AUTOBOOT_KEYED 1
  31 #define CONFIG_AUTOBOOT_PROMPT  \
  32         "Press SPACE to abort autoboot in %d seconds\n", bootdelay
  33 #undef CONFIG_AUTOBOOT_DELAY_STR
  34 #define CONFIG_AUTOBOOT_STOP_STR " "
  35
  36 #undef CONFIG_BOOTARGS
  37 #undef CONFIG_BOOTCOMMAND
  38
  39 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  40
  41 #define CFG_BOOTM_LEN           0x1000000 /* support booting of huge images */
  42
  43 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  44 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1  /* allow baudrate change        */
  45
  46 #undef  CONFIG_HAS_ETH1
  47
  48 #define CONFIG_PPC4xx_EMAC
  49 #define CONFIG_MII              1       /* MII PHY management           */
  50 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  51 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  52 #define CONFIG_RESET_PHY_R      1       /* use reset_phy()              */
  53
  54 /*
  55  * BOOTP options
  56  */
  57 #define CONFIG_BOOTP_BOOTFILESIZE
  58 #define CONFIG_BOOTP_BOOTPATH
  59 #define CONFIG_BOOTP_GATEWAY
  60 #define CONFIG_BOOTP_HOSTNAME
  61
  62 /*
  63  * Command line configuration.
  64  */
  65 #include <config_cmd_default.h>
  66
  67 #define CONFIG_CMD_BSP
  68 #define CONFIG_CMD_PCI
  69 #define CONFIG_CMD_IRQ
  70 #define CONFIG_CMD_ELF
  71 #define CONFIG_CMD_DATE
  72 #define CONFIG_CMD_JFFS2
  73 #define CONFIG_CMD_MII
  74 #define CONFIG_CMD_I2C
  75 #define CONFIG_CMD_PING
  76 #define CONFIG_CMD_UNIVERSE
  77 #define CONFIG_CMD_EEPROM
  78
  79 #define CONFIG_MAC_PARTITION
  80 #define CONFIG_DOS_PARTITION
  81
  82 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
  83
  84 #define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible */
  85 #define CONFIG_SYS_RTC_REG_BASE_ADDR    0xF0000500 /* RTC Base Address */
  86
  87 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  88
  89 /*
  90  * Miscellaneous configurable options
  91  */
  92 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
  93
  94 #undef CONFIG_SYS_HUSH_PARSER                   /* use "hush" command parser */
  95
  96 #if defined(CONFIG_CMD_KGDB)
  97 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
  98 #else
  99 #define CONFIG_SYS_CBSIZE       512             /* Console I/O Buffer Size */
 100 #endif
 101 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 102 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 103 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Argument Buffer Sz */
 104
 105 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device */
 106
 107 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console info */
 108
 109 #define CONFIG_AUTO_COMPLETE            1       /* add autocompletion support */
 110
 111 #define CONFIG_SYS_MEMTEST_START        0x0400000 /* memtest works on */
 112 #define CONFIG_SYS_MEMTEST_END          0x0C00000 /* 4 ... 12 MB in DRAM */
 113
 114 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 115 #define CONFIG_SYS_NS16550
 116 #define CONFIG_SYS_NS16550_SERIAL
 117 #define CONFIG_SYS_NS16550_REG_SIZE     1
 118 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 119
 120 #undef CONFIG_SYS_EXT_SERIAL_CLOCK              /* no external serial clock */
 121 #define CONFIG_SYS_BASE_BAUD    806400
 122
 123 /* The following table includes the supported baudrates */
 124 #define CONFIG_SYS_BAUDRATE_TABLE       \
 125         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 126
 127 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 128 #define CONFIG_SYS_EXTBDINFO    1       /* To use extended board_into (bd_t) */
 129
 130 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 131 #define CONFIG_LOOPW            1       /* enable loopw command */
 132
 133 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 134
 135 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 136
 137 #define CONFIG_SYS_RX_ETH_BUFFER        16
 138
 139 /*
 140  * PCI stuff
 141  */
 142 #define PCI_HOST_ADAPTER        0       /* configure as pci adapter     */
 143 #define PCI_HOST_FORCE          1       /* configure as pci host        */
 144 #define PCI_HOST_AUTO           2       /* detected via arbiter enable  */
 145
 146 #define CONFIG_PCI                      /* include pci support          */
 147 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 148 #define CONFIG_PCI_HOST PCI_HOST_AUTO   /* select pci host function     */
 149 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 150                                         /* resource configuration       */
 151
 152 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 153
 154 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config */
 155
 156 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh */
 157 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID */
 158 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID */
 159 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid()
 160
 161 #define CONFIG_SYS_PCI_CLASSCODE       0x0b20 /* Processor/PPC */
 162
 163 #define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram      */
 164 #define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable */
 165 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000       /* Host: use this pci address */
 166 #define CONFIG_SYS_PCI_PTM2LA  0xef000000       /* point to internal regs */
 167 #define CONFIG_SYS_PCI_PTM2MS  0xff000001       /* 16MB, enable */
 168 #define CONFIG_SYS_PCI_PTM2PCI 0x00000000       /* Host: use this pci address */
 169
 170 #define CONFIG_PCI_4xx_PTM_OVERWRITE    1 /* overwrite PTMx settings by env */
 171
 172 /*
 173  * Start addresses for the final memory configuration
 174  * (Set up by the startup code)
 175  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 176  */
 177 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 178 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 179 #define CONFIG_SYS_MONITOR_LEN          (~(CONFIG_SYS_TEXT_BASE) + 1)
 180 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024) /* 128 kB for malloc() */
 181
 182 #define CONFIG_PRAM                     0 /* use pram variable to overwrite */
 183
 184 /*
 185  * For booting Linux, the board info and command line data
 186  * have to be in the first 8 MB of memory, since this is
 187  * the maximum mapped by the Linux kernel during initialization.
 188  */
 189 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20) /* Initial Memory map for Linux */
 190
 191 /*
 192  * FLASH organization
 193  */
 194 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 195 #define CONFIG_SYS_FLASH_INCREMENT      0x01000000
 196
 197 #define CONFIG_SYS_FLASH_CFI            1 /* Flash is CFI conformant */
 198 #define CONFIG_FLASH_CFI_DRIVER         1 /* Use the common driver */
 199 #define CONFIG_SYS_FLASH_PROTECTION     1 /* don't use hardware protection */
 200 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST {{0xfff80000, 0x80000}}
 201 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (faster) */
 202 #define CONFIG_SYS_MAX_FLASH_BANKS      2 /* max num of flash banks */
 203 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE, \
 204                         CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT}
 205 #define CONFIG_SYS_MAX_FLASH_SECT       128 /* max num of sects on one chip */
 206 #define CONFIG_SYS_FLASH_EMPTY_INFO     /* print 'E' for empty sector on fli */
 207
 208 /*
 209  * Environment Variable setup
 210  */
 211 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 212
 213 /* environment starts at the beginning of the EEPROM */
 214 #define CONFIG_ENV_OFFSET       0x000
 215 #define CONFIG_ENV_SIZE         0x800 /* 2048 bytes may be used for env vars */
 216
 217 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xF0000500      /* NVRAM base address */
 218 #define CONFIG_SYS_NVRAM_SIZE           242             /* NVRAM size */
 219
 220 /*
 221  * I2C EEPROM (CAT24WC16) for environment
 222  */
 223 #define CONFIG_SYS_I2C
 224 #define CONFIG_SYS_I2C_PPC4XX
 225 #define CONFIG_SYS_I2C_PPC4XX_CH0
 226 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           100000
 227 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 228
 229 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT24W16 */
 230 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address */
 231 /* mask of address bits that overflow into the "EEPROM chip address" */
 232 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 233 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24W16 has */
 234                                         /* 16 byte page write mode using*/
 235                                         /* last 4 bits of the address */
 236
 237 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
 238
 239 /*
 240  * External Bus Controller (EBC) Setup
 241  */
 242 #define FLASH0_BA       0xFF000000      /* FLASH 0 Base Address */
 243 #define FLASH1_BA       0xFE000000      /* FLASH 1 Base Address */
 244 #define CAN_BA          0xF0000000      /* CAN Base Addres      */
 245 #define RTC_BA          0xF0000500      /* RTC Base Address     */
 246 #define NVRAM_BA        0xF0200000      /* NVRAM Base Address   */
 247
 248 /* Memory Bank 0 (Flash Bank 0) initialization */
 249 #define CONFIG_SYS_EBC_PB0AP    0x92015480
 250 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */
 251 #define CONFIG_SYS_EBC_PB0CR    (FLASH0_BA | 0x9A000)
 252
 253 /* Memory Bank 1 (Flash Bank 1) initialization */
 254 #define CONFIG_SYS_EBC_PB1AP    0x92015480
 255 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
 256 #define CONFIG_SYS_EBC_PB1CR    (FLASH1_BA | 0x9A000)
 257
 258 /* Memory Bank 2 (CAN0, 1, RTC) initialization */
 259 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0      */
 260 #define CONFIG_SYS_EBC_PB2AP    0x03000440
 261 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
 262 #define CONFIG_SYS_EBC_PB2CR    (CAN_BA | 0x18000)
 263
 264 /* Memory Bank 3 -> unused */
 265
 266 /* Memory Bank 4 (NVRAM) initialization */
 267 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
 268 #define CONFIG_SYS_EBC_PB4AP    0x03000440
 269 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
 270 #define CONFIG_SYS_EBC_PB4CR    (NVRAM_BA | 0x18000)
 271
 272 /*
 273  * FPGA stuff
 274  */
 275 /* FPGA program pin configuration */
 276 #define CONFIG_SYS_FPGA_PRG             0x04000000 /* JTAG TMS pin (output) */
 277 #define CONFIG_SYS_FPGA_CLK             0x02000000 /* JTAG TCK pin (output) */
 278 #define CONFIG_SYS_FPGA_DATA            0x01000000 /* JTAG TDO pin (output) */
 279 #define CONFIG_SYS_FPGA_INIT            0x00010000 /* unused (ppc input) */
 280 #define CONFIG_SYS_FPGA_DONE            0x00008000 /* JTAG TDI pin (input) */
 281
 282 /* pass Ethernet MAC to VxWorks */
 283 #define CONFIG_SYS_VXWORKS_MAC_PTR      0x00000000
 284
 285 /*
 286  * GPIOs
 287  */
 288 #define CONFIG_SYS_VPEN                 (0x80000000 >>  3) /* GPIO3 */
 289 #define CONFIG_SYS_NONMONARCH           (0x80000000 >> 14) /* GPIO14 */
 290 #define CONFIG_SYS_XEREADY              (0x80000000 >> 15) /* GPIO15 */
 291 #define CONFIG_SYS_INTA_FAKE            (0x80000000 >> 19) /* GPIO19 */
 292 #define CONFIG_SYS_SELF_RST             (0x80000000 >> 21) /* GPIO21 */
 293 #define CONFIG_SYS_REV1_2               (0x80000000 >> 23) /* GPIO23 */
 294
 295 /*
 296  * Definitions for initial stack pointer and data area (in data cache)
 297  */
 298
 299 /* use on chip memory (OCM) for temperary stack until sdram is tested */
 300 #define CONFIG_SYS_TEMP_STACK_OCM       1
 301
 302 /* On Chip Memory location */
 303 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 304 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 305
 306 /* inside of SDRAM */
 307 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR
 308
 309 /* End of used area in RAM */
 310 #define CONFIG_SYS_INIT_RAM_SIZE                CONFIG_SYS_OCM_DATA_SIZE
 311
 312 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 313                                          GENERATED_GBL_DATA_SIZE)
 314 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 315
 316 #define CONFIG_OF_LIBFDT
 317 #define CONFIG_OF_BOARD_SETUP
 318
 319 #endif /* __CONFIG_H */