include/configs/PMC405.h

   1 /*
   2  * (C) Copyright 2001-2004
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * High Level Configuration Options
  29  */
  30
  31 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  32 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  33 #define CONFIG_PMC405           1       /* ...on a PMC405 board         */
  34
  35 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  36
  37 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  38 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  39
  40 #define CONFIG_SYS_CLK_FREQ     33330000 /* external frequency to pll   */
  41
  42 #define CONFIG_BAUDRATE         9600
  43 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  44
  45 /* Only interrupt boot if space is pressed. */
  46 #define CONFIG_AUTOBOOT_KEYED 1
  47 #define CONFIG_AUTOBOOT_PROMPT  \
  48         "Press SPACE to abort autoboot in %d seconds\n", bootdelay
  49 #undef CONFIG_AUTOBOOT_DELAY_STR
  50 #define CONFIG_AUTOBOOT_STOP_STR " "
  51
  52 #undef CONFIG_BOOTARGS
  53 #undef CONFIG_BOOTCOMMAND
  54
  55 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  56
  57 #define CFG_BOOTM_LEN           0x1000000 /* support booting of huge images */
  58
  59 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  60 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1  /* allow baudrate change        */
  61
  62 #define CONFIG_NET_MULTI        1
  63 #undef  CONFIG_HAS_ETH1
  64
  65 #define CONFIG_PPC4xx_EMAC
  66 #define CONFIG_MII              1       /* MII PHY management           */
  67 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  68 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  69 #define CONFIG_RESET_PHY_R      1       /* use reset_phy()              */
  70
  71 /*
  72  * BOOTP options
  73  */
  74 #define CONFIG_BOOTP_BOOTFILESIZE
  75 #define CONFIG_BOOTP_BOOTPATH
  76 #define CONFIG_BOOTP_GATEWAY
  77 #define CONFIG_BOOTP_HOSTNAME
  78
  79 /*
  80  * Command line configuration.
  81  */
  82 #include <config_cmd_default.h>
  83
  84 #define CONFIG_CMD_BSP
  85 #define CONFIG_CMD_PCI
  86 #define CONFIG_CMD_IRQ
  87 #define CONFIG_CMD_ELF
  88 #define CONFIG_CMD_DATE
  89 #define CONFIG_CMD_JFFS2
  90 #define CONFIG_CMD_MII
  91 #define CONFIG_CMD_I2C
  92 #define CONFIG_CMD_PING
  93 #define CONFIG_CMD_UNIVERSE
  94 #define CONFIG_CMD_EEPROM
  95
  96 #define CONFIG_MAC_PARTITION
  97 #define CONFIG_DOS_PARTITION
  98
  99 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 100
 101 #define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible */
 102 #define CONFIG_SYS_RTC_REG_BASE_ADDR    0xF0000500 /* RTC Base Address */
 103
 104 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
 105
 106 /*
 107  * Miscellaneous configurable options
 108  */
 109 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 110 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 111
 112 #undef CONFIG_SYS_HUSH_PARSER                   /* use "hush" command parser */
 113 #ifdef CONFIG_SYS_HUSH_PARSER
 114 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 115 #endif
 116
 117 #if defined(CONFIG_CMD_KGDB)
 118 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 119 #else
 120 #define CONFIG_SYS_CBSIZE       512             /* Console I/O Buffer Size */
 121 #endif
 122 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 123 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 124 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Argument Buffer Sz */
 125
 126 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device */
 127
 128 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console info */
 129
 130 #define CONFIG_AUTO_COMPLETE            1       /* add autocompletion support */
 131
 132 #define CONFIG_SYS_MEMTEST_START        0x0400000 /* memtest works on */
 133 #define CONFIG_SYS_MEMTEST_END          0x0C00000 /* 4 ... 12 MB in DRAM */
 134
 135 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 136 #define CONFIG_SYS_NS16550
 137 #define CONFIG_SYS_NS16550_SERIAL
 138 #define CONFIG_SYS_NS16550_REG_SIZE     1
 139 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 140
 141 #undef CONFIG_SYS_EXT_SERIAL_CLOCK              /* no external serial clock */
 142 #define CONFIG_SYS_BASE_BAUD    806400
 143
 144 /* The following table includes the supported baudrates */
 145 #define CONFIG_SYS_BAUDRATE_TABLE       \
 146         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 147
 148 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 149 #define CONFIG_SYS_EXTBDINFO    1       /* To use extended board_into (bd_t) */
 150
 151 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1 ms ticks */
 152
 153 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 154 #define CONFIG_LOOPW            1       /* enable loopw command */
 155
 156 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 157
 158 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 159
 160 #define CONFIG_SYS_RX_ETH_BUFFER        16
 161
 162 /*
 163  * PCI stuff
 164  */
 165 #define PCI_HOST_ADAPTER        0       /* configure as pci adapter     */
 166 #define PCI_HOST_FORCE          1       /* configure as pci host        */
 167 #define PCI_HOST_AUTO           2       /* detected via arbiter enable  */
 168
 169 #define CONFIG_PCI                      /* include pci support          */
 170 #define CONFIG_PCI_HOST PCI_HOST_AUTO   /* select pci host function     */
 171 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 172                                         /* resource configuration       */
 173
 174 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 175
 176 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config */
 177
 178 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh */
 179 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID */
 180 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID */
 181 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid()
 182
 183 #define CONFIG_SYS_PCI_CLASSCODE       0x0b20 /* Processor/PPC */
 184
 185 #define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram      */
 186 #define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable */
 187 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000       /* Host: use this pci address */
 188 #define CONFIG_SYS_PCI_PTM2LA  0xef000000       /* point to internal regs */
 189 #define CONFIG_SYS_PCI_PTM2MS  0xff000001       /* 16MB, enable */
 190 #define CONFIG_SYS_PCI_PTM2PCI 0x00000000       /* Host: use this pci address */
 191
 192 #define CONFIG_PCI_4xx_PTM_OVERWRITE    1 /* overwrite PTMx settings by env */
 193
 194 /*
 195  * Start addresses for the final memory configuration
 196  * (Set up by the startup code)
 197  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 198  */
 199 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 200 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 201 #define CONFIG_SYS_MONITOR_LEN          (~(CONFIG_SYS_TEXT_BASE) + 1)
 202 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024) /* 128 kB for malloc() */
 203
 204 #define CONFIG_PRAM                     0 /* use pram variable to overwrite */
 205
 206 /*
 207  * For booting Linux, the board info and command line data
 208  * have to be in the first 8 MB of memory, since this is
 209  * the maximum mapped by the Linux kernel during initialization.
 210  */
 211 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20) /* Initial Memory map for Linux */
 212
 213 /*
 214  * FLASH organization
 215  */
 216 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 217 #define CONFIG_SYS_FLASH_INCREMENT      0x01000000
 218
 219 #define CONFIG_SYS_FLASH_CFI            1 /* Flash is CFI conformant */
 220 #define CONFIG_FLASH_CFI_DRIVER         1 /* Use the common driver */
 221 #define CONFIG_SYS_FLASH_PROTECTION     1 /* don't use hardware protection */
 222 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST {{0xfff80000, 0x80000}}
 223 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (faster) */
 224 #define CONFIG_SYS_MAX_FLASH_BANKS      2 /* max num of flash banks */
 225 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE, \
 226                         CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT}
 227 #define CONFIG_SYS_MAX_FLASH_SECT       128 /* max num of sects on one chip */
 228 #define CONFIG_SYS_FLASH_EMPTY_INFO     /* print 'E' for empty sector on fli */
 229
 230 /*
 231  * Environment Variable setup
 232  */
 233 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 234
 235 /* environment starts at the beginning of the EEPROM */
 236 #define CONFIG_ENV_OFFSET       0x000
 237 #define CONFIG_ENV_SIZE         0x800 /* 2048 bytes may be used for env vars */
 238
 239 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xF0000500      /* NVRAM base address */
 240 #define CONFIG_SYS_NVRAM_SIZE           242             /* NVRAM size */
 241
 242 /*
 243  * I2C EEPROM (CAT24WC16) for environment
 244  */
 245 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 246 #define CONFIG_PPC4XX_I2C               /* use PPC4xx driver            */
 247 #define CONFIG_SYS_I2C_SPEED            100000 /* I2C speed and slave address */
 248 #define CONFIG_SYS_I2C_SLAVE            0x7F
 249
 250 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT24W16 */
 251 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address */
 252 /* mask of address bits that overflow into the "EEPROM chip address" */
 253 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 254 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24W16 has */
 255                                         /* 16 byte page write mode using*/
 256                                         /* last 4 bits of the address */
 257
 258 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
 259
 260 /*
 261  * External Bus Controller (EBC) Setup
 262  */
 263 #define FLASH0_BA       0xFF000000      /* FLASH 0 Base Address */
 264 #define FLASH1_BA       0xFE000000      /* FLASH 1 Base Address */
 265 #define CAN_BA          0xF0000000      /* CAN Base Addres      */
 266 #define RTC_BA          0xF0000500      /* RTC Base Address     */
 267 #define NVRAM_BA        0xF0200000      /* NVRAM Base Address   */
 268
 269 /* Memory Bank 0 (Flash Bank 0) initialization */
 270 #define CONFIG_SYS_EBC_PB0AP    0x92015480
 271 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */
 272 #define CONFIG_SYS_EBC_PB0CR    (FLASH0_BA | 0x9A000)
 273
 274 /* Memory Bank 1 (Flash Bank 1) initialization */
 275 #define CONFIG_SYS_EBC_PB1AP    0x92015480
 276 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
 277 #define CONFIG_SYS_EBC_PB1CR    (FLASH1_BA | 0x9A000)
 278
 279 /* Memory Bank 2 (CAN0, 1, RTC) initialization */
 280 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0      */
 281 #define CONFIG_SYS_EBC_PB2AP    0x03000440
 282 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
 283 #define CONFIG_SYS_EBC_PB2CR    (CAN_BA | 0x18000)
 284
 285 /* Memory Bank 3 -> unused */
 286
 287 /* Memory Bank 4 (NVRAM) initialization */
 288 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
 289 #define CONFIG_SYS_EBC_PB4AP    0x03000440
 290 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
 291 #define CONFIG_SYS_EBC_PB4CR    (NVRAM_BA | 0x18000)
 292
 293 /*
 294  * FPGA stuff
 295  */
 296 /* FPGA program pin configuration */
 297 #define CONFIG_SYS_FPGA_PRG             0x04000000 /* JTAG TMS pin (output) */
 298 #define CONFIG_SYS_FPGA_CLK             0x02000000 /* JTAG TCK pin (output) */
 299 #define CONFIG_SYS_FPGA_DATA            0x01000000 /* JTAG TDO pin (output) */
 300 #define CONFIG_SYS_FPGA_INIT            0x00010000 /* unused (ppc input) */
 301 #define CONFIG_SYS_FPGA_DONE            0x00008000 /* JTAG TDI pin (input) */
 302
 303 /* pass Ethernet MAC to VxWorks */
 304 #define CONFIG_SYS_VXWORKS_MAC_PTR      0x00000000
 305
 306 /*
 307  * GPIOs
 308  */
 309 #define CONFIG_SYS_VPEN                 (0x80000000 >>  3) /* GPIO3 */
 310 #define CONFIG_SYS_NONMONARCH           (0x80000000 >> 14) /* GPIO14 */
 311 #define CONFIG_SYS_XEREADY              (0x80000000 >> 15) /* GPIO15 */
 312 #define CONFIG_SYS_INTA_FAKE            (0x80000000 >> 19) /* GPIO19 */
 313 #define CONFIG_SYS_SELF_RST             (0x80000000 >> 21) /* GPIO21 */
 314 #define CONFIG_SYS_REV1_2               (0x80000000 >> 23) /* GPIO23 */
 315
 316 /*
 317  * Definitions for initial stack pointer and data area (in data cache)
 318  */
 319
 320 /* use on chip memory (OCM) for temperary stack until sdram is tested */
 321 #define CONFIG_SYS_TEMP_STACK_OCM       1
 322
 323 /* On Chip Memory location */
 324 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 325 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 326
 327 /* inside of SDRAM */
 328 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR
 329
 330 /* End of used area in RAM */
 331 #define CONFIG_SYS_INIT_RAM_SIZE                CONFIG_SYS_OCM_DATA_SIZE
 332
 333 /* size in bytes reserved for initial data */
 334 #define CONFIG_SYS_GBL_DATA_SIZE        128
 335 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 336                                          CONFIG_SYS_GBL_DATA_SIZE)
 337 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 338
 339 #define CONFIG_OF_LIBFDT
 340 #define CONFIG_OF_BOARD_SETUP
 341
 342 #endif /* __CONFIG_H */