include/configs/PMC405.h

   1 /*
   2  * (C) Copyright 2001-2003
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  37 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  38 #define CONFIG_PMC405           1       /* ...on a PMC405 board         */
  39
  40 #define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
  41 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  42
  43 #define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
  44
  45 #define CONFIG_BAUDRATE         9600
  46 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  47
  48 #undef  CONFIG_BOOTARGS
  49 #define CONFIG_RAMBOOTCOMMAND                                                   \
  50         "setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) "     \
  51         "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"    \
  52         "bootm ffc00000 ffca0000"
  53 #define CONFIG_NFSBOOTCOMMAND                                                   \
  54         "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "     \
  55         "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"    \
  56         "bootm ffc00000"
  57 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
  58
  59 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  60 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
  61
  62 #define CONFIG_MII              1       /* MII PHY management           */
  63 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  64
  65 #define CONFIG_COMMANDS       ( CONFIG_CMD_DFL  | \
  66                                 CFG_CMD_PCI     | \
  67                                 CFG_CMD_IRQ     | \
  68                                 CFG_CMD_ELF     | \
  69                                 CFG_CMD_DATE    | \
  70                                 CFG_CMD_JFFS2   | \
  71                                 CFG_CMD_MII     | \
  72                                 CFG_CMD_I2C     | \
  73                                 CFG_CMD_PING    | \
  74                                 CFG_CMD_EEPROM  )
  75
  76 #define CONFIG_MAC_PARTITION
  77 #define CONFIG_DOS_PARTITION
  78
  79 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  80 #include <cmd_confdefs.h>
  81
  82 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  83
  84 #define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
  85 #define CFG_RTC_REG_BASE_ADDR    0xF0000300 /* RTC Base Address         */
  86
  87 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  88
  89 /*
  90  * Miscellaneous configurable options
  91  */
  92 #define CFG_LONGHELP                    /* undef to save memory         */
  93 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
  94
  95 #undef  CFG_HUSH_PARSER                 /* use "hush" command parser    */
  96 #ifdef  CFG_HUSH_PARSER
  97 #define CFG_PROMPT_HUSH_PS2     "> "
  98 #endif
  99
 100 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 101 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 102 #else
 103 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 104 #endif
 105 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 106 #define CFG_MAXARGS     16              /* max number of command args   */
 107 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 108
 109 #define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
 110
 111 #define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
 112
 113 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 114 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 115
 116 #undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
 117 #define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
 118 #define CFG_BASE_BAUD       691200
 119
 120 /* The following table includes the supported baudrates */
 121 #define CFG_BAUDRATE_TABLE      \
 122         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 123          57600, 115200, 230400, 460800, 921600 }
 124
 125 #define CFG_LOAD_ADDR   0x100000        /* default load address */
 126 #define CFG_EXTBDINFO   1               /* To use extended board_into (bd_t) */
 127
 128 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 129
 130 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 131
 132 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 133
 134 #define CFG_RX_ETH_BUFFER       16      /* use 16 rx buffer on 405 emac */
 135
 136 /*-----------------------------------------------------------------------
 137  * PCI stuff
 138  *-----------------------------------------------------------------------
 139  */
 140 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 141 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 142 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 143
 144 #define CONFIG_PCI                      /* include pci support          */
 145 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 146 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 147                                         /* resource configuration       */
 148
 149 #undef CONFIG_PCI_SCAN_SHOW             /* print pci devices @ startup  */
 150
 151 #define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 152 #define CFG_PCI_SUBSYS_DEVICEID 0x0408  /* PCI Device ID: PMC-405       */
 153 #define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
 154 #define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
 155 #define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
 156 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 157 #define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
 158 #define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
 159 #define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 160
 161 /*-----------------------------------------------------------------------
 162  * Start addresses for the final memory configuration
 163  * (Set up by the startup code)
 164  * Please note that CFG_SDRAM_BASE _must_ start at 0
 165  */
 166 #define CFG_SDRAM_BASE          0x00000000
 167 #define CFG_MONITOR_BASE        0xFFFC0000
 168 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Monitor   */
 169 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserve 128 kB for malloc()  */
 170
 171 /*
 172  * For booting Linux, the board info and command line data
 173  * have to be in the first 8 MB of memory, since this is
 174  * the maximum mapped by the Linux kernel during initialization.
 175  */
 176 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 177
 178 /*-----------------------------------------------------------------------
 179  * FLASH organization
 180  */
 181 #define CFG_FLASH_CFI           1       /* Flash is CFI conformant              */
 182 #define CFG_MAX_FLASH_SECT      128     /* max number of sectors on one chip    */
 183 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
 184 #undef CFG_FLASH_PROTECTION             /* don't use hardware protection        */
 185 #define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
 186 #define CFG_FLASH_BASE          0xFE000000
 187 #define CFG_FLASH_INCREMENT     0x01000000
 188
 189 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 190
 191 #define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
 192 #define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains u-boot    */
 193
 194 /*-----------------------------------------------------------------------
 195  * Environment Variable setup
 196  */
 197 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 198 #define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
 199 #define CFG_ENV_SIZE            0x800   /* 2048 bytes may be used for env vars*/
 200                                    /* total size of a CAT24WC16 is 2048 bytes */
 201
 202 #define CFG_NVRAM_BASE_ADDR     0xF0000500              /* NVRAM base address   */
 203 #define CFG_NVRAM_SIZE          242                     /* NVRAM size           */
 204
 205 /*-----------------------------------------------------------------------
 206  * I2C EEPROM (CAT24WC16) for environment
 207  */
 208 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 209 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 210 #define CFG_I2C_SLAVE           0x7F
 211
 212 #define CFG_I2C_EEPROM_ADDR     0x50    /* EEPROM CAT28WC08             */
 213 #define CFG_I2C_EEPROM_ADDR_LEN 1       /* Bytes of address             */
 214 /* mask of address bits that overflow into the "EEPROM chip address"    */
 215 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x07
 216 #define CFG_EEPROM_PAGE_WRITE_BITS 4    /* The Catalyst CAT24WC08 has   */
 217                                         /* 16 byte page write mode using*/
 218                                         /* last 4 bits of the address   */
 219 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10   /* and takes up to 10 msec */
 220 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 221
 222 /*-----------------------------------------------------------------------
 223  * Cache Configuration
 224  */
 225 #define CFG_DCACHE_SIZE         16384   /* For IBM 405 CPUs, older 405 ppc's    */
 226                                         /* have only 8kB, 16kB is save here     */
 227 #define CFG_CACHELINE_SIZE      32      /* ...                  */
 228 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 229 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value        */
 230 #endif
 231
 232 /*-----------------------------------------------------------------------
 233  * External Bus Controller (EBC) Setup
 234  */
 235 #define FLASH0_BA       0xFF000000          /* FLASH 0 Base Address             */
 236 #define FLASH1_BA       0xFE000000          /* FLASH 1 Base Address             */
 237 #define CAN_BA          0xF0000000          /* CAN Base Address                 */
 238 #define RTC_BA          0xF0000500          /* RTC Base Address                 */
 239 #define CF_BA           0xF0100000          /* CompactFlash Base Address        */
 240
 241 /* Memory Bank 0 (Flash Bank 0) initialization                                  */
 242 #define CFG_EBC_PB0AP   0x92015480
 243 #define CFG_EBC_PB0CR   FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
 244
 245 /* Memory Bank 1 (Flash Bank 1) initialization                                  */
 246 #define CFG_EBC_PB1AP   0x92015480
 247 #define CFG_EBC_PB1CR   FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
 248
 249 /* Memory Bank 2 (CAN0, 1, RTC) initialization                                  */
 250 #define CFG_EBC_PB2AP   0x03000040   /* TWT=6,TH=0,CSN=0,OEN=0,WBN=0,WBF=0      */
 251 #define CFG_EBC_PB2CR   CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 252
 253 /* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization               */
 254 #define CFG_EBC_PB3AP   0x010059C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 255 #define CFG_EBC_PB3CR   CF_BA | 0x1A000     /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 256
 257 /*-----------------------------------------------------------------------
 258  * Definitions for initial stack pointer and data area (in data cache)
 259  */
 260
 261 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 262 #define CFG_TEMP_STACK_OCM      1
 263
 264 /* On Chip Memory location */
 265 #define CFG_OCM_DATA_ADDR       0xF8000000
 266 #define CFG_OCM_DATA_SIZE       0x1000
 267
 268 #define CFG_INIT_RAM_ADDR       CFG_OCM_DATA_ADDR /* inside of SDRAM            */
 269 #define CFG_INIT_RAM_END        CFG_OCM_DATA_SIZE /* End of used area in RAM    */
 270 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 271 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 272 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 273
 274 /*
 275  * Internal Definitions
 276  *
 277  * Boot Flags
 278  */
 279 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 280 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 281
 282 #endif  /* __CONFIG_H */