include/configs/PMC405.h

   1 /*
   2  * (C) Copyright 2001-2004
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  37 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  38 #define CONFIG_PMC405           1       /* ...on a PMC405 board         */
  39
  40 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  41 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  42
  43 #define CONFIG_SYS_CLK_FREQ     33330000 /* external frequency to pll   */
  44
  45 #define CONFIG_BAUDRATE         9600
  46 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  47
  48 #undef  CONFIG_BOOTARGS
  49 #undef  CONFIG_BOOTCOMMAND
  50
  51 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  52
  53 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  54 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
  55
  56 #define CONFIG_NET_MULTI        1
  57 #undef  CONFIG_HAS_ETH1
  58
  59 #define CONFIG_MII              1       /* MII PHY management           */
  60 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  61 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  62 #define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
  63
  64 #define CONFIG_NETCONSOLE               /* include NetConsole support   */
  65
  66 #define CONFIG_COMMANDS       ( CONFIG_CMD_DFL  | \
  67                                 CFG_CMD_BSP     | \
  68                                 CFG_CMD_PCI     | \
  69                                 CFG_CMD_IRQ     | \
  70                                 CFG_CMD_ELF     | \
  71                                 CFG_CMD_DATE    | \
  72                                 CFG_CMD_JFFS2   | \
  73                                 CFG_CMD_MII     | \
  74                                 CFG_CMD_I2C     | \
  75                                 CFG_CMD_PING    | \
  76                                 CFG_CMD_UNIVERSE | \
  77                                 CFG_CMD_EEPROM  )
  78
  79 #define CONFIG_MAC_PARTITION
  80 #define CONFIG_DOS_PARTITION
  81
  82 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  83 #include <cmd_confdefs.h>
  84
  85 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  86
  87 #define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
  88 #define CFG_RTC_REG_BASE_ADDR    0xF0000500 /* RTC Base Address         */
  89
  90 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  91
  92 /*
  93  * Miscellaneous configurable options
  94  */
  95 #define CFG_LONGHELP                    /* undef to save memory         */
  96 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
  97
  98 #undef  CFG_HUSH_PARSER                 /* use "hush" command parser    */
  99 #ifdef  CFG_HUSH_PARSER
 100 #define CFG_PROMPT_HUSH_PS2     "> "
 101 #endif
 102
 103 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 104 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 105 #else
 106 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 107 #endif
 108 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 109 #define CFG_MAXARGS     16              /* max number of command args   */
 110 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 111
 112 #define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
 113
 114 #define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
 115
 116 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
 117
 118 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 119 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 120
 121 #undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
 122 #define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
 123 #define CFG_BASE_BAUD       691200
 124
 125 /* The following table includes the supported baudrates */
 126 #define CFG_BAUDRATE_TABLE      \
 127         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 128          57600, 115200, 230400, 460800, 921600 }
 129
 130 #define CFG_LOAD_ADDR   0x100000        /* default load address */
 131 #define CFG_EXTBDINFO   1               /* To use extended board_into (bd_t) */
 132
 133 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 134
 135 #define CONFIG_LOOPW            1       /* enable loopw command         */
 136
 137 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 138
 139 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 140
 141 #define CFG_RX_ETH_BUFFER       16      /* use 16 rx buffer on 405 emac */
 142
 143 /*-----------------------------------------------------------------------
 144  * PCI stuff
 145  *-----------------------------------------------------------------------
 146  */
 147 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 148 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 149 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 150
 151 #define CONFIG_PCI                      /* include pci support          */
 152 #define CONFIG_PCI_HOST PCI_HOST_AUTO   /* select pci host function     */
 153 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 154                                         /* resource configuration       */
 155
 156 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 157
 158 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 159
 160 #define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 161
 162 #define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 163 #define CFG_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408  /* PCI Device ID: Non-Monarch */
 164 #define CFG_PCI_SUBSYS_DEVICEID_MONARCH 0x0409     /* PCI Device ID: Monarch */
 165 #define CFG_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid()
 166
 167 #define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
 168
 169 #define CFG_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
 170 #define CFG_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
 171 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 172 #if 1
 173 #define CFG_PCI_PTM2LA  0xef000000      /* point to internal regs       */
 174 #define CFG_PCI_PTM2MS  0xff000001      /* 16MB, enable                 */
 175 #define CFG_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
 176 #else /* old mapping */
 177 #define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
 178 #define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
 179 #define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 180 #endif
 181 /*-----------------------------------------------------------------------
 182  * Start addresses for the final memory configuration
 183  * (Set up by the startup code)
 184  * Please note that CFG_SDRAM_BASE _must_ start at 0
 185  */
 186 #define CFG_SDRAM_BASE          0x00000000
 187 #define CFG_MONITOR_BASE        0xFFFC0000
 188 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Monitor   */
 189 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserve 128 kB for malloc()  */
 190
 191 /*
 192  * For booting Linux, the board info and command line data
 193  * have to be in the first 8 MB of memory, since this is
 194  * the maximum mapped by the Linux kernel during initialization.
 195  */
 196 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 197
 198 /*-----------------------------------------------------------------------
 199  * FLASH organization
 200  */
 201 #define CFG_FLASH_BASE          0xFE000000
 202 #define CFG_FLASH_INCREMENT     0x01000000
 203
 204 #define CFG_FLASH_CFI         1       /* Flash is CFI conformant */
 205 #define CFG_FLASH_CFI_DRIVER  1       /* Use the common driver */
 206 #define CFG_FLASH_PROTECTION  1       /* don't use hardware protection        */
 207 #define CFG_FLASH_USE_BUFFER_WRITE 1  /* use buffered writes (20x faster)     */
 208 #define CFG_MAX_FLASH_BANKS   2       /* max num of flash banks */
 209 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + CFG_FLASH_INCREMENT }
 210 #define CFG_MAX_FLASH_SECT    128     /* max num of sects on one chip */
 211
 212 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 213
 214 /*
 215  * JFFS2 partitions - second bank contains u-boot
 216  *
 217  */
 218 /* No command line, one static partition, whole device */
 219 #undef CONFIG_JFFS2_CMDLINE
 220 #define CONFIG_JFFS2_DEV                "nor0"
 221 #define CONFIG_JFFS2_PART_SIZE          0x01b00000
 222 #define CONFIG_JFFS2_PART_OFFSET        0x00400000
 223
 224 /* mtdparts command line support */
 225 /* Note: fake mtd_id used, no linux mtd map file */
 226 /*
 227 #define CONFIG_JFFS2_CMDLINE
 228 #define MTDIDS_DEFAULT          "nor0=pmc405-0"
 229 #define MTDPARTS_DEFAULT        "mtdparts=pmc405-0:-(jffs2)"
 230 */
 231
 232 /*-----------------------------------------------------------------------
 233  * Environment Variable setup
 234  */
 235 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 236 #define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
 237 #define CFG_ENV_SIZE            0x800   /* 2048 bytes may be used for env vars*/
 238                                    /* total size of a CAT24WC16 is 2048 bytes */
 239
 240 #define CFG_NVRAM_BASE_ADDR     0xF0000500              /* NVRAM base address   */
 241 #define CFG_NVRAM_SIZE          242                     /* NVRAM size           */
 242
 243 /*-----------------------------------------------------------------------
 244  * I2C EEPROM (CAT24WC16) for environment
 245  */
 246 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 247 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 248 #define CFG_I2C_SLAVE           0x7F
 249
 250 #define CFG_I2C_EEPROM_ADDR     0x50    /* EEPROM CAT28WC08             */
 251 #define CFG_I2C_EEPROM_ADDR_LEN 1       /* Bytes of address             */
 252 /* mask of address bits that overflow into the "EEPROM chip address"    */
 253 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x07
 254 #define CFG_EEPROM_PAGE_WRITE_BITS 4    /* The Catalyst CAT24WC08 has   */
 255                                         /* 16 byte page write mode using*/
 256                                         /* last 4 bits of the address   */
 257 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10   /* and takes up to 10 msec */
 258 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 259
 260 /*-----------------------------------------------------------------------
 261  * Cache Configuration
 262  */
 263 #define CFG_DCACHE_SIZE         16384   /* For AMCC 405 CPUs, older 405 ppc's   */
 264                                         /* have only 8kB, 16kB is save here     */
 265 #define CFG_CACHELINE_SIZE      32      /* ...                  */
 266 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 267 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value        */
 268 #endif
 269
 270 /*-----------------------------------------------------------------------
 271  * External Bus Controller (EBC) Setup
 272  */
 273 #define FLASH0_BA       0xFF000000          /* FLASH 0 Base Address             */
 274 #define FLASH1_BA       0xFE000000          /* FLASH 1 Base Address             */
 275 #define CAN_BA          0xF0000000          /* CAN Base Address                 */
 276 #define RTC_BA          0xF0000500          /* RTC Base Address                 */
 277 #define NVRAM_BA        0xF0200000          /* NVRAM Base Address               */
 278
 279 /* Memory Bank 0 (Flash Bank 0) initialization                                  */
 280 #define CFG_EBC_PB0AP   0x92015480
 281 #define CFG_EBC_PB0CR   FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
 282
 283 /* Memory Bank 1 (Flash Bank 1) initialization                                  */
 284 #define CFG_EBC_PB1AP   0x92015480
 285 #define CFG_EBC_PB1CR   FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
 286
 287 /* Memory Bank 2 (CAN0, 1, RTC) initialization                                  */
 288 #define CFG_EBC_PB2AP   0x03000440   /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0      */
 289 #define CFG_EBC_PB2CR   CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 290
 291 /* Memory Bank 3 -> unused */
 292
 293 /* Memory Bank 4 (NVRAM) initialization                                 */
 294 #define CFG_EBC_PB4AP   0x03000440   /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0      */
 295 #define CFG_EBC_PB4CR   NVRAM_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit        */
 296
 297 /*-----------------------------------------------------------------------
 298  * FPGA stuff
 299  */
 300 #define CFG_FPGA_XC95XL         1           /* using Xilinx XC95XL CPLD      */
 301 #define CFG_FPGA_MAX_SIZE       32*1024     /* 32kByte is enough for CPLD    */
 302
 303 /* FPGA program pin configuration */
 304 #define CFG_FPGA_PRG            0x04000000  /* JTAG TMS pin (ppc output)     */
 305 #define CFG_FPGA_CLK            0x02000000  /* JTAG TCK pin (ppc output)     */
 306 #define CFG_FPGA_DATA           0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
 307 #define CFG_FPGA_INIT           0x00010000  /* unused (ppc input)            */
 308 #define CFG_FPGA_DONE           0x00008000  /* JTAG TDI->TDO pin (ppc input) */
 309
 310 #define CFG_VXWORKS_MAC_PTR     0x00000000      /* Pass Ethernet MAC to VxWorks */
 311
 312 /*-----------------------------------------------------------------------
 313  * GPIOs
 314  */
 315 #define CFG_NONMONARCH          (0x80000000 >> 14)   /* GPIO24 */
 316 #define CFG_XEREADY             (0x80000000 >> 15)   /* GPIO15 */
 317 #define CFG_INTA_FAKE           (0x80000000 >> 19)   /* GPIO19 */
 318 #define CFG_SELF_RST            (0x80000000 >> 21)   /* GPIO21 */
 319 #define CFG_REV1_2              (0x80000000 >> 23)   /* GPIO23 */
 320
 321 /*-----------------------------------------------------------------------
 322  * Definitions for initial stack pointer and data area (in data cache)
 323  */
 324
 325 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 326 #define CFG_TEMP_STACK_OCM      1
 327
 328 /* On Chip Memory location */
 329 #define CFG_OCM_DATA_ADDR       0xF8000000
 330 #define CFG_OCM_DATA_SIZE       0x1000
 331
 332 #define CFG_INIT_RAM_ADDR       CFG_OCM_DATA_ADDR /* inside of SDRAM            */
 333 #define CFG_INIT_RAM_END        CFG_OCM_DATA_SIZE /* End of used area in RAM    */
 334 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 335 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 336 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 337
 338 /*
 339  * Internal Definitions
 340  *
 341  * Boot Flags
 342  */
 343 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 344 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 345
 346 #endif  /* __CONFIG_H */