include/configs/PN62.h

   1 /*
   2  * (C) Copyright 2002
   3  * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /* ------------------------------------------------------------------------- */
  25
  26 /*
  27  * board/config.h - configuration options, board specific
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37
  38 #define CONFIG_MPC824X          1
  39 #define CONFIG_MPC8240          1
  40 #define CONFIG_PN62             1
  41
  42 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  43
  44 #define CONFIG_CONS_INDEX       1
  45
  46
  47 /*
  48  * BOOTP options
  49  */
  50 #define CONFIG_BOOTP_BOOTFILESIZE
  51 #define CONFIG_BOOTP_BOOTPATH
  52 #define CONFIG_BOOTP_GATEWAY
  53 #define CONFIG_BOOTP_HOSTNAME
  54
  55
  56 /*
  57  * Command line configuration.
  58  */
  59 #include <config_cmd_default.h>
  60
  61 #define CONFIG_CMD_PCI
  62 #define CONFIG_CMD_BSP
  63
  64 #undef CONFIG_CMD_FLASH
  65 #undef CONFIG_CMD_IMLS
  66 #undef CONFIG_CMD_LOADS
  67 #undef CONFIG_CMD_SAVEENV
  68 #undef CONFIG_CMD_SOURCE
  69
  70
  71 #define CONFIG_BAUDRATE         19200   /* console baudrate             */
  72
  73 #define CONFIG_BOOTDELAY        1       /* autoboot after n seconds     */
  74
  75 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  76
  77 #define CONFIG_SERVERIP         10.0.0.201
  78 #define CONFIG_IPADDR           10.0.0.200
  79 #define CONFIG_ROOTPATH         "/opt/eldk/ppc_82xx"
  80 #define CONFIG_NETMASK          255.255.255.0
  81 #undef CONFIG_BOOTARGS
  82 #if 0
  83 /* Boot Linux with NFS root filesystem */
  84 #define CONFIG_BOOTCOMMAND \
  85                         "setenv verify y;" \
  86                         "setenv bootargs console=ttyS0,19200 mem=31M quiet " \
  87                         "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
  88                         "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \
  89                         "loadp 100000; bootm"
  90                         /* "tftpboot 100000 uImage; bootm" */
  91 #else
  92 /* Boot Linux with RAMdisk based filesystem (initrd, BusyBox) */
  93 #define CONFIG_BOOTCOMMAND \
  94                         "setenv verify n;" \
  95                         "setenv bootargs console=ttyS0,19200 mem=31M quiet " \
  96                         "root=/dev/ram rw " \
  97                         "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \
  98                         "loadp 200000; bootm"
  99 #endif
 100
 101 /*
 102  * Miscellaneous configurable options
 103  */
 104 #define CONFIG_SYS_LONGHELP             1               /* undef to save memory         */
 105 #define CONFIG_SYS_PROMPT               "=> "           /* Monitor Command Prompt       */
 106 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
 107 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size    */
 108 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 109 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 110 #define CONFIG_SYS_LOAD_ADDR            0x00100000      /* default load address         */
 111 #define CONFIG_SYS_HZ                   1000            /* decrementer freq: 1 ms ticks */
 112
 113 #define CONFIG_PRAM             1024            /* reserve 1 MB protected RAM   */
 114
 115 #define CONFIG_MISC_INIT_R      1               /* call misc_init_r() on init   */
 116
 117 #define CONFIG_HAS_ETH1         1               /* add support for eth1addr     */
 118
 119 #define CONFIG_SHOW_BOOT_PROGRESS 1             /* Show boot progress on LEDs   */
 120
 121 /*
 122  * PCI stuff
 123  */
 124 #define CONFIG_PCI                              /* include pci support          */
 125 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 126 #define CONFIG_PCI_PNP                          /* we need Plug 'n Play         */
 127 #if 0
 128 #define CONFIG_PCI_SCAN_SHOW                    /* show PCI auto-scan at boot   */
 129 #endif
 130
 131 /*
 132  * Networking stuff
 133  */
 134
 135 #define CONFIG_PCNET                            /* there are 2 AMD PCnet 79C973 */
 136 #define CONFIG_PCNET_79C973
 137
 138 #define _IO_BASE                0xfe000000      /* points to PCI I/O space      */
 139
 140
 141 /*
 142  * Start addresses for the final memory configuration
 143  * (Set up by the startup code)
 144  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 145  */
 146 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 147 #define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
 148
 149 #define CONFIG_SYS_RESET_ADDRESS        0xfff00100
 150
 151 #undef  CONFIG_SYS_RAMBOOT
 152 #define CONFIG_SYS_MONITOR_LEN          0x00030000
 153 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 154
 155
 156 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
 157 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000
 158 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 159
 160
 161 #define CONFIG_SYS_NO_FLASH             1               /* There is no FLASH memory     */
 162
 163 #define CONFIG_ENV_IS_NOWHERE   1               /* Store ENV in memory only     */
 164 #define CONFIG_ENV_OFFSET               0x00004000      /* Offset of Environment Sector */
 165 #define CONFIG_ENV_SIZE         0x00002000      /* Total Size of Environment Sector */
 166
 167 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)     /* Reserve 512 kB for malloc()  */
 168
 169 #define CONFIG_SYS_MEMTEST_START        0x00004000      /* memtest works on             */
 170 #define CONFIG_SYS_MEMTEST_END          0x01f00000      /* 0 ... 32 MB in DRAM          */
 171
 172 /*
 173  * Serial port configuration
 174  */
 175
 176 #define CONFIG_SYS_NS16550
 177 #define CONFIG_SYS_NS16550_SERIAL
 178
 179 #define CONFIG_SYS_NS16550_REG_SIZE     1
 180
 181 #define CONFIG_SYS_NS16550_CLK          1843200
 182
 183 #define CONFIG_SYS_NS16550_COM1 0xff800008
 184 #define CONFIG_SYS_NS16550_COM2 0xff800000
 185
 186 /*
 187  * Low Level Configuration Settings
 188  * (address mappings, register initial values, etc.)
 189  * You should know what you are doing if you make changes here.
 190  */
 191
 192 #define CONFIG_SYS_CLK_FREQ  33333333   /* external frequency to pll */
 193 #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  3
 194
 195 #define CONFIG_SYS_EUMB_ADDR            0xFCE00000
 196
 197 /* MCCR1 */
 198 #define CONFIG_SYS_ROMNAL               3       /* rom/flash next access time           */
 199 #define CONFIG_SYS_ROMFAL               7       /* rom/flash access time                */
 200
 201 /* MCCR2 */
 202 #define CONFIG_SYS_ASRISE               6       /* ASRISE in clocks                     */
 203 #define CONFIG_SYS_ASFALL               12      /* ASFALL in clocks                     */
 204 #define CONFIG_SYS_REFINT               5600    /* REFINT in clocks                     */
 205
 206 /* MCCR3 */
 207 #define CONFIG_SYS_BSTOPRE              0x3cf   /* Burst To Precharge                   */
 208 #define CONFIG_SYS_REFREC               2       /* Refresh to activate interval         */
 209 #define CONFIG_SYS_RDLAT                3       /* data latency from read command       */
 210
 211 /* MCCR4 */
 212 #define CONFIG_SYS_PRETOACT             1       /* Precharge to activate interval       */
 213 #define CONFIG_SYS_ACTTOPRE             3       /* Activate to Precharge interval       */
 214 #define CONFIG_SYS_ACTORW               2       /* Activate to R/W                      */
 215 #define CONFIG_SYS_SDMODE_CAS_LAT       2       /* SDMODE CAS latency                   */
 216 #define CONFIG_SYS_SDMODE_WRAP          0       /* SDMODE Wrap type                     */
 217 #define CONFIG_SYS_SDMODE_BURSTLEN      2       /* SDMODE Burst length 2=4, 3=8         */
 218 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
 219
 220 /* Memory bank settings:
 221  *
 222  * only bits 20-29 are actually used from these vales to set the
 223  * start/qend address the upper two bits will be 0, and the lower 20
 224  * bits will be set to 0x00000 for a start address, or 0xfffff for an
 225  * end address
 226  */
 227 #define CONFIG_SYS_BANK0_START          0x00000000
 228 #define CONFIG_SYS_BANK0_END            (CONFIG_SYS_MAX_RAM_SIZE - 1)
 229 #define CONFIG_SYS_BANK0_ENABLE 1
 230 #define CONFIG_SYS_BANK1_START          0x00000000
 231 #define CONFIG_SYS_BANK1_END            0x00000000
 232 #define CONFIG_SYS_BANK1_ENABLE 0
 233 #define CONFIG_SYS_BANK2_START          0x00000000
 234 #define CONFIG_SYS_BANK2_END            0x00000000
 235 #define CONFIG_SYS_BANK2_ENABLE 0
 236 #define CONFIG_SYS_BANK3_START          0x00000000
 237 #define CONFIG_SYS_BANK3_END            0x00000000
 238 #define CONFIG_SYS_BANK3_ENABLE 0
 239 #define CONFIG_SYS_BANK4_START          0x00000000
 240 #define CONFIG_SYS_BANK4_END            0x00000000
 241 #define CONFIG_SYS_BANK4_ENABLE 0
 242 #define CONFIG_SYS_BANK5_START          0x00000000
 243 #define CONFIG_SYS_BANK5_END            0x00000000
 244 #define CONFIG_SYS_BANK5_ENABLE 0
 245 #define CONFIG_SYS_BANK6_START          0x00000000
 246 #define CONFIG_SYS_BANK6_END            0x00000000
 247 #define CONFIG_SYS_BANK6_ENABLE 0
 248 #define CONFIG_SYS_BANK7_START          0x00000000
 249 #define CONFIG_SYS_BANK7_END            0x00000000
 250 #define CONFIG_SYS_BANK7_ENABLE 0
 251
 252 /*
 253  * Memory bank enable bitmask, specifying which of the banks defined above
 254  * are actually present. MSB is for bank #7, LSB is for bank #0.
 255  */
 256 #define CONFIG_SYS_BANK_ENABLE          0x01
 257
 258 #define CONFIG_SYS_ODCR         0xff    /* configures line driver impedances,   */
 259                                         /* see 8240 book for bit definitions    */
 260 #define CONFIG_SYS_PGMAX                0x32    /* how long the 8240 retains the        */
 261                                         /* currently accessed page in memory    */
 262                                         /* see 8240 book for details            */
 263
 264 /* SDRAM 0 - 256MB */
 265 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 266 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 267
 268 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
 269 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 270
 271 /* PCI memory space */
 272 #define CONFIG_SYS_IBAT2L       (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 273 #define CONFIG_SYS_IBAT2U       (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 274
 275 /* Config addrs, etc */
 276 #define CONFIG_SYS_IBAT3L       (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 277 #define CONFIG_SYS_IBAT3U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 278
 279 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 280 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 281 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 282 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 283 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 284 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 285 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 286 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 287
 288 /*
 289  * For booting Linux, the board info and command line data
 290  * have to be in the first 8 MB of memory, since this is
 291  * the maximum mapped by the Linux kernel during initialization.
 292  */
 293 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 294
 295 /*
 296  * Cache Configuration
 297  */
 298 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8240 CPU                      */
 299 #if defined(CONFIG_CMD_KGDB)
 300 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 301 #endif
 302
 303 #endif  /* __CONFIG_H */