include/configs/PPChameleonEVB.h

   1 /*
   2  * (C) Copyright 2003-2005
   3  * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
   4  *
   5  * (C) Copyright 2003
   6  * DAVE Srl
   7  *
   8  * http://www.dave-tech.it
   9  * http://www.wawnet.biz
  10  * mailto:info@wawnet.biz
  11  *
  12  * Credits: Stefan Roese, Wolfgang Denk
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 /*
  31  * board/config.h - configuration options, board specific
  32  */
  33
  34 #ifndef __CONFIG_H
  35 #define __CONFIG_H
  36
  37 #define CONFIG_PPCHAMELEON_MODULE_BA    0       /* Basic    Model */
  38 #define CONFIG_PPCHAMELEON_MODULE_ME    1       /* Medium   Model */
  39 #define CONFIG_PPCHAMELEON_MODULE_HI    2       /* High-End Model */
  40 #ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
  41 #define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
  42 #endif
  43
  44
  45 /* Only one of the following two symbols must be defined (default is 25 MHz)
  46  * CONFIG_PPCHAMELEON_CLK_25
  47  * CONFIG_PPCHAMELEON_CLK_33
  48  */
  49 #if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
  50 #define CONFIG_PPCHAMELEON_CLK_25
  51 #endif
  52
  53 #if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
  54 #error "* Two external frequencies (SysClk) are defined! *"
  55 #endif
  56
  57 #undef  CONFIG_PPCHAMELEON_SMI712
  58
  59 /*
  60  * Debug stuff
  61  */
  62 #undef  __DEBUG_START_FROM_SRAM__
  63 #define __DISABLE_MACHINE_EXCEPTION__
  64
  65 #ifdef __DEBUG_START_FROM_SRAM__
  66 #define CFG_DUMMY_FLASH_SIZE            1024*1024*4
  67 #endif
  68
  69 /*
  70  * High Level Configuration Options
  71  * (easy to change)
  72  */
  73
  74 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  75 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  76 #define CONFIG_PPCHAMELEONEVB   1       /* ...on a PPChameleonEVB board */
  77
  78 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  79 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  80
  81
  82 #ifdef CONFIG_PPCHAMELEON_CLK_25
  83 # define CONFIG_SYS_CLK_FREQ    25000000 /* external frequency to pll   */
  84 #elif (defined (CONFIG_PPCHAMELEON_CLK_33))
  85 # define CONFIG_SYS_CLK_FREQ    33333333 /* external frequency to pll   */
  86 #else
  87 # error "* External frequency (SysClk) not defined! *"
  88 #endif
  89
  90 #define CONFIG_BAUDRATE         115200
  91 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  92
  93 #undef  CONFIG_BOOTARGS
  94
  95 /* Ethernet stuff */
  96 #define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
  97 #define CONFIG_ETHADDR  00:50:c2:1e:af:fe
  98 #define CONFIG_HAS_ETH1
  99 #define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd
 100
 101 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 102 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 103
 104 #undef CONFIG_EXT_PHY
 105 #define CONFIG_NET_MULTI        1
 106
 107 #define CONFIG_MII              1       /* MII PHY management           */
 108 #ifndef  CONFIG_EXT_PHY
 109 #define CONFIG_PHY_ADDR         1       /* EMAC0 PHY address            */
 110 #define CONFIG_PHY1_ADDR        2       /* EMAC1 PHY address            */
 111 #else
 112 #define CONFIG_PHY_ADDR         2       /* PHY address                  */
 113 #endif
 114 #define CONFIG_PHY_CLK_FREQ     EMAC_STACR_CLK_66MHZ
 115
 116 #define CONFIG_COMMANDS       ( CONFIG_CMD_DFL  | \
 117                                 CFG_CMD_DATE    | \
 118                                 CFG_CMD_DHCP    | \
 119                                 CFG_CMD_ELF     | \
 120                                 CFG_CMD_EEPROM  | \
 121                                 CFG_CMD_I2C     | \
 122                                 CFG_CMD_IRQ     | \
 123                                 CFG_CMD_JFFS2   | \
 124                                 CFG_CMD_MII     | \
 125                                 CFG_CMD_NAND    | \
 126                                 CFG_CMD_NFS     | \
 127                                 CFG_CMD_PCI     | \
 128                                 CFG_CMD_SNTP    )
 129
 130 #define CONFIG_MAC_PARTITION
 131 #define CONFIG_DOS_PARTITION
 132
 133 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 134 #include <cmd_confdefs.h>
 135
 136 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 137
 138 #define CONFIG_RTC_M41T11       1       /* uses a M41T00 RTC            */
 139 #define CFG_I2C_RTC_ADDR        0x68
 140 #define CFG_M41T11_BASE_YEAR    1900
 141
 142 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
 143
 144 /*
 145  * Miscellaneous configurable options
 146  */
 147 #define CFG_LONGHELP                    /* undef to save memory         */
 148 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 149
 150 #undef  CFG_HUSH_PARSER                 /* use "hush" command parser    */
 151 #ifdef  CFG_HUSH_PARSER
 152 #define CFG_PROMPT_HUSH_PS2     "> "
 153 #endif
 154
 155 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 156 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 157 #else
 158 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 159 #endif
 160 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 161 #define CFG_MAXARGS     16              /* max number of command args   */
 162 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 163
 164 #define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
 165
 166 #define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
 167
 168 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 169 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 170
 171 #undef  CFG_EXT_SERIAL_CLOCK            /* no external serial clock used */
 172 #define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
 173 #define CFG_BASE_BAUD           691200
 174
 175 /* The following table includes the supported baudrates */
 176 #define CFG_BAUDRATE_TABLE      \
 177         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 178          57600, 115200, 230400, 460800, 921600 }
 179
 180 #define CFG_LOAD_ADDR   0x100000        /* default load address */
 181 #define CFG_EXTBDINFO   1               /* To use extended board_into (bd_t) */
 182
 183 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 184
 185 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 186
 187 /*-----------------------------------------------------------------------
 188  * NAND-FLASH stuff
 189  *-----------------------------------------------------------------------
 190  */
 191
 192 /* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
 193 #define CONFIG_NEW_NAND_CODE
 194 #define CFG_NAND0_BASE 0xFF400000
 195 #define CFG_NAND1_BASE 0xFF000000
 196 #define CFG_NAND_BASE_LIST      { CFG_NAND0_BASE, CFG_NAND1_BASE }
 197 #define NAND_BIG_DELAY_US       25
 198 #define CFG_MAX_NAND_DEVICE     2       /* Max number of NAND devices */
 199 #define SECTORSIZE 512
 200 #define NAND_NO_RB
 201
 202 #define ADDR_COLUMN 1
 203 #define ADDR_PAGE 2
 204 #define ADDR_COLUMN_PAGE 3
 205
 206 #define NAND_ChipID_UNKNOWN     0x00
 207 #define NAND_MAX_FLOORS 1
 208 #define NAND_MAX_CHIPS 1
 209
 210 #define CFG_NAND0_CE  (0x80000000 >> 1)  /* our CE is GPIO1 */
 211 #define CFG_NAND0_CLE (0x80000000 >> 2)  /* our CLE is GPIO2 */
 212 #define CFG_NAND0_ALE (0x80000000 >> 3)  /* our ALE is GPIO3 */
 213 #define CFG_NAND0_RDY (0x80000000 >> 4)  /* our RDY is GPIO4 */
 214
 215 #define CFG_NAND1_CE  (0x80000000 >> 14)  /* our CE is GPIO14 */
 216 #define CFG_NAND1_CLE (0x80000000 >> 15)  /* our CLE is GPIO15 */
 217 #define CFG_NAND1_ALE (0x80000000 >> 16)  /* our ALE is GPIO16 */
 218 #define CFG_NAND1_RDY (0x80000000 >> 31)  /* our RDY is GPIO31 */
 219
 220 #ifdef CONFIG_NEW_NAND_CODE
 221 #define MACRO_NAND_DISABLE_CE(nandptr) do \
 222 { \
 223         switch((unsigned long)nandptr) \
 224         { \
 225             case CFG_NAND0_BASE: \
 226                 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
 227                 break; \
 228             case CFG_NAND1_BASE: \
 229                 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
 230                 break; \
 231         } \
 232 } while(0)
 233
 234 #define MACRO_NAND_ENABLE_CE(nandptr) do \
 235 { \
 236         switch((unsigned long)nandptr) \
 237         { \
 238             case CFG_NAND0_BASE: \
 239                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
 240                 break; \
 241             case CFG_NAND1_BASE: \
 242                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
 243                 break; \
 244         } \
 245 } while(0)
 246
 247 #define MACRO_NAND_CTL_CLRALE(nandptr) do \
 248 { \
 249         switch((unsigned long)nandptr) \
 250         { \
 251             case CFG_NAND0_BASE: \
 252                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
 253                 break; \
 254             case CFG_NAND1_BASE: \
 255                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
 256                 break; \
 257         } \
 258 } while(0)
 259
 260 #define MACRO_NAND_CTL_SETALE(nandptr) do \
 261 { \
 262         switch((unsigned long)nandptr) \
 263         { \
 264             case CFG_NAND0_BASE: \
 265                 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
 266                 break; \
 267             case CFG_NAND1_BASE: \
 268                 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
 269                 break; \
 270         } \
 271 } while(0)
 272
 273 #define MACRO_NAND_CTL_CLRCLE(nandptr) do \
 274 { \
 275         switch((unsigned long)nandptr) \
 276         { \
 277             case CFG_NAND0_BASE: \
 278                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
 279                 break; \
 280             case CFG_NAND1_BASE: \
 281                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
 282                 break; \
 283         } \
 284 } while(0)
 285
 286 #define MACRO_NAND_CTL_SETCLE(nandptr) do { \
 287         switch((unsigned long)nandptr) { \
 288         case CFG_NAND0_BASE: \
 289                 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
 290                 break; \
 291         case CFG_NAND1_BASE: \
 292                 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
 293                 break; \
 294         } \
 295 } while(0)
 296 #else
 297 #define NAND_DISABLE_CE(nand) do \
 298 { \
 299         switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
 300         { \
 301             case CFG_NAND0_BASE: \
 302                 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
 303                 break; \
 304             case CFG_NAND1_BASE: \
 305                 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
 306                 break; \
 307         } \
 308 } while(0)
 309
 310 #define NAND_ENABLE_CE(nand) do \
 311 { \
 312         switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
 313         { \
 314             case CFG_NAND0_BASE: \
 315                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
 316                 break; \
 317             case CFG_NAND1_BASE: \
 318                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
 319                 break; \
 320         } \
 321 } while(0)
 322
 323 #define NAND_CTL_CLRALE(nandptr) do \
 324 { \
 325         switch((unsigned long)nandptr) \
 326         { \
 327             case CFG_NAND0_BASE: \
 328                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
 329                 break; \
 330             case CFG_NAND1_BASE: \
 331                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
 332                 break; \
 333         } \
 334 } while(0)
 335
 336 #define NAND_CTL_SETALE(nandptr) do \
 337 { \
 338         switch((unsigned long)nandptr) \
 339         { \
 340             case CFG_NAND0_BASE: \
 341                 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
 342                 break; \
 343             case CFG_NAND1_BASE: \
 344                 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
 345                 break; \
 346         } \
 347 } while(0)
 348
 349 #define NAND_CTL_CLRCLE(nandptr) do \
 350 { \
 351         switch((unsigned long)nandptr) \
 352         { \
 353             case CFG_NAND0_BASE: \
 354                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
 355                 break; \
 356             case CFG_NAND1_BASE: \
 357                 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
 358                 break; \
 359         } \
 360 } while(0)
 361
 362 #define NAND_CTL_SETCLE(nandptr) do { \
 363         switch((unsigned long)nandptr) { \
 364         case CFG_NAND0_BASE: \
 365                 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
 366                 break; \
 367         case CFG_NAND1_BASE: \
 368                 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
 369                 break; \
 370         } \
 371 } while(0)
 372 #endif /* !CONFIG_NEW_NAND_CODE */
 373
 374 #ifdef NAND_NO_RB
 375 /* constant delay (see also tR in the datasheet) */
 376 #define NAND_WAIT_READY(nand) do { \
 377         udelay(12); \
 378 } while (0)
 379 #else
 380 /* use the R/B pin */
 381 /* TBD */
 382 #endif
 383
 384 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
 385 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
 386 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
 387 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
 388
 389 /*-----------------------------------------------------------------------
 390  * PCI stuff
 391  *-----------------------------------------------------------------------
 392  */
 393 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 394 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 395 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 396
 397 #define CONFIG_PCI                      /* include pci support          */
 398 #define CONFIG_PCI_HOST PCI_HOST_FORCE   /* select pci host function     */
 399 #undef  CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 400                                         /* resource configuration       */
 401
 402 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 403
 404 #define CFG_PCI_SUBSYS_VENDORID 0x1014  /* PCI Vendor ID: IBM   */
 405 #define CFG_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: ---   */
 406 #define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
 407
 408 #define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
 409 #define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
 410 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 411 #define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
 412 #define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
 413 #define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 414
 415 /*-----------------------------------------------------------------------
 416  * Start addresses for the final memory configuration
 417  * (Set up by the startup code)
 418  * Please note that CFG_SDRAM_BASE _must_ start at 0
 419  */
 420 #define CFG_SDRAM_BASE          0x00000000
 421
 422 /* Reserve 256 kB for Monitor   */
 423 /*
 424 #define CFG_FLASH_BASE          0xFFFC0000
 425 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 426 #define CFG_MONITOR_LEN         (256 * 1024)
 427 */
 428
 429 /* Reserve 320 kB for Monitor   */
 430 #define CFG_FLASH_BASE          0xFFFB0000
 431 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 432 #define CFG_MONITOR_LEN         (320 * 1024)
 433
 434 #define CFG_MALLOC_LEN          (256 * 1024)    /* Reserve 256 kB for malloc()  */
 435
 436 /*
 437  * For booting Linux, the board info and command line data
 438  * have to be in the first 8 MB of memory, since this is
 439  * the maximum mapped by the Linux kernel during initialization.
 440  */
 441 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 442 /*-----------------------------------------------------------------------
 443  * FLASH organization
 444  */
 445 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 446 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
 447
 448 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 449 #define CFG_FLASH_WRITE_TOUT    1000    /* Timeout for Flash Write (in ms)      */
 450
 451 #define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
 452 #define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
 453 #define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
 454 /*
 455  * The following defines are added for buggy IOP480 byte interface.
 456  * All other boards should use the standard values (CPCI405 etc.)
 457  */
 458 #define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
 459 #define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
 460 #define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
 461
 462 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 463
 464 /*-----------------------------------------------------------------------
 465  * Environment Variable setup
 466  */
 467 #ifdef ENVIRONMENT_IN_EEPROM
 468
 469 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 470 #define CFG_ENV_OFFSET          0x100   /* environment starts at the beginning of the EEPROM */
 471 #define CFG_ENV_SIZE            0x700   /* 2048-256 bytes may be used for env vars (total size of a CAT24WC16 is 2048 bytes)*/
 472
 473 #else   /* DEFAULT: environment in flash, using redundand flash sectors */
 474
 475 #define CFG_ENV_IS_IN_FLASH     1       /* use FLASH for environment vars */
 476 #define CFG_ENV_ADDR            0xFFFF8000      /* environment starts at the first small sector */
 477 #define CFG_ENV_SECT_SIZE       0x2000  /* 8196 bytes may be used for env vars*/
 478 #define CFG_ENV_ADDR_REDUND     0xFFFFA000
 479 #define CFG_ENV_SIZE_REDUND     0x2000
 480
 481 #endif  /* ENVIRONMENT_IN_EEPROM */
 482
 483
 484 #define CFG_NVRAM_BASE_ADDR     0xF0000500              /* NVRAM base address   */
 485 #define CFG_NVRAM_SIZE          242                     /* NVRAM size           */
 486
 487 /*-----------------------------------------------------------------------
 488  * I2C EEPROM (CAT24WC16) for environment
 489  */
 490 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 491 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address */
 492 #define CFG_I2C_SLAVE           0x7F
 493
 494 #define CFG_I2C_EEPROM_ADDR     0x50    /* EEPROM CAT28WC08             */
 495 #define CFG_I2C_EEPROM_ADDR_LEN 1       /* Bytes of address             */
 496 /* mask of address bits that overflow into the "EEPROM chip address"    */
 497 /*#define CFG_I2C_EEPROM_ADDR_OVERFLOW  0x07*/
 498 #define CFG_EEPROM_PAGE_WRITE_BITS 4    /* The Catalyst CAT24WC08 has   */
 499                                         /* 16 byte page write mode using*/
 500                                         /* last 4 bits of the address   */
 501 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10   /* and takes up to 10 msec */
 502 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 503
 504 /*-----------------------------------------------------------------------
 505  * Cache Configuration
 506  */
 507 #define CFG_DCACHE_SIZE         16384   /* For AMCC 405 CPUs, older 405 ppc's   */
 508                                         /* have only 8kB, 16kB is save here     */
 509 #define CFG_CACHELINE_SIZE      32      /* ...                  */
 510 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 511 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value        */
 512 #endif
 513
 514 /*
 515  * Init Memory Controller:
 516  *
 517  * BR0/1 and OR0/1 (FLASH)
 518  */
 519
 520 #define FLASH_BASE0_PRELIM      0xFFC00000      /* FLASH bank #0        */
 521
 522 /*-----------------------------------------------------------------------
 523  * External Bus Controller (EBC) Setup
 524  */
 525
 526 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 527 #define CFG_EBC_PB0AP           0x92015480
 528 #define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 529
 530 /* Memory Bank 1 (External SRAM) initialization                                 */
 531 /* Since this must replace NOR Flash, we use the same settings for CS0          */
 532 #define CFG_EBC_PB1AP           0x92015480
 533 #define CFG_EBC_PB1CR           0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
 534
 535 /* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization                      */
 536 #define CFG_EBC_PB2AP           0x92015480
 537 #define CFG_EBC_PB2CR           0xFF458000  /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit  */
 538
 539 /* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization                      */
 540 #define CFG_EBC_PB3AP           0x92015480
 541 #define CFG_EBC_PB3CR           0xFF058000  /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit  */
 542
 543 #ifdef CONFIG_PPCHAMELEON_SMI712
 544 /*
 545  * Video console (graphic: SMI LynxEM)
 546  */
 547 #define CONFIG_VIDEO
 548 #define CONFIG_CFB_CONSOLE
 549 #define CONFIG_VIDEO_SMI_LYNXEM
 550 #define CONFIG_VIDEO_LOGO
 551 /*#define CONFIG_VIDEO_BMP_LOGO*/
 552 #define CONFIG_CONSOLE_EXTRA_INFO
 553 #define CONFIG_VGA_AS_SINGLE_DEVICE
 554 /* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
 555 #define CFG_ISA_IO 0xE8000000
 556 /* see also drivers/videomodes.c */
 557 #define CFG_DEFAULT_VIDEO_MODE 0x303
 558 #endif
 559
 560 /*-----------------------------------------------------------------------
 561  * FPGA stuff
 562  */
 563 /* FPGA internal regs */
 564 #define CFG_FPGA_MODE           0x00
 565 #define CFG_FPGA_STATUS         0x02
 566 #define CFG_FPGA_TS             0x04
 567 #define CFG_FPGA_TS_LOW         0x06
 568 #define CFG_FPGA_TS_CAP0        0x10
 569 #define CFG_FPGA_TS_CAP0_LOW    0x12
 570 #define CFG_FPGA_TS_CAP1        0x14
 571 #define CFG_FPGA_TS_CAP1_LOW    0x16
 572 #define CFG_FPGA_TS_CAP2        0x18
 573 #define CFG_FPGA_TS_CAP2_LOW    0x1a
 574 #define CFG_FPGA_TS_CAP3        0x1c
 575 #define CFG_FPGA_TS_CAP3_LOW    0x1e
 576
 577 /* FPGA Mode Reg */
 578 #define CFG_FPGA_MODE_CF_RESET  0x0001
 579 #define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
 580 #define CFG_FPGA_MODE_TS_IRQ_CLEAR  0x1000
 581 #define CFG_FPGA_MODE_TS_CLEAR  0x2000
 582
 583 /* FPGA Status Reg */
 584 #define CFG_FPGA_STATUS_DIP0    0x0001
 585 #define CFG_FPGA_STATUS_DIP1    0x0002
 586 #define CFG_FPGA_STATUS_DIP2    0x0004
 587 #define CFG_FPGA_STATUS_FLASH   0x0008
 588 #define CFG_FPGA_STATUS_TS_IRQ  0x1000
 589
 590 #define CFG_FPGA_SPARTAN2       1               /* using Xilinx Spartan 2 now    */
 591 #define CFG_FPGA_MAX_SIZE       128*1024        /* 128kByte is enough for XC2S50E*/
 592
 593 /* FPGA program pin configuration */
 594 #define CFG_FPGA_PRG            0x04000000      /* FPGA program pin (ppc output) */
 595 #define CFG_FPGA_CLK            0x02000000      /* FPGA clk pin (ppc output)     */
 596 #define CFG_FPGA_DATA           0x01000000      /* FPGA data pin (ppc output)    */
 597 #define CFG_FPGA_INIT           0x00010000      /* FPGA init pin (ppc input)     */
 598 #define CFG_FPGA_DONE           0x00008000      /* FPGA done pin (ppc input)     */
 599
 600 /*-----------------------------------------------------------------------
 601  * Definitions for initial stack pointer and data area (in data cache)
 602  */
 603 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 604 #define CFG_TEMP_STACK_OCM      1
 605
 606 /* On Chip Memory location */
 607 #define CFG_OCM_DATA_ADDR       0xF8000000
 608 #define CFG_OCM_DATA_SIZE       0x1000
 609 #define CFG_INIT_RAM_ADDR       CFG_OCM_DATA_ADDR /* inside of SDRAM            */
 610 #define CFG_INIT_RAM_END        CFG_OCM_DATA_SIZE /* End of used area in RAM    */
 611
 612 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 613 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 614 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 615
 616 /*-----------------------------------------------------------------------
 617  * Definitions for GPIO setup (PPC405EP specific)
 618  *
 619  * GPIO0[0]     - External Bus Controller BLAST output
 620  * GPIO0[1-9]   - Instruction trace outputs -> GPIO
 621  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 622  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
 623  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 624  * GPIO0[24-27] - UART0 control signal inputs/outputs
 625  * GPIO0[28-29] - UART1 data signal input/output
 626  * GPIO0[30]    - EMAC0 input
 627  * GPIO0[31]    - EMAC1 reject packet as output
 628  */
 629 #define CFG_GPIO0_OSRH          0x40000550
 630 #define CFG_GPIO0_OSRL          0x00000110
 631 #define CFG_GPIO0_ISR1H         0x00000000
 632 /*#define CFG_GPIO0_ISR1L       0x15555445*/
 633 #define CFG_GPIO0_ISR1L         0x15555444
 634 #define CFG_GPIO0_TSRH          0x00000000
 635 #define CFG_GPIO0_TSRL          0x00000000
 636 #define CFG_GPIO0_TCR           0xF7FF8014
 637
 638 /*
 639  * Internal Definitions
 640  *
 641  * Boot Flags
 642  */
 643 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 644 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 645
 646
 647 #define CONFIG_NO_SERIAL_EEPROM
 648
 649 /*--------------------------------------------------------------------*/
 650
 651 #ifdef CONFIG_NO_SERIAL_EEPROM
 652
 653 /*
 654 !-----------------------------------------------------------------------
 655 ! Defines for entry options.
 656 ! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
 657 !       are plugged in the board will be utilized as non-ECC DIMMs.
 658 !-----------------------------------------------------------------------
 659 */
 660 #undef          AUTO_MEMORY_CONFIG
 661 #define         DIMM_READ_ADDR 0xAB
 662 #define         DIMM_WRITE_ADDR 0xAA
 663
 664 #define CPC0_PLLMR0  (CNTRL_DCR_BASE+0x0)  /* PLL mode 0 register               */
 665 #define CPC0_BOOT    (CNTRL_DCR_BASE+0x1)  /* Chip Clock Status register        */
 666 #define CPC0_CR1     (CNTRL_DCR_BASE+0x2)  /* Chip Control 1 register           */
 667 #define CPC0_EPRCSR  (CNTRL_DCR_BASE+0x3)  /* EMAC PHY Rcv Clk Src register     */
 668 #define CPC0_PLLMR1  (CNTRL_DCR_BASE+0x4)  /* PLL mode 1 register               */
 669 #define CPC0_UCR     (CNTRL_DCR_BASE+0x5)  /* UART Control register             */
 670 #define CPC0_SRR     (CNTRL_DCR_BASE+0x6)  /* Soft Reset register               */
 671 #define CPC0_JTAGID  (CNTRL_DCR_BASE+0x7)  /* JTAG ID register                  */
 672 #define CPC0_SPARE   (CNTRL_DCR_BASE+0x8)  /* Spare DCR                         */
 673 #define CPC0_PCI     (CNTRL_DCR_BASE+0x9)  /* PCI Control register              */
 674
 675 /* Defines for CPC0_PLLMR1 Register fields */
 676 #define PLL_ACTIVE              0x80000000
 677 #define CPC0_PLLMR1_SSCS        0x80000000
 678 #define PLL_RESET               0x40000000
 679 #define CPC0_PLLMR1_PLLR        0x40000000
 680     /* Feedback multiplier */
 681 #define PLL_FBKDIV              0x00F00000
 682 #define CPC0_PLLMR1_FBDV        0x00F00000
 683 #define PLL_FBKDIV_16           0x00000000
 684 #define PLL_FBKDIV_1            0x00100000
 685 #define PLL_FBKDIV_2            0x00200000
 686 #define PLL_FBKDIV_3            0x00300000
 687 #define PLL_FBKDIV_4            0x00400000
 688 #define PLL_FBKDIV_5            0x00500000
 689 #define PLL_FBKDIV_6            0x00600000
 690 #define PLL_FBKDIV_7            0x00700000
 691 #define PLL_FBKDIV_8            0x00800000
 692 #define PLL_FBKDIV_9            0x00900000
 693 #define PLL_FBKDIV_10           0x00A00000
 694 #define PLL_FBKDIV_11           0x00B00000
 695 #define PLL_FBKDIV_12           0x00C00000
 696 #define PLL_FBKDIV_13           0x00D00000
 697 #define PLL_FBKDIV_14           0x00E00000
 698 #define PLL_FBKDIV_15           0x00F00000
 699     /* Forward A divisor */
 700 #define PLL_FWDDIVA             0x00070000
 701 #define CPC0_PLLMR1_FWDVA       0x00070000
 702 #define PLL_FWDDIVA_8           0x00000000
 703 #define PLL_FWDDIVA_7           0x00010000
 704 #define PLL_FWDDIVA_6           0x00020000
 705 #define PLL_FWDDIVA_5           0x00030000
 706 #define PLL_FWDDIVA_4           0x00040000
 707 #define PLL_FWDDIVA_3           0x00050000
 708 #define PLL_FWDDIVA_2           0x00060000
 709 #define PLL_FWDDIVA_1           0x00070000
 710     /* Forward B divisor */
 711 #define PLL_FWDDIVB             0x00007000
 712 #define CPC0_PLLMR1_FWDVB       0x00007000
 713 #define PLL_FWDDIVB_8           0x00000000
 714 #define PLL_FWDDIVB_7           0x00001000
 715 #define PLL_FWDDIVB_6           0x00002000
 716 #define PLL_FWDDIVB_5           0x00003000
 717 #define PLL_FWDDIVB_4           0x00004000
 718 #define PLL_FWDDIVB_3           0x00005000
 719 #define PLL_FWDDIVB_2           0x00006000
 720 #define PLL_FWDDIVB_1           0x00007000
 721     /* PLL tune bits */
 722 #define PLL_TUNE_MASK           0x000003FF
 723 #define PLL_TUNE_2_M_3          0x00000133      /*  2 <= M <= 3                 */
 724 #define PLL_TUNE_4_M_6          0x00000134      /*  3 <  M <= 6                 */
 725 #define PLL_TUNE_7_M_10         0x00000138      /*  6 <  M <= 10                */
 726 #define PLL_TUNE_11_M_14        0x0000013C      /* 10 <  M <= 14                */
 727 #define PLL_TUNE_15_M_40        0x0000023E      /* 14 <  M <= 40                */
 728 #define PLL_TUNE_VCO_LOW        0x00000000      /* 500MHz <= VCO <=  800MHz     */
 729 #define PLL_TUNE_VCO_HI         0x00000080      /* 800MHz <  VCO <= 1000MHz     */
 730
 731 /* Defines for CPC0_PLLMR0 Register fields */
 732     /* CPU divisor */
 733 #define PLL_CPUDIV              0x00300000
 734 #define CPC0_PLLMR0_CCDV        0x00300000
 735 #define PLL_CPUDIV_1            0x00000000
 736 #define PLL_CPUDIV_2            0x00100000
 737 #define PLL_CPUDIV_3            0x00200000
 738 #define PLL_CPUDIV_4            0x00300000
 739     /* PLB divisor */
 740 #define PLL_PLBDIV              0x00030000
 741 #define CPC0_PLLMR0_CBDV        0x00030000
 742 #define PLL_PLBDIV_1            0x00000000
 743 #define PLL_PLBDIV_2            0x00010000
 744 #define PLL_PLBDIV_3            0x00020000
 745 #define PLL_PLBDIV_4            0x00030000
 746     /* OPB divisor */
 747 #define PLL_OPBDIV              0x00003000
 748 #define CPC0_PLLMR0_OPDV        0x00003000
 749 #define PLL_OPBDIV_1            0x00000000
 750 #define PLL_OPBDIV_2            0x00001000
 751 #define PLL_OPBDIV_3            0x00002000
 752 #define PLL_OPBDIV_4            0x00003000
 753     /* EBC divisor */
 754 #define PLL_EXTBUSDIV           0x00000300
 755 #define CPC0_PLLMR0_EPDV        0x00000300
 756 #define PLL_EXTBUSDIV_2         0x00000000
 757 #define PLL_EXTBUSDIV_3         0x00000100
 758 #define PLL_EXTBUSDIV_4         0x00000200
 759 #define PLL_EXTBUSDIV_5         0x00000300
 760     /* MAL divisor */
 761 #define PLL_MALDIV              0x00000030
 762 #define CPC0_PLLMR0_MPDV        0x00000030
 763 #define PLL_MALDIV_1            0x00000000
 764 #define PLL_MALDIV_2            0x00000010
 765 #define PLL_MALDIV_3            0x00000020
 766 #define PLL_MALDIV_4            0x00000030
 767     /* PCI divisor */
 768 #define PLL_PCIDIV              0x00000003
 769 #define CPC0_PLLMR0_PPFD        0x00000003
 770 #define PLL_PCIDIV_1            0x00000000
 771 #define PLL_PCIDIV_2            0x00000001
 772 #define PLL_PCIDIV_3            0x00000002
 773 #define PLL_PCIDIV_4            0x00000003
 774
 775 #ifdef CONFIG_PPCHAMELEON_CLK_25
 776 /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
 777 #define PPCHAMELEON_PLLMR0_133_133_33_66_33      (PLL_CPUDIV_1 | PLL_PLBDIV_1 |  \
 778                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
 779                               PLL_MALDIV_1 | PLL_PCIDIV_4)
 780 #define PPCHAMELEON_PLLMR1_133_133_33_66_33      (PLL_FBKDIV_8  |  \
 781                               PLL_FWDDIVA_6 | PLL_FWDDIVB_4 |  \
 782                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 783
 784 #define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
 785                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |  \
 786                               PLL_MALDIV_1 | PLL_PCIDIV_4)
 787 #define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8  |  \
 788                               PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
 789                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 790
 791 #define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |      \
 792                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |  \
 793                               PLL_MALDIV_1 | PLL_PCIDIV_4)
 794 #define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8  |  \
 795                               PLL_FWDDIVA_3 | PLL_FWDDIVB_4 |  \
 796                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 797
 798 #define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |      \
 799                               PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |  \
 800                               PLL_MALDIV_1 | PLL_PCIDIV_2)
 801 #define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10      |  \
 802                               PLL_FWDDIVA_3 | PLL_FWDDIVB_4 |  \
 803                               PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
 804
 805 #elif (defined (CONFIG_PPCHAMELEON_CLK_33))
 806
 807 /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
 808 #define PPCHAMELEON_PLLMR0_133_133_33_66_33      (PLL_CPUDIV_1 | PLL_PLBDIV_1 |  \
 809                                   PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |      \
 810                                   PLL_MALDIV_1 | PLL_PCIDIV_4)
 811 #define PPCHAMELEON_PLLMR1_133_133_33_66_33      (PLL_FBKDIV_4  |  \
 812                                   PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |  \
 813                                   PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 814
 815 #define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
 816                                   PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |      \
 817                                   PLL_MALDIV_1 | PLL_PCIDIV_4)
 818 #define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6  |  \
 819                                   PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
 820                                   PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 821
 822 #define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |      \
 823                                   PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |      \
 824                                   PLL_MALDIV_1 | PLL_PCIDIV_4)
 825 #define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8  |  \
 826                                   PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
 827                                   PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
 828
 829 #define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |      \
 830                                   PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |      \
 831                                   PLL_MALDIV_1 | PLL_PCIDIV_2)
 832 #define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10      |  \
 833                                   PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
 834                                   PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
 835
 836 #else
 837 #error "* External frequency (SysClk) not defined! *"
 838 #endif
 839
 840 #if   (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
 841 /* Model HI */
 842 #define PLLMR0_DEFAULT  PPCHAMELEON_PLLMR0_333_111_37_55_55
 843 #define PLLMR1_DEFAULT  PPCHAMELEON_PLLMR1_333_111_37_55_55
 844 #define CFG_OPB_FREQ    55555555
 845 /* Model ME */
 846 #elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
 847 #define PLLMR0_DEFAULT  PPCHAMELEON_PLLMR0_266_133_33_66_33
 848 #define PLLMR1_DEFAULT  PPCHAMELEON_PLLMR1_266_133_33_66_33
 849 #define CFG_OPB_FREQ    66666666
 850 #else
 851 /* Model BA (default) */
 852 #define PLLMR0_DEFAULT  PPCHAMELEON_PLLMR0_133_133_33_66_33
 853 #define PLLMR1_DEFAULT  PPCHAMELEON_PLLMR1_133_133_33_66_33
 854 #define CFG_OPB_FREQ    66666666
 855 #endif
 856
 857 #endif /* CONFIG_NO_SERIAL_EEPROM */
 858
 859 #define CONFIG_JFFS2_NAND 1                     /* jffs2 on nand support */
 860 #define NAND_CACHE_PAGES 16                     /* size of nand cache in 512 bytes pages */
 861
 862 /*
 863  * JFFS2 partitions
 864  */
 865
 866 /* No command line, one static partition */
 867 #undef CONFIG_JFFS2_CMDLINE
 868 #define CONFIG_JFFS2_DEV                "nand0"
 869 #define CONFIG_JFFS2_PART_SIZE          0x00400000
 870 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 871
 872 /* mtdparts command line support */
 873 /*
 874 #define CONFIG_JFFS2_CMDLINE
 875 #define MTDIDS_DEFAULT          "nor0=PPChameleon-0,nand0=ppchameleonevb-nand"
 876 */
 877
 878 /* 256 kB U-boot image */
 879 /*
 880 #define MTDPARTS_DEFAULT        "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
 881                                         "1792k(user),256k(u-boot);" \
 882                                 "ppchameleonevb-nand:-(nand)"
 883 */
 884
 885 /* 320 kB U-boot image */
 886 /*
 887 #define MTDPARTS_DEFAULT        "mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
 888                                         "1728k(user),320k(u-boot);" \
 889                                 "ppchameleonevb-nand:-(nand)"
 890 */
 891
 892 #endif  /* __CONFIG_H */