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* Fix RTC configuration for PPChameleon board
[people/ms/u-boot.git] / include / configs / PPChameleonEVB.h
1 /*
2 * (C) Copyright 2003
3 * DAVE Srl
4 *
5 * http://www.dave-tech.it
6 * http://www.wawnet.biz
7 * mailto:info@wawnet.biz
8 *
9 * Credits: Stefan Roese, Wolfgang Denk
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27 /*
28 * board/config.h - configuration options, board specific
29 */
30
31 #ifndef __CONFIG_H
32 #define __CONFIG_H
33
34 #define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */
35 #define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */
36 #define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */
37 #ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
38 #define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
39 #endif
40
41
42 /* Only one of the following two symbols must be defined (default is 25 MHz)
43 * CONFIG_PPCHAMELEON_CLK_25
44 * CONFIG_PPCHAMELEON_CLK_33
45 */
46 #if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
47 #define CONFIG_PPCHAMELEON_CLK_33
48 #endif
49
50 #if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
51 #error "* Two external frequencies (SysClk) are defined! *"
52 #endif
53
54 #undef CONFIG_PPCHAMELEON_SMI712
55
56 /*
57 * Debug stuff
58 */
59 #undef __DEBUG_START_FROM_SRAM__
60 #define __DISABLE_MACHINE_EXCEPTION__
61
62 #ifdef __DEBUG_START_FROM_SRAM__
63 #define CFG_DUMMY_FLASH_SIZE 1024*1024*4
64 #endif
65
66 /*
67 * High Level Configuration Options
68 * (easy to change)
69 */
70
71 #define CONFIG_405EP 1 /* This is a PPC405 CPU */
72 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
73 #define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */
74
75 #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
76 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
77
78
79 #ifdef CONFIG_PPCHAMELEON_CLK_25
80 # define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
81 #elif (defined (CONFIG_PPCHAMELEON_CLK_33))
82 # define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
83 #else
84 # error "* External frequency (SysClk) not defined! *"
85 #endif
86
87 #define CONFIG_BAUDRATE 115200
88 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
89
90 #undef CONFIG_BOOTARGS
91
92 /* Ethernet stuff */
93 #define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
94 #define CONFIG_ETHADDR 00:50:c2:1e:af:fe
95 #define CONFIG_HAS_ETH1
96 #define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd
97
98 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
99 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
100
101 #undef CONFIG_EXT_PHY
102 #define CONFIG_NET_MULTI 1
103
104 #define CONFIG_MII 1 /* MII PHY management */
105 #ifndef CONFIG_EXT_PHY
106 #define CONFIG_PHY_ADDR 0 /* EMAC0 PHY address */
107 #define CONFIG_PHY1_ADDR 1 /* EMAC1 PHY address */
108 #else
109 #define CONFIG_PHY_ADDR 2 /* PHY address */
110 #endif
111 #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
112
113 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
114 CFG_CMD_DATE | \
115 CFG_CMD_ELF | \
116 CFG_CMD_EEPROM | \
117 CFG_CMD_I2C | \
118 CFG_CMD_IRQ | \
119 CFG_CMD_JFFS2 | \
120 CFG_CMD_MII | \
121 CFG_CMD_NAND | \
122 CFG_CMD_PCI )
123
124 #define CONFIG_MAC_PARTITION
125 #define CONFIG_DOS_PARTITION
126
127 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
128 #include <cmd_confdefs.h>
129
130 #undef CONFIG_WATCHDOG /* watchdog disabled */
131
132 #define CONFIG_RTC_M41T11 1 /* uses a M41T00 RTC */
133 #define CFG_I2C_RTC_ADDR 0x68
134 #define CFG_M41T11_BASE_YEAR 1900
135
136 #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
137
138 /*
139 * Miscellaneous configurable options
140 */
141 #define CFG_LONGHELP /* undef to save memory */
142 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
143
144 #undef CFG_HUSH_PARSER /* use "hush" command parser */
145 #ifdef CFG_HUSH_PARSER
146 #define CFG_PROMPT_HUSH_PS2 "> "
147 #endif
148
149 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
150 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
151 #else
152 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
153 #endif
154 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
155 #define CFG_MAXARGS 16 /* max number of command args */
156 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
157
158 #define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
159
160 #define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
161
162 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
163 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
164
165 #undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
166 #define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
167 #define CFG_BASE_BAUD 691200
168
169 /* The following table includes the supported baudrates */
170 #define CFG_BAUDRATE_TABLE \
171 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
172 57600, 115200, 230400, 460800, 921600 }
173
174 #define CFG_LOAD_ADDR 0x100000 /* default load address */
175 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
176
177 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
178
179 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
180
181 /*-----------------------------------------------------------------------
182 * NAND-FLASH stuff
183 *-----------------------------------------------------------------------
184 */
185 #define CFG_NAND0_BASE 0xFF400000
186 #define CFG_NAND1_BASE 0xFF000000
187
188 #define CFG_MAX_NAND_DEVICE 2 /* Max number of NAND devices */
189 #define SECTORSIZE 512
190 #define NAND_NO_RB
191
192 #define ADDR_COLUMN 1
193 #define ADDR_PAGE 2
194 #define ADDR_COLUMN_PAGE 3
195
196 #define NAND_ChipID_UNKNOWN 0x00
197 #define NAND_MAX_FLOORS 1
198 #define NAND_MAX_CHIPS 1
199
200 #define CFG_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
201 #define CFG_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
202 #define CFG_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
203 #define CFG_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
204
205 #define CFG_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */
206 #define CFG_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */
207 #define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
208 #define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
209
210 #define NAND_DISABLE_CE(nand) do \
211 { \
212 switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
213 { \
214 case CFG_NAND0_BASE: \
215 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
216 break; \
217 case CFG_NAND1_BASE: \
218 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
219 break; \
220 } \
221 } while(0)
222
223 #define NAND_ENABLE_CE(nand) do \
224 { \
225 switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
226 { \
227 case CFG_NAND0_BASE: \
228 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
229 break; \
230 case CFG_NAND1_BASE: \
231 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
232 break; \
233 } \
234 } while(0)
235
236 #define NAND_CTL_CLRALE(nandptr) do \
237 { \
238 switch((unsigned long)nandptr) \
239 { \
240 case CFG_NAND0_BASE: \
241 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
242 break; \
243 case CFG_NAND1_BASE: \
244 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
245 break; \
246 } \
247 } while(0)
248
249 #define NAND_CTL_SETALE(nandptr) do \
250 { \
251 switch((unsigned long)nandptr) \
252 { \
253 case CFG_NAND0_BASE: \
254 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
255 break; \
256 case CFG_NAND1_BASE: \
257 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
258 break; \
259 } \
260 } while(0)
261
262 #define NAND_CTL_CLRCLE(nandptr) do \
263 { \
264 switch((unsigned long)nandptr) \
265 { \
266 case CFG_NAND0_BASE: \
267 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
268 break; \
269 case CFG_NAND1_BASE: \
270 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
271 break; \
272 } \
273 } while(0)
274
275 #define NAND_CTL_SETCLE(nandptr) do { \
276 switch((unsigned long)nandptr) { \
277 case CFG_NAND0_BASE: \
278 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
279 break; \
280 case CFG_NAND1_BASE: \
281 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
282 break; \
283 } \
284 } while(0)
285
286 #ifdef NAND_NO_RB
287 /* constant delay (see also tR in the datasheet) */
288 #define NAND_WAIT_READY(nand) do { \
289 udelay(12); \
290 } while (0)
291 #else
292 /* use the R/B pin */
293 /* TBD */
294 #endif
295
296 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
297 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
298 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
299 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
300
301 /*-----------------------------------------------------------------------
302 * PCI stuff
303 *-----------------------------------------------------------------------
304 */
305 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
306 #define PCI_HOST_FORCE 1 /* configure as pci host */
307 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
308
309 #define CONFIG_PCI /* include pci support */
310 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
311 #undef CONFIG_PCI_PNP /* do pci plug-and-play */
312 /* resource configuration */
313
314 #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
315
316 #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
317 #define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */
318 #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
319
320 #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
321 #define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
322 #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
323 #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
324 #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
325 #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
326
327 /*-----------------------------------------------------------------------
328 * Start addresses for the final memory configuration
329 * (Set up by the startup code)
330 * Please note that CFG_SDRAM_BASE _must_ start at 0
331 */
332 #define CFG_SDRAM_BASE 0x00000000
333 #define CFG_FLASH_BASE 0xFFFC0000
334 #define CFG_MONITOR_BASE CFG_FLASH_BASE
335 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
336 #define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
337
338 /*
339 * For booting Linux, the board info and command line data
340 * have to be in the first 8 MB of memory, since this is
341 * the maximum mapped by the Linux kernel during initialization.
342 */
343 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
344 /*-----------------------------------------------------------------------
345 * FLASH organization
346 */
347 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
348 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
349
350 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
351 #define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
352
353 #define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
354 #define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
355 #define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
356 /*
357 * The following defines are added for buggy IOP480 byte interface.
358 * All other boards should use the standard values (CPCI405 etc.)
359 */
360 #define CFG_FLASH_READ0 0x0000 /* 0 is standard */
361 #define CFG_FLASH_READ1 0x0001 /* 1 is standard */
362 #define CFG_FLASH_READ2 0x0002 /* 2 is standard */
363
364 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
365
366 #if 0 /* test-only */
367 #define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
368 #define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
369 #endif
370
371 /*-----------------------------------------------------------------------
372 * Environment Variable setup
373 */
374 #ifdef ENVIRONMENT_IN_EEPROM
375
376 #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
377 #define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
378 #define CFG_ENV_SIZE 0x700 /* 2048-256 bytes may be used for env vars (total size of a CAT24WC16 is 2048 bytes)*/
379
380 #else /* DEFAULT: environment in flash, using redundand flash sectors */
381
382 #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
383 #define CFG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */
384 #define CFG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/
385 #define CFG_ENV_ADDR_REDUND 0xFFFFA000
386 #define CFG_ENV_SIZE_REDUND 0x2000
387
388 #endif /* ENVIRONMENT_IN_EEPROM */
389
390
391 #define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
392 #define CFG_NVRAM_SIZE 242 /* NVRAM size */
393
394 /*-----------------------------------------------------------------------
395 * I2C EEPROM (CAT24WC16) for environment
396 */
397 #define CONFIG_HARD_I2C /* I2c with hardware support */
398 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
399 #define CFG_I2C_SLAVE 0x7F
400
401 #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
402 #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
403 /* mask of address bits that overflow into the "EEPROM chip address" */
404 /*#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07*/
405 #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
406 /* 16 byte page write mode using*/
407 /* last 4 bits of the address */
408 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
409 #define CFG_EEPROM_PAGE_WRITE_ENABLE
410
411 /*-----------------------------------------------------------------------
412 * Cache Configuration
413 */
414 #define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
415 /* have only 8kB, 16kB is save here */
416 #define CFG_CACHELINE_SIZE 32 /* ... */
417 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
418 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
419 #endif
420
421 /*
422 * Init Memory Controller:
423 *
424 * BR0/1 and OR0/1 (FLASH)
425 */
426
427 #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
428
429 /*-----------------------------------------------------------------------
430 * External Bus Controller (EBC) Setup
431 */
432
433 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
434 #define CFG_EBC_PB0AP 0x92015480
435 #define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
436
437 /* Memory Bank 1 (External SRAM) initialization */
438 /* Since this must replace NOR Flash, we use the same settings for CS0 */
439 #define CFG_EBC_PB1AP 0x92015480
440 #define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
441
442 /* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */
443 #define CFG_EBC_PB2AP 0x92015480
444 #define CFG_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */
445
446 /* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */
447 #define CFG_EBC_PB3AP 0x92015480
448 #define CFG_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */
449
450 #ifdef CONFIG_PPCHAMELEON_SMI712
451 /*
452 * Video console (graphic: SMI LynxEM)
453 */
454 #define CONFIG_VIDEO
455 #define CONFIG_CFB_CONSOLE
456 #define CONFIG_VIDEO_SMI_LYNXEM
457 #define CONFIG_VIDEO_LOGO
458 /*#define CONFIG_VIDEO_BMP_LOGO*/
459 #define CONFIG_CONSOLE_EXTRA_INFO
460 #define CONFIG_VGA_AS_SINGLE_DEVICE
461 /* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
462 #define CFG_ISA_IO 0xE8000000
463 /* see also drivers/videomodes.c */
464 #define CFG_DEFAULT_VIDEO_MODE 0x303
465 #endif
466
467 /*-----------------------------------------------------------------------
468 * FPGA stuff
469 */
470 /* FPGA internal regs */
471 #define CFG_FPGA_MODE 0x00
472 #define CFG_FPGA_STATUS 0x02
473 #define CFG_FPGA_TS 0x04
474 #define CFG_FPGA_TS_LOW 0x06
475 #define CFG_FPGA_TS_CAP0 0x10
476 #define CFG_FPGA_TS_CAP0_LOW 0x12
477 #define CFG_FPGA_TS_CAP1 0x14
478 #define CFG_FPGA_TS_CAP1_LOW 0x16
479 #define CFG_FPGA_TS_CAP2 0x18
480 #define CFG_FPGA_TS_CAP2_LOW 0x1a
481 #define CFG_FPGA_TS_CAP3 0x1c
482 #define CFG_FPGA_TS_CAP3_LOW 0x1e
483
484 /* FPGA Mode Reg */
485 #define CFG_FPGA_MODE_CF_RESET 0x0001
486 #define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
487 #define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000
488 #define CFG_FPGA_MODE_TS_CLEAR 0x2000
489
490 /* FPGA Status Reg */
491 #define CFG_FPGA_STATUS_DIP0 0x0001
492 #define CFG_FPGA_STATUS_DIP1 0x0002
493 #define CFG_FPGA_STATUS_DIP2 0x0004
494 #define CFG_FPGA_STATUS_FLASH 0x0008
495 #define CFG_FPGA_STATUS_TS_IRQ 0x1000
496
497 #define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
498 #define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
499
500 /* FPGA program pin configuration */
501 #define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
502 #define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
503 #define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
504 #define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
505 #define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
506
507 /*-----------------------------------------------------------------------
508 * Definitions for initial stack pointer and data area (in data cache)
509 */
510 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
511 #define CFG_TEMP_STACK_OCM 1
512
513 /* On Chip Memory location */
514 #define CFG_OCM_DATA_ADDR 0xF8000000
515 #define CFG_OCM_DATA_SIZE 0x1000
516 #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
517 #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
518
519 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
520 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
521 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
522
523 /*-----------------------------------------------------------------------
524 * Definitions for GPIO setup (PPC405EP specific)
525 *
526 * GPIO0[0] - External Bus Controller BLAST output
527 * GPIO0[1-9] - Instruction trace outputs -> GPIO
528 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
529 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
530 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
531 * GPIO0[24-27] - UART0 control signal inputs/outputs
532 * GPIO0[28-29] - UART1 data signal input/output
533 * GPIO0[30] - EMAC0 input
534 * GPIO0[31] - EMAC1 reject packet as output
535 */
536 #define CFG_GPIO0_OSRH 0x40000550
537 #define CFG_GPIO0_OSRL 0x00000110
538 #define CFG_GPIO0_ISR1H 0x00000000
539 /*#define CFG_GPIO0_ISR1L 0x15555445*/
540 #define CFG_GPIO0_ISR1L 0x15555444
541 #define CFG_GPIO0_TSRH 0x00000000
542 #define CFG_GPIO0_TSRL 0x00000000
543 #define CFG_GPIO0_TCR 0xF7FF8014
544
545 /*
546 * Internal Definitions
547 *
548 * Boot Flags
549 */
550 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
551 #define BOOTFLAG_WARM 0x02 /* Software reboot */
552
553
554 #define CONFIG_NO_SERIAL_EEPROM
555
556 /*--------------------------------------------------------------------*/
557
558 #ifdef CONFIG_NO_SERIAL_EEPROM
559
560 /*
561 !-----------------------------------------------------------------------
562 ! Defines for entry options.
563 ! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
564 ! are plugged in the board will be utilized as non-ECC DIMMs.
565 !-----------------------------------------------------------------------
566 */
567 #undef AUTO_MEMORY_CONFIG
568 #define DIMM_READ_ADDR 0xAB
569 #define DIMM_WRITE_ADDR 0xAA
570
571 #define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
572 #define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
573 #define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
574 #define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */
575 #define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
576 #define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
577 #define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
578 #define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
579 #define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
580 #define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
581
582 /* Defines for CPC0_PLLMR1 Register fields */
583 #define PLL_ACTIVE 0x80000000
584 #define CPC0_PLLMR1_SSCS 0x80000000
585 #define PLL_RESET 0x40000000
586 #define CPC0_PLLMR1_PLLR 0x40000000
587 /* Feedback multiplier */
588 #define PLL_FBKDIV 0x00F00000
589 #define CPC0_PLLMR1_FBDV 0x00F00000
590 #define PLL_FBKDIV_16 0x00000000
591 #define PLL_FBKDIV_1 0x00100000
592 #define PLL_FBKDIV_2 0x00200000
593 #define PLL_FBKDIV_3 0x00300000
594 #define PLL_FBKDIV_4 0x00400000
595 #define PLL_FBKDIV_5 0x00500000
596 #define PLL_FBKDIV_6 0x00600000
597 #define PLL_FBKDIV_7 0x00700000
598 #define PLL_FBKDIV_8 0x00800000
599 #define PLL_FBKDIV_9 0x00900000
600 #define PLL_FBKDIV_10 0x00A00000
601 #define PLL_FBKDIV_11 0x00B00000
602 #define PLL_FBKDIV_12 0x00C00000
603 #define PLL_FBKDIV_13 0x00D00000
604 #define PLL_FBKDIV_14 0x00E00000
605 #define PLL_FBKDIV_15 0x00F00000
606 /* Forward A divisor */
607 #define PLL_FWDDIVA 0x00070000
608 #define CPC0_PLLMR1_FWDVA 0x00070000
609 #define PLL_FWDDIVA_8 0x00000000
610 #define PLL_FWDDIVA_7 0x00010000
611 #define PLL_FWDDIVA_6 0x00020000
612 #define PLL_FWDDIVA_5 0x00030000
613 #define PLL_FWDDIVA_4 0x00040000
614 #define PLL_FWDDIVA_3 0x00050000
615 #define PLL_FWDDIVA_2 0x00060000
616 #define PLL_FWDDIVA_1 0x00070000
617 /* Forward B divisor */
618 #define PLL_FWDDIVB 0x00007000
619 #define CPC0_PLLMR1_FWDVB 0x00007000
620 #define PLL_FWDDIVB_8 0x00000000
621 #define PLL_FWDDIVB_7 0x00001000
622 #define PLL_FWDDIVB_6 0x00002000
623 #define PLL_FWDDIVB_5 0x00003000
624 #define PLL_FWDDIVB_4 0x00004000
625 #define PLL_FWDDIVB_3 0x00005000
626 #define PLL_FWDDIVB_2 0x00006000
627 #define PLL_FWDDIVB_1 0x00007000
628 /* PLL tune bits */
629 #define PLL_TUNE_MASK 0x000003FF
630 #define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
631 #define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
632 #define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
633 #define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
634 #define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
635 #define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
636 #define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
637
638 /* Defines for CPC0_PLLMR0 Register fields */
639 /* CPU divisor */
640 #define PLL_CPUDIV 0x00300000
641 #define CPC0_PLLMR0_CCDV 0x00300000
642 #define PLL_CPUDIV_1 0x00000000
643 #define PLL_CPUDIV_2 0x00100000
644 #define PLL_CPUDIV_3 0x00200000
645 #define PLL_CPUDIV_4 0x00300000
646 /* PLB divisor */
647 #define PLL_PLBDIV 0x00030000
648 #define CPC0_PLLMR0_CBDV 0x00030000
649 #define PLL_PLBDIV_1 0x00000000
650 #define PLL_PLBDIV_2 0x00010000
651 #define PLL_PLBDIV_3 0x00020000
652 #define PLL_PLBDIV_4 0x00030000
653 /* OPB divisor */
654 #define PLL_OPBDIV 0x00003000
655 #define CPC0_PLLMR0_OPDV 0x00003000
656 #define PLL_OPBDIV_1 0x00000000
657 #define PLL_OPBDIV_2 0x00001000
658 #define PLL_OPBDIV_3 0x00002000
659 #define PLL_OPBDIV_4 0x00003000
660 /* EBC divisor */
661 #define PLL_EXTBUSDIV 0x00000300
662 #define CPC0_PLLMR0_EPDV 0x00000300
663 #define PLL_EXTBUSDIV_2 0x00000000
664 #define PLL_EXTBUSDIV_3 0x00000100
665 #define PLL_EXTBUSDIV_4 0x00000200
666 #define PLL_EXTBUSDIV_5 0x00000300
667 /* MAL divisor */
668 #define PLL_MALDIV 0x00000030
669 #define CPC0_PLLMR0_MPDV 0x00000030
670 #define PLL_MALDIV_1 0x00000000
671 #define PLL_MALDIV_2 0x00000010
672 #define PLL_MALDIV_3 0x00000020
673 #define PLL_MALDIV_4 0x00000030
674 /* PCI divisor */
675 #define PLL_PCIDIV 0x00000003
676 #define CPC0_PLLMR0_PPFD 0x00000003
677 #define PLL_PCIDIV_1 0x00000000
678 #define PLL_PCIDIV_2 0x00000001
679 #define PLL_PCIDIV_3 0x00000002
680 #define PLL_PCIDIV_4 0x00000003
681
682 #ifdef CONFIG_PPCHAMELEON_CLK_25
683 /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
684 #define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
685 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
686 PLL_MALDIV_1 | PLL_PCIDIV_4)
687 #define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \
688 PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \
689 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
690
691 #define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
692 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
693 PLL_MALDIV_1 | PLL_PCIDIV_4)
694 #define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \
695 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
696 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
697
698 #define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
699 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
700 PLL_MALDIV_1 | PLL_PCIDIV_4)
701 #define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
702 PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
703 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
704
705 #define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
706 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
707 PLL_MALDIV_1 | PLL_PCIDIV_2)
708 #define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
709 PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
710 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
711
712 #elif (defined (CONFIG_PPCHAMELEON_CLK_33))
713
714 /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
715 #define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
716 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
717 PLL_MALDIV_1 | PLL_PCIDIV_4)
718 #define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \
719 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
720 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
721
722 #define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
723 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
724 PLL_MALDIV_1 | PLL_PCIDIV_4)
725 #define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
726 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
727 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
728
729 #define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
730 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
731 PLL_MALDIV_1 | PLL_PCIDIV_4)
732 #define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
733 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
734 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
735
736 #define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
737 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
738 PLL_MALDIV_1 | PLL_PCIDIV_2)
739 #define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
740 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
741 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
742
743 #else
744 #error "* External frequency (SysClk) not defined! *"
745 #endif
746
747 #if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
748 /* Model HI */
749 #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55
750 #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55
751 #define CFG_OPB_FREQ 55555555
752 /* Model ME */
753 #elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
754 #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33
755 #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33
756 #define CFG_OPB_FREQ 66666666
757 #else
758 /* Model BA (default) */
759 #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33
760 #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33
761 #define CFG_OPB_FREQ 66666666
762 #endif
763
764 #endif /* CONFIG_NO_SERIAL_EEPROM */
765
766 #define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
767 #define CONFIG_JFFS2_NAND_DEV 0 /* nand device jffs2 lives on */
768 #define CONFIG_JFFS2_NAND_OFF 0 /* start of jffs2 partition */
769 #define CONFIG_JFFS2_NAND_SIZE 2*1024*1024 /* size of jffs2 partition */
770 #define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
771
772 #endif /* __CONFIG_H */
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