include/configs/QS850.h

   1 /*
   2  * (C) Copyright 2003
   3  * MuLogic B.V.
   4  *
   5  * (C) Copyright 2002
   6  * Simple Network Magic Corporation
   7  *
   8  * (C) Copyright 2000
   9  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 /*
  31  * board/config.h - configuration options, board specific
  32  */
  33
  34 #ifndef __CONFIG_H
  35 #define __CONFIG_H
  36
  37 /* various debug settings */
  38 #undef CFG_DEVICE_NULLDEV               /* null device */
  39 #undef CONFIG_SILENT_CONSOLE            /* silent console */
  40 #undef CFG_CONSOLE_INFO_QUIET           /* silent console ? */
  41 #undef DEBUG                            /* debug output code */
  42 #undef DEBUG_FLASH                      /* debug flash code */
  43 #undef FLASH_DEBUG                      /* debug fash code */
  44 #undef DEBUG_ENV                        /* debug environment code */
  45
  46 #define CFG_DIRECT_FLASH_TFTP   1       /* allow direct tftp to flash */
  47 #define CONFIG_ENV_OVERWRITE    1       /* allow overwrite MAC address */
  48
  49 /*
  50  * High Level Configuration Options
  51  * (easy to change)
  52  */
  53 #define CONFIG_MPC850           1       /* This is a MPC850 CPU */
  54 #define CONFIG_QS850            1       /* ...on a QS850 module */
  55 #define CONFIG_SCC2_ENET        1       /* SCC2 10BaseT ethernet */
  56
  57 /* Select the target clock speed */
  58 #undef CONFIG_CLOCK_16MHZ               /* cpu=16,777,216 Hz, mem=16Mhz */
  59 #undef CONFIG_CLOCK_33MHZ               /* cpu=33,554,432 Hz, mem=33Mhz */
  60 #undef CONFIG_CLOCK_50MHZ               /* cpu=49,971,200 Hz, mem=33Mhz */
  61 #define CONFIG_CLOCK_66MHZ      1       /* cpu=67,108,864 Hz, mem=66Mhz */
  62 #undef CONFIG_CLOCK_80MHZ               /* cpu=79,986,688 Hz, mem=33Mhz */
  63
  64 #ifdef CONFIG_CLOCK_16MHZ
  65 #define CONFIG_CLOCK_MULT       512
  66 #endif
  67
  68 #ifdef CONFIG_CLOCK_33MHZ
  69 #define CONFIG_CLOCK_MULT       1024
  70 #endif
  71
  72 #ifdef CONFIG_CLOCK_50MHZ
  73 #define CONFIG_CLOCK_MULT       1525
  74 #endif
  75
  76 #ifdef CONFIG_CLOCK_66MHZ
  77 #define CONFIG_CLOCK_MULT       2048
  78 #endif
  79
  80 #ifdef CONFIG_CLOCK_80MHZ
  81 #define CONFIG_CLOCK_MULT       2441
  82 #endif
  83
  84 /* choose flash size, 4Mb or 8Mb */
  85 #define CONFIG_FLASH_4MB        1       /* board has 4Mb flash */
  86 #undef CONFIG_FLASH_8MB                 /* board has 8Mb flash */
  87
  88 #define CONFIG_CLOCK_BASE       32768   /* Base clock input freq */
  89
  90 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1 */
  91 #undef CONFIG_8xx_CONS_SMC2
  92 #undef CONFIG_8xx_CONS_NONE
  93
  94 #define CONFIG_BAUDRATE         38400   /* console baudrate = 38.4kbps */
  95
  96 #undef CONFIG_CLOCKS_IN_MHZ             /* clocks passsed to Linux in MHz */
  97
  98 /* Define default IP addresses */
  99 #define CONFIG_IPADDR           192.168.1.99    /* own ip address */
 100 #define CONFIG_SERVERIP         192.168.1.19    /* used for tftp (not nfs?) */
 101
 102 /* message to say directly after booting */
 103 #define CONFIG_PREBOOT          "echo '';" \
 104         "echo 'type:';" \
 105         "echo 'run boot_nfs       to boot to NFS';" \
 106         "echo 'run boot_flash     to boot to flash';" \
 107         "echo '';" \
 108         "echo 'run flash_rootfs   to install a new rootfs';" \
 109         "echo 'run flash_env      to clear the env sector';" \
 110         "echo 'run flash_rw       to clear the rw fs';" \
 111         "echo 'run flash_uboot    to install a new u-boot';" \
 112         "echo 'run flash_kernel   to install a new kernel';"
 113
 114 /* wait 5 seconds before executing CONFIG_BOOTCOMMAND */
 115 #define CONFIG_BOOTDELAY        5
 116 #define CONFIG_BOOTCOMMAND      "run boot_nfs"
 117
 118 #undef CONFIG_BOOTARGS          /* made by set_nfs of set_flash */
 119
 120 /* Our flash filesystem looks like this
 121  *
 122  * 4Mb board:
 123  * ffc0 0000 - ffeb ffff        root filesystem (jffs2) (~3Mb)
 124  * ffec 0000 - ffed ffff        read-write filesystem (ext2)
 125  * ffee 0000 - ffef ffff        environment
 126  * fff0 0000 - fff1 ffff        u-boot
 127  * fff2 0000 - ffff ffff        linux kernel
 128  *
 129  * 8Mb board:
 130  * ff80 0000 - ffeb ffff        root filesystem (jffs2) (~7Mb)
 131  * ffec 0000 - ffed ffff        read-write filesystem (ext2)
 132  * ffee 0000 - ffef ffff        environment
 133  * fff0 0000 - fff1 ffff        u-boot
 134  * fff2 0000 - ffff ffff        linux kernel
 135  *
 136  */
 137
 138 /* environment for 4Mb board */
 139 #ifdef CONFIG_FLASH_4MB
 140 #define CONFIG_EXTRA_ENV_SETTINGS \
 141         "serial#=QS850\0" \
 142         "hostname=qs850\0" \
 143         "netdev=eth0\0" \
 144         "ethaddr=00:01:02:B4:36:56\0" \
 145         "rootpath=/exports/rootfs\0" \
 146         "mtdparts=mtdparts=phys:2816k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
 147         /* fill in variables */ \
 148         "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
 149         "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
 150         "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
 151         /* commands */ \
 152         "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
 153         "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
 154         /* reinstall flash parts */ \
 155         "flash_rootfs=protect off ffc00000 ffebffff; era ffc00000 ffebffff; tftp ffc00000 /tftpboot/rootfs.jffs2\0" \
 156         "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
 157         "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
 158         "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.4mb.bin\0" \
 159         "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0"
 160 #endif /* CONFIG_FLASH_4MB */
 161
 162 /* environment for 8Mb board */
 163 #ifdef CONFIG_FLASH_8MB
 164 #define CONFIG_EXTRA_ENV_SETTINGS \
 165         "serial#=QS850\0" \
 166         "hostname=qs850\0" \
 167         "netdev=eth0\0" \
 168         "ethaddr=00:01:02:B4:36:56\0" \
 169         "rootpath=/exports/rootfs\0" \
 170         "mtdparts=mtdparts=phys:6912k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
 171         /* fill in variables */ \
 172         "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
 173         "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
 174         "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
 175         /* commands */ \
 176         "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
 177         "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
 178         /* reinstall flash parts */ \
 179         "flash_rootfs=protect off ff800000 ffebffff; era ff800000 ffebffff; tftp ff800000 /tftpboot/rootfs.jffs2\0" \
 180         "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
 181         "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
 182         "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.8mb.bin\0" \
 183         "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0"
 184 #endif /* CONFIG_FLASH_8MB */
 185
 186 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 187 #undef CFG_LOADS_BAUD_CHANGE            /* don't allow baudrate change */
 188 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 189 #undef CONFIG_STATUS_LED                /* Status LED disabled */
 190 #undef CONFIG_CAN_DRIVER                /* CAN Driver support disabled */
 191
 192 /*
 193  * BOOTP options
 194  */
 195 #define CONFIG_BOOTP_SUBNETMASK
 196 #define CONFIG_BOOTP_GATEWAY
 197 #define CONFIG_BOOTP_HOSTNAME
 198 #define CONFIG_BOOTP_BOOTPATH
 199 #define CONFIG_BOOTP_BOOTFILESIZE
 200
 201 #undef CONFIG_MAC_PARTITION
 202 #undef CONFIG_DOS_PARTITION
 203
 204 #define CONFIG_RTC_MPC8xx       /* use internal RTC of MPC8xx */
 205
 206
 207 /*
 208  * Command line configuration.
 209  */
 210
 211 #define CONFIG_CMD_BDI
 212 #define CONFIG_CMD_BOOTD
 213 #define CONFIG_CMD_CONSOLE
 214 #define CONFIG_CMD_DATE
 215 #define CONFIG_CMD_ENV
 216 #define CONFIG_CMD_FLASH
 217 #define CONFIG_CMD_IMI
 218 #define CONFIG_CMD_IMMAP
 219 #define CONFIG_CMD_MEMORY
 220 #define CONFIG_CMD_NET
 221 #define CONFIG_CMD_RUN
 222
 223
 224 /*-----------------------------------------------------------------------
 225  * Environment variable storage is in FLASH, one sector before U-boot
 226  */
 227 #define CFG_ENV_IS_IN_FLASH     1
 228 #define CFG_ENV_SECT_SIZE       0x20000         /* 128Kb, one whole sector */
 229 #define CFG_ENV_SIZE            0x2000          /* 8kb */
 230 #define CFG_ENV_ADDR            0xffee0000      /* address of env sector */
 231
 232 /*-----------------------------------------------------------------------
 233  * Miscellaneous configurable options
 234  */
 235 #define CFG_LONGHELP                            /* undef to save memory */
 236 #define CFG_PROMPT              "=> "           /* Monitor Command Prompt */
 237
 238 #define CFG_HUSH_PARSER         1               /* use "hush" command parser */
 239 #define CFG_PROMPT_HUSH_PS2     "> "
 240
 241 #if defined(CONFIG_CMD_KGDB)
 242 #define CFG_CBSIZE              1024            /* Console I/O Buffer Size */
 243 #else
 244 #define CFG_CBSIZE              256             /* Console I/O Buffer Size */
 245 #endif
 246 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 247 #define CFG_MAXARGS             16              /* max number of command args */
 248 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size */
 249
 250 #define CFG_MEMTEST_START       0x0400000       /* memtest works */
 251 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM */
 252
 253 #define CFG_LOAD_ADDR           0x400000        /* default load address */
 254
 255 #define CFG_HZ                  1000            /* decrementer freq: 1 ms ticks */
 256
 257 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 258
 259 /*-----------------------------------------------------------------------
 260  * Low Level Configuration Settings
 261  * (address mappings, register initial values, etc.)
 262  * You should know what you are doing if you make changes here.
 263  */
 264
 265 /*-----------------------------------------------------------------------
 266  * Internal Memory Mapped Register
 267  */
 268 #define CFG_IMMR                0xFF000000
 269
 270 /*-----------------------------------------------------------------------
 271  * Definitions for initial stack pointer and data area (in DPRAM)
 272  */
 273 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 274 #define CFG_INIT_RAM_END        0x2F00          /* End of used area in DPRAM */
 275 #define CFG_GBL_DATA_SIZE       64              /* size in bytes reserved for initial data */
 276 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 277 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 278
 279 /*-----------------------------------------------------------------------
 280  * Start addresses for the final memory configuration
 281  * (Set up by the startup code)
 282  * Please note that CFG_SDRAM_BASE _must_ start at 0
 283  */
 284 #define CFG_SDRAM_BASE          0x00000000
 285 #define CFG_FLASH_BASE          0xFF800000      /* Allow an 8Mbyte window */
 286
 287 #define FLASH_BASE0_4M_PRELIM   0xFFC00000      /* Base for 4M Flash */
 288 #define FLASH_BASE0_8M_PRELIM   0xFF800000      /* Base for 8M Flash */
 289
 290 #define CFG_MONITOR_LEN         (192 << 10)     /* Reserve 192 kB for Monitor */
 291 #define CFG_MONITOR_BASE        0xFFF00000      /* U-boot location */
 292 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc() */
 293
 294 /*
 295  * For booting Linux, the board info and command line data
 296  * have to be in the first 8 MB of memory, since this is
 297  * the maximum mapped by the Linux kernel during initialization.
 298  */
 299 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 300
 301 /*-----------------------------------------------------------------------
 302  * TODO flash parameters
 303  * FLASH organization for Intel Strataflash
 304  */
 305 #undef  CFG_FLASH_16BIT                         /* 32-bit wide flash memory */
 306 #define CFG_MAX_FLASH_BANKS     1               /* max number of memory banks */
 307 #define CFG_MAX_FLASH_SECT      71              /* max number of sectors on one chip */
 308
 309 #define CFG_FLASH_ERASE_TOUT    120000          /* Timeout for Flash Erase (in ms) */
 310 #define CFG_FLASH_WRITE_TOUT    500             /* Timeout for Flash Write (in ms) */
 311
 312 /*-----------------------------------------------------------------------
 313  * Cache Configuration
 314  */
 315 #define CFG_CACHELINE_SIZE      16              /* For all MPC8xx CPUs */
 316 #if defined(CONFIG_CMD_KGDB)
 317 #define CFG_CACHELINE_SHIFT     4               /* log base 2 of the above value */
 318 #endif
 319
 320 /*-----------------------------------------------------------------------
 321  * SYPCR - System Protection Control 11-9
 322  * SYPCR can only be written once after reset!
 323  *-----------------------------------------------------------------------
 324  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 325  */
 326
 327 #ifdef CONFIG_WATCHDOG
 328 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
 329 #else
 330 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP)
 331 #endif
 332
 333 /*-----------------------------------------------------------------------
 334  * SIUMCR - SIU Module Configuration 11-6
 335  *-----------------------------------------------------------------------
 336  */
 337 #define CFG_SIUMCR      (SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E)
 338
 339 /*-----------------------------------------------------------------------
 340  * TBSCR - Time Base Status and Control 11-26
 341  *-----------------------------------------------------------------------
 342  */
 343 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 344
 345 /*-----------------------------------------------------------------------
 346  * RTCSC - Real-Time Clock Status and Control Register 11-27
 347  *-----------------------------------------------------------------------
 348  */
 349 #define CFG_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 350
 351 /*-----------------------------------------------------------------------
 352  * PISCR - Periodic Interrupt Status and Control 11-31
 353  *-----------------------------------------------------------------------
 354  */
 355 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 356
 357 /*-----------------------------------------------------------------------
 358  * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
 359  *-----------------------------------------------------------------------
 360  */
 361
 362 /* MF (Multiplication Factor of SPLL) */
 363 /* Sets the QS850 to specified clock from 32KHz clock at EXTAL. */
 364 #define vPLPRCR_MF      ((CONFIG_CLOCK_MULT+1) << 20)
 365 #define CFG_PLPRCR      (vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE)
 366
 367 /*-----------------------------------------------------------------------
 368  * SCCR - System Clock and reset Control Register               15-27
 369  *-----------------------------------------------------------------------
 370  */
 371 #if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
 372 #define CFG_SCCR                (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00)
 373 #define CFG_BRGCLK_PRESCALE     1
 374 #endif
 375
 376 #if defined(CONFIG_CLOCK_66MHZ)
 377 #define CFG_SCCR                (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01)
 378 #define CFG_BRGCLK_PRESCALE     4
 379 #endif
 380
 381 #if defined(CONFIG_CLOCK_80MHZ)
 382 #define CFG_SCCR                (SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01)
 383 #define CFG_BRGCLK_PRESCALE     4
 384 #endif
 385
 386 #define SCCR_MASK               CFG_SCCR
 387
 388 /*-----------------------------------------------------------------------
 389  * Debug Enable Register
 390  * 0x73E67C0F - All interrupts handled by BDM
 391  * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM
 392  *-----------------------------------------------------------------------
 393 #define CFG_DER                 0x73E67C0F
 394 #define CFG_DER                 0x0082400F
 395
 396  #-------------------------------------------------------------------------
 397  # Program the Debug Enable Register (DER). This register provides the user
 398  # with the reason for entering into the debug mode. We want all conditions
 399  # to end up as an exception. We don't want to enter into debug mode for
 400  # any condition. See the back of of the Development Support section of the
 401  # MPC860 User Manual for a description of this register.
 402  #-------------------------------------------------------------------------
 403 */
 404 #define CFG_DER                 0
 405
 406 /*-----------------------------------------------------------------------
 407  * Memory Controller Initialization Constants
 408  *-----------------------------------------------------------------------
 409  */
 410
 411 /*
 412  * BR0 and OR0 (AMD dual FLASH devices)
 413  * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation)
 414  */
 415 #define CFG_PRELIM_OR_AM
 416 #define CFG_OR_TIMING_FLASH
 417
 418 /*
 419  *-----------------------------------------------------------------------
 420  * Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32)
 421  *                        flash that resides on the QS850.
 422  *-----------------------------------------------------------------------
 423  */
 424
 425 /* BA (Base Address) = 0xFF80+0b for a total of 17 bits. 17 bit base addr */
 426 /*                     represents a minumum 32K block size. */
 427 #define vBR0_BA                 ((0xFF80 << 16) + (0 << 15))
 428 #define CFG_BR0_PRELIM          (vBR0_BA | BR_V)
 429
 430 /* AM (Address Mask) = 0xFF80+0b = We've masked the upper 9 bits        */
 431 /*                                 which defines a 8 Mbyte memory block. */
 432 #define vOR0_AM                 ((0xFF80 << 16) + (0 << 15))
 433
 434 #if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ)
 435 /*  0101 = Add a 5 clock cycle wait state */
 436 #define CFG_OR0_PRELIM          (vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK)
 437 #endif
 438
 439 #if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ)
 440 /*  0011 = Add a 3 clock cycle wait state */
 441 /*  29.8ns clock * (3 + 2) = 149ns cycle time */
 442 #define CFG_OR0_PRELIM          (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK)
 443 #endif
 444
 445 #if defined(CONFIG_CLOCK_16MHZ)
 446 /*  0010 = Add a 2 clock cycle wait state */
 447 #define CFG_OR0_PRELIM          (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK)
 448 #endif
 449
 450 /*
 451  * BR1 and OR1 (SDRAM)
 452  * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation)
 453  * Base Address = 0x00000000 - 0x01FF_FFFF (32M After relocation)
 454  * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation)
 455  * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation)
 456  */
 457
 458 #define SDRAM_BASE              0x00000000      /* SDRAM bank */
 459 #define SDRAM_PRELIM_OR_AM      0xF8000000      /* map max. 128 MB */
 460
 461 /* AM (Address Mask) = 0xF800+0b = We've masked the upper 5 bits which
 462  *                                 represents a 128 Mbyte block the DRAM in
 463  *                                 this address base.
 464  */
 465 #define vOR1_AM                 ((0xF800 << 16) + (0 << 15))
 466 #define vBR1_BA                 ((0x0000 << 16) + (0 << 15))
 467 #define CFG_OR1                 (vOR1_AM | OR_CSNT_SAM | OR_BI)
 468 #define CFG_BR1                 (vBR1_BA | BR_MS_UPMA | BR_V)
 469
 470 /* Machine A Mode Register */
 471
 472 /* PTA Periodic Timer A */
 473
 474 #if defined(CONFIG_CLOCK_80MHZ)
 475 #define vMAMR_PTA               (19 << 24)
 476 #endif
 477
 478 #if defined(CONFIG_CLOCK_66MHZ)
 479 #define vMAMR_PTA               (16 << 24)
 480 #endif
 481
 482 #if defined(CONFIG_CLOCK_50MHZ)
 483 #define vMAMR_PTA               (195 << 24)
 484 #endif
 485
 486 #if defined(CONFIG_CLOCK_33MHZ)
 487 #define vMAMR_PTA               (131 << 24)
 488 #endif
 489
 490 #if defined(CONFIG_CLOCK_16MHZ)
 491 #define vMAMR_PTA               (65 << 24)
 492 #endif
 493
 494 /* For boards with 16M of SDRAM */
 495 #define SDRAM_16M_MAX_SIZE      0x01000000      /* max 16MB SDRAM */
 496 #define CFG_16M_MAMR            (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\
 497 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
 498
 499 /* For boards with 32M of SDRAM */
 500 #define SDRAM_32M_MAX_SIZE      0x02000000      /* max 32MB SDRAM */
 501 #define CFG_32M_MAMR            (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\
 502 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
 503
 504
 505 /* Memory Periodic Timer Prescaler Register */
 506
 507 #if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ)
 508 /* Divide by 32 */
 509 #define CFG_MPTPR               0x02
 510 #endif
 511
 512 #if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
 513 /* Divide by 16 */
 514 #define CFG_MPTPR               0x04
 515 #endif
 516
 517 /*
 518  * BR2 and OR2 (Unused)
 519  * Base address = 0xF020_0000 - 0xF020_0FFF
 520  *
 521  */
 522 #define CFG_OR2_PRELIM          0xFFF00000
 523 #define CFG_BR2_PRELIM          0xF0200000
 524
 525 /*
 526  * BR3 and OR3 (External Bus CS3)
 527  * Base address = 0xF030_0000 - 0xF030_0FFF
 528  *
 529  */
 530 #define CFG_OR3_PRELIM          0xFFF00000
 531 #define CFG_BR3_PRELIM          0xF0300000
 532
 533 /*
 534  * BR4 and OR4 (External Bus CS3)
 535  * Base address = 0xF040_0000 - 0xF040_0FFF
 536  *
 537  */
 538 #define CFG_OR4_PRELIM          0xFFF00000
 539 #define CFG_BR4_PRELIM          0xF0400000
 540
 541
 542 /*
 543  * BR4 and OR4 (External Bus CS3)
 544  * Base address = 0xF050_0000 - 0xF050_0FFF
 545  *
 546  */
 547 #define CFG_OR5_PRELIM          0xFFF00000
 548 #define CFG_BR5_PRELIM          0xF0500000
 549
 550 /*
 551  * BR6 and OR6 (Unused)
 552  * Base address = 0xF060_0000 - 0xF060_0FFF
 553  *
 554  */
 555 #define CFG_OR6_PRELIM          0xFFF00000
 556 #define CFG_BR6_PRELIM          0xF0600000
 557
 558 /*
 559  * BR7 and OR7 (Unused)
 560  * Base address = 0xF070_0000 - 0xF070_0FFF
 561  *
 562  */
 563 #define CFG_OR7_PRELIM          0xFFF00000
 564 #define CFG_BR7_PRELIM          0xF0700000
 565
 566 /*
 567  * Internal Definitions
 568  *
 569  * Boot Flags
 570  */
 571 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
 572 #define BOOTFLAG_WARM           0x02    /* Software reboot */
 573
 574 /*
 575  * Sanity checks
 576  */
 577 #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
 578 #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
 579 #endif
 580
 581 #endif /* __CONFIG_H */