include/configs/QS860T.h

   1 /*
   2  * (C) Copyright 2003
   3  * MuLogic B.V.
   4  *
   5  * (C) Copyright 2002
   6  * Simple Network Magic Corporation
   7  *
   8  * (C) Copyright 2000
   9  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 /*
  31  * board/config.h - configuration options, board specific
  32  */
  33
  34 #ifndef __CONFIG_H
  35 #define __CONFIG_H
  36
  37 /* various debug settings */
  38 #undef CFG_DEVICE_NULLDEV               /* null device */
  39 #undef CONFIG_SILENT_CONSOLE            /* silent console */
  40 #undef CFG_CONSOLE_INFO_QUIET           /* silent console ? */
  41 #undef DEBUG                            /* debug output code */
  42 #undef DEBUG_FLASH                      /* debug flash code */
  43 #undef FLASH_DEBUG                      /* debug fash code */
  44 #undef DEBUG_ENV                        /* debug environment code */
  45
  46 #define CFG_DIRECT_FLASH_TFTP   1       /* allow direct tftp to flash */
  47 #define CONFIG_ENV_OVERWRITE    1       /* allow overwrite MAC address */
  48
  49
  50 /*
  51  * High Level Configuration Options
  52  * (easy to change)
  53  */
  54
  55 #define CONFIG_MPC860           1       /* This is a MPC860 CPU */
  56 #define CONFIG_QS860T           1       /* ...on a QS860T module */
  57
  58 #define CONFIG_FEC_ENET         1       /* FEC 10/100BaseT ethernet */
  59 #define CONFIG_MII
  60 #define FEC_INTERRUPT           SIU_LEVEL1
  61 #undef CONFIG_SCC1_ENET                 /* SCC1 10BaseT ethernet */
  62 #define CFG_DISCOVER_PHY
  63
  64 #undef CONFIG_8xx_CONS_SMC1
  65 #define CONFIG_8xx_CONS_SMC2    1       /* Console is on SMC */
  66 #undef CONFIG_8xx_CONS_NONE
  67
  68 #define CONFIG_BAUDRATE         38400   /* console baudrate = 38.4kbps */
  69
  70 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
  71
  72 /* Pass clocks to Linux 2.4.18 in Hz */
  73 #undef CONFIG_CLOCKS_IN_MHZ             /* clocks passsed to Linux in MHz */
  74
  75 #define CONFIG_PREBOOT          "echo;" \
  76         "echo 'Type \"run flash_nfs\" to mount root filesystem over NFS';" \
  77         "echo"
  78
  79 #undef CONFIG_BOOTARGS
  80 /* TODO compare against CADM860 */
  81 #define CONFIG_BOOTCOMMAND      "bootp; " \
  82         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
  83         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
  84         "bootm"
  85
  86 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
  87 #undef CFG_LOADS_BAUD_CHANGE            /* don't allow baudrate change */
  88
  89 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
  90
  91 #undef CONFIG_STATUS_LED                /* Status LED disabled */
  92
  93 #undef CONFIG_CAN_DRIVER                /* CAN Driver support disabled */
  94
  95 /*
  96  * BOOTP options
  97  */
  98 #define CONFIG_BOOTP_SUBNETMASK
  99 #define CONFIG_BOOTP_GATEWAY
 100 #define CONFIG_BOOTP_HOSTNAME
 101 #define CONFIG_BOOTP_BOOTPATH
 102 #define CONFIG_BOOTP_BOOTFILESIZE
 103
 104
 105 #define CONFIG_MAC_PARTITION
 106 #define CONFIG_DOS_PARTITION
 107
 108 #define CONFIG_RTC_MPC8xx       /* use internal RTC of MPC8xx */
 109
 110
 111 /*
 112  * Command line configuration.
 113  */
 114 #include <config_cmd_default.h>
 115
 116 #define CONFIG_CMD_REGINFO
 117 #define CONFIG_CMD_IMMAP
 118 #define CONFIG_CMD_ASKENV
 119 #define CONFIG_CMD_NET
 120 #define CONFIG_CMD_DHCP
 121 #define CONFIG_CMD_DATE
 122
 123
 124 /* TODO */
 125 #if 0
 126 /* Look at these */
 127 CONFIG_IPADDR
 128 CONFIG_SERVERIP
 129 CONFIG_I2C
 130 CONFIG_SPI
 131 #endif
 132
 133 /*
 134  * Environment variable storage is in NVRAM
 135  */
 136 #define CFG_ENV_IS_IN_NVRAM     1
 137 #define CFG_ENV_SIZE            0x00001000      /* We use only the last 4K for PPCBoot */
 138 #define CFG_ENV_ADDR            0xD100E000
 139
 140 /*
 141  * Miscellaneous configurable options
 142  */
 143 #define CFG_LONGHELP                            /* undef to save memory */
 144 #define CFG_PROMPT              "=> "           /* Monitor Command Prompt */
 145
 146 #define CFG_HUSH_PARSER         1               /* use "hush" command parser */
 147 #define CFG_PROMPT_HUSH_PS2     "> "
 148
 149 #if defined(CONFIG_CMD_KGDB)
 150 #define CFG_CBSIZE              1024            /* Console I/O Buffer Size */
 151 #else
 152 #define CFG_CBSIZE              256             /* Console I/O Buffer Size */
 153 #endif
 154 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 155 #define CFG_MAXARGS             16              /* max number of command args */
 156 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size */
 157
 158 /* TODO - size? */
 159 #define CFG_MEMTEST_START       0x0400000       /* memtest works */
 160 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM */
 161
 162 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 163
 164 #define CFG_HZ                  1000            /* decrementer freq: 1 ms ticks */
 165
 166 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 167
 168 /*-----------------------------------------------------------------------
 169  * Low Level Configuration Settings
 170  * (address mappings, register initial values, etc.)
 171  * You should know what you are doing if you make changes here.
 172  */
 173 /*-----------------------------------------------------------------------
 174  * Internal Memory Mapped Register
 175  */
 176 #define CFG_IMMR                0xF0000000
 177
 178 /*-----------------------------------------------------------------------
 179  * Definitions for initial stack pointer and data area (in DPRAM)
 180  */
 181 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 182 #define CFG_INIT_RAM_END        0x2F00          /* End of used area in DPRAM */
 183 #define CFG_GBL_DATA_SIZE       64              /* size in bytes reserved for initial data */
 184 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 185 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 186
 187 /*-----------------------------------------------------------------------
 188  * Start addresses for the final memory configuration
 189  * (Set up by the startup code)
 190  * Please note that CFG_SDRAM_BASE _must_ start at 0
 191  */
 192 #define CFG_SDRAM_BASE          0x00000000
 193 #define CFG_FLASH_BASE          0xFFF00000
 194
 195 #define CFG_MONITOR_LEN         (192 << 10)     /* Reserve 192 kB for Monitor */
 196 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 197 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc() */
 198
 199 /*
 200  * For booting Linux, the board info and command line data
 201  * have to be in the first 8 MB of memory, since this is
 202  * the maximum mapped by the Linux kernel during initialization.
 203  */
 204 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 205
 206 /* TODO flash parameters */
 207 /*-----------------------------------------------------------------------
 208  * FLASH organization for Intel Strataflash
 209  */
 210 #define CFG_FLASH_16BIT         1               /* 16-bit wide flash memory */
 211 #define CFG_MAX_FLASH_BANKS     1               /* max number of memory banks */
 212 #define CFG_MAX_FLASH_SECT      64              /* max number of sectors on one chip */
 213
 214 #define CFG_FLASH_ERASE_TOUT    120000          /* Timeout for Flash Erase (in ms) */
 215 #define CFG_FLASH_WRITE_TOUT    500             /* Timeout for Flash Write (in ms) */
 216
 217 #undef  CFG_ENV_IS_IN_FLASH
 218
 219 /*-----------------------------------------------------------------------
 220  * Cache Configuration
 221  */
 222 #define CFG_CACHELINE_SIZE      16              /* For all MPC8xx CPUs */
 223 #if defined(CONFIG_CMD_KGDB)
 224 #define CFG_CACHELINE_SHIFT     4               /* log base 2 of the above value */
 225 #endif
 226
 227 /*-----------------------------------------------------------------------
 228  * SYPCR - System Protection Control 11-9
 229  * SYPCR can only be written once after reset!
 230  *-----------------------------------------------------------------------
 231  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 232  */
 233 #if defined(CONFIG_WATCHDOG)
 234 #define CFG_SYPCR       (0xFFFFFF88 | SYPCR_SWE | SYPCR_SWRI)
 235 #else
 236 #define CFG_SYPCR       0xFFFFFF88
 237 #endif
 238
 239 /*-----------------------------------------------------------------------
 240  * SIUMCR - SIU Module Configuration 11-6
 241  *-----------------------------------------------------------------------
 242  */
 243 #define CFG_SIUMCR      0x00620000
 244
 245 /*-----------------------------------------------------------------------
 246  * TBSCR - Time Base Status and Control 11-26
 247  *-----------------------------------------------------------------------
 248  */
 249 #define CFG_TBSCR       0x00C3
 250
 251 /*-----------------------------------------------------------------------
 252  * RTCSC - Real-Time Clock Status and Control Register 11-27
 253  *-----------------------------------------------------------------------
 254  */
 255 #define CFG_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 256
 257 /*-----------------------------------------------------------------------
 258  * PISCR - Periodic Interrupt Status and Control 11-31
 259  *-----------------------------------------------------------------------
 260  */
 261 #define CFG_PISCR       0x0082
 262
 263 /*-----------------------------------------------------------------------
 264  * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
 265  *-----------------------------------------------------------------------
 266  */
 267 #define CFG_PLPRCR      0x0090D000
 268
 269 /*-----------------------------------------------------------------------
 270  * SCCR - System Clock and reset Control Register               15-27
 271  *-----------------------------------------------------------------------
 272  */
 273 #define SCCR_MASK       SCCR_EBDF11
 274 #define CFG_SCCR        0x02000000
 275
 276
 277 /*-----------------------------------------------------------------------
 278  * Debug Enable Register
 279  * 0x73E67C0F - All interrupts handled by BDM
 280  * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM
 281  *-----------------------------------------------------------------------
 282 #define CFG_DER                 0x73E67C0F
 283 */
 284 #define CFG_DER                 0x0082400F
 285
 286
 287 /*-----------------------------------------------------------------------
 288  * Memory Controller Initialization Constants
 289  *-----------------------------------------------------------------------
 290  */
 291
 292 /*
 293  * BR0 and OR0 (AMD 512K Socketed FLASH)
 294  * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation)
 295  */
 296 #define CFG_PRELIM_OR_AM
 297 #define CFG_OR_TIMING_FLASH
 298
 299 #define FLASH_BASE0_PRELIM      0xFFF00001
 300 #define CFG_OR0_PRELIM          0xFFF80D42
 301 #define CFG_BR0_PRELIM          0xFFF00401
 302
 303
 304 /*
 305  * BR1 and OR1 (Intel 8M StrataFLASH)
 306  * Base address = 0xD000_0000 - 0xD07F_FFFF
 307  */
 308
 309 #define FLASH_BASE1_PRELIM      0xD0000000
 310 #define CFG_OR1_PRELIM          0xFF800D42
 311 #define CFG_BR1_PRELIM          0xD0000801
 312 /* #define CFG_OR1              0xFF800D42 */
 313 /* #define CFG_BR1              0xD0000801 */
 314
 315
 316 /*
 317  * BR2 and OR2 (SDRAM)
 318  * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation)
 319  * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation)
 320  * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation)
 321  *
 322  */
 323 #define SDRAM_BASE              0x00000000      /* SDRAM bank */
 324 #define SDRAM_PRELIM_OR_AM      0xF8000000      /* map max. 128 MB */
 325
 326 /* SDRAM timing */
 327 #define SDRAM_TIMING            0x00000A00
 328
 329 /* For boards with 16M of SDRAM */
 330 #define SDRAM_16M_MAX_SIZE      0x01000000      /* max 16MB SDRAM */
 331 #define CFG_16M_MBMR            0x18802114      /* Mem Periodic Timer Prescaler */
 332
 333 /* For boards with 64M of SDRAM */
 334 #define SDRAM_64M_MAX_SIZE      0x04000000      /* max 64MB SDRAM */
 335 /* TODO - determine real value */
 336 #define CFG_64M_MBMR            0x18802114      /* Mem Period Timer Prescaler */
 337
 338 #define CFG_OR2                 (SDRAM_PRELIM_OR_AM | SDRAM_TIMING)
 339 #define CFG_BR2                 (SDRAM_BASE | 0x000000C1)
 340
 341
 342 /*
 343  * BR3 and OR3 (NVRAM, Sipex, NAND Flash)
 344  * Base address = 0xD100_0000 - 0xD100_FFFF (64K NVRAM)
 345  * Base address = 0xD108_0000 - 0xD108_0000 (Sipex chip ctl register)
 346  * Base address = 0xD110_0000 - 0xD110_0000 (NAND ctl register)
 347  * Base address = 0xD138_0000 - 0xD138_0000 (LED ctl register)
 348  *
 349  */
 350
 351 #define CFG_OR3_PRELIM          0xFFC00DF6
 352 #define CFG_BR3_PRELIM          0xD1000401
 353 /* #define CFG_OR3              0xFFC00DF6 */
 354 /* #define CFG_BR3              0xD1000401 */
 355
 356
 357 /*
 358  * BR4 and OR4 (Unused)
 359  * Base address = 0xE000_0000 - 0xE3FF_FFFF
 360  *
 361  */
 362
 363 #define CFG_OR4_PRELIM          0xFF000000
 364 #define CFG_BR4_PRELIM          0xE0000000
 365 /* #define CFG_OR4              0xFF000000 */
 366 /* #define CFG_BR4              0xE0000000 */
 367
 368
 369 /*
 370  * BR5 and OR5 (Expansion bus)
 371  * Base address = 0xE400_0000 - 0xE7FF_FFFF
 372  *
 373  */
 374
 375 #define CFG_OR5_PRELIM          0xFF000000
 376 #define CFG_BR5_PRELIM          0xE4000000
 377 /* #define CFG_OR5              0xFF000000 */
 378 /* #define CFG_BR5              0xE4000000 */
 379
 380
 381 /*
 382  * BR6 and OR6 (Expansion bus)
 383  * Base address = 0xE800_0000 - 0xEBFF_FFFF
 384  *
 385  */
 386
 387 #define CFG_OR6_PRELIM          0xFF000000
 388 #define CFG_BR6_PRELIM          0xE8000000
 389 /* #define CFG_OR6              0xFF000000 */
 390 /* #define CFG_BR6              0xE8000000 */
 391
 392
 393 /*
 394  * BR7 and OR7 (Expansion bus)
 395  * Base address = 0xEC00_0000 - 0xEFFF_FFFF
 396  *
 397  */
 398
 399 #define CFG_OR7_PRELIM          0xFF000000
 400 #define CFG_BR7_PRELIM          0xE8000000
 401 /* #define CFG_OR7              0xFF000000 */
 402 /* #define CFG_BR7              0xE8000000 */
 403
 404
 405 /*
 406  * Internal Definitions
 407  *
 408  * Boot Flags
 409  */
 410 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
 411 #define BOOTFLAG_WARM           0x02    /* Software reboot */
 412
 413 /*
 414  * Sanity checks
 415  */
 416 #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
 417 #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
 418 #endif
 419
 420 #endif /* __CONFIG_H */