include/configs/R360MPI.h

   1 /*
   2  * (C) Copyright 2000-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC823           1       /* This is a MPC823 CPU         */
  21 #define CONFIG_R360MPI          1
  22
  23 #define CONFIG_SYS_TEXT_BASE    0x40000000
  24
  25 #define CONFIG_LCD
  26 #define CONFIG_MPC8XX_LCD
  27 #undef  CONFIG_EDT32F10
  28 #define CONFIG_SHARP_LQ057Q3DC02
  29
  30 #define CONFIG_SPLASH_SCREEN
  31
  32 #define MPC8XX_FACT             1               /* Multiply by 1        */
  33 #define MPC8XX_XIN              50000000        /* 50 MHz in            */
  34 #define CONFIG_8xx_GCLK_FREQ    50000000 /* define if can't use get_gclk_freq */
  35
  36 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  37 #undef  CONFIG_8xx_CONS_SMC2
  38 #undef  CONFIG_8xx_CONS_NONE
  39 #define CONFIG_BAUDRATE         115200  /* console baudrate in bps      */
  40 #if 0
  41 #define CONFIG_BOOTDELAY        0       /* immediate boot               */
  42 #else
  43 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  44 #endif
  45
  46 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  47
  48 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  49
  50 #undef  CONFIG_BOOTARGS
  51 #define CONFIG_BOOTCOMMAND                                                      \
  52         "bootp; "                                                               \
  53         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
  54         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
  55         "bootm"
  56
  57 #undef  CONFIG_SCC1_ENET
  58 #define CONFIG_SCC2_ENET
  59
  60 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  61 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  62
  63 #define CONFIG_MISC_INIT_R              /* have misc_init_r() function  */
  64
  65 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  66
  67 #define CONFIG_CAN_DRIVER               /* CAN Driver support enabled   */
  68
  69 /*
  70  * BOOTP options
  71  */
  72 #define CONFIG_BOOTP_SUBNETMASK
  73 #define CONFIG_BOOTP_GATEWAY
  74 #define CONFIG_BOOTP_HOSTNAME
  75 #define CONFIG_BOOTP_BOOTPATH
  76 #define CONFIG_BOOTP_BOOTFILESIZE
  77
  78 #define CONFIG_MAC_PARTITION
  79 #define CONFIG_DOS_PARTITION
  80
  81 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  82
  83 #define CONFIG_HARD_I2C         1       /* To I2C with hardware support */
  84 #undef CONFIG_SYS_I2C_SOFT              /* To I2C with software support */
  85 #define CONFIG_SYS_I2C_SPEED            4700    /* I2C speed and slave address */
  86 #define CONFIG_SYS_I2C_SLAVE            0x7F
  87
  88 #if defined(CONFIG_SYS_I2C_SOFT)
  89 #define CONFIG_SYS_SYS_I2C_SOFT_SPEED   4700 /* I2C speed and slave address */
  90 #define CONFIG_SYS_SYS_I2C_SOFT_SLAVE   0x7F
  91 /*
  92  * Software (bit-bang) I2C driver configuration
  93  */
  94 #define PB_SCL                  0x00000020      /* PB 26 */
  95 #define PB_SDA                  0x00000010      /* PB 27 */
  96
  97 #define I2C_INIT                (immr->im_cpm.cp_pbdir |=  PB_SCL)
  98 #define I2C_ACTIVE              (immr->im_cpm.cp_pbdir |=  PB_SDA)
  99 #define I2C_TRISTATE            (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 100 #define I2C_READ                ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 101 #define I2C_SDA(bit)            if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 102                                 else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 103 #define I2C_SCL(bit)            if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 104                                 else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 105 #define I2C_DELAY               udelay(50)
 106 #endif /* #define(CONFIG_SYS_I2C_SOFT) */
 107
 108 #define CONFIG_SYS_I2C_LCD_ADDR 0x8     /* LCD Control */
 109 #define CONFIG_SYS_I2C_KEY_ADDR 0x9     /* Keyboard coprocessor */
 110 #define CONFIG_SYS_I2C_TEM_ADDR 0x49    /* Temperature Sensors */
 111
 112
 113 /*
 114  * Command line configuration.
 115  */
 116 #include <config_cmd_default.h>
 117
 118 #define CONFIG_CMD_BMP
 119 #define CONFIG_CMD_BSP
 120 #define CONFIG_CMD_DATE
 121 #define CONFIG_CMD_DHCP
 122 #define CONFIG_CMD_I2C
 123 #define CONFIG_CMD_IDE
 124 #define CONFIG_CMD_JFFS2
 125 #define CONFIG_CMD_NFS
 126 #define CONFIG_CMD_PCMCIA
 127 #define CONFIG_CMD_SNTP
 128
 129
 130 /*
 131  * Miscellaneous configurable options
 132  */
 133 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* we need the null device      */
 134 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    1       /* must set console from env    */
 135
 136 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 137 #if defined(CONFIG_CMD_KGDB)
 138 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 139 #else
 140 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 141 #endif
 142 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 143 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 144 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 145
 146 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 147 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 148
 149 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 150
 151 /*
 152  * JFFS2 partitions
 153  */
 154 /* No command line, one static partition
 155  * use all the space starting at offset 3MB*/
 156 #undef CONFIG_CMD_MTDPARTS
 157 #define CONFIG_JFFS2_DEV                "nor0"
 158 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 159 #define CONFIG_JFFS2_PART_OFFSET        0x00300000
 160
 161 /* mtdparts command line support */
 162 /*
 163 #define CONFIG_CMD_MTDPARTS
 164 #define MTDIDS_DEFAULT          "nor0=r360-0"
 165 #define MTDPARTS_DEFAULT        "mtdparts=r360-0:-@3m(user)"
 166 */
 167
 168 /*
 169  * Low Level Configuration Settings
 170  * (address mappings, register initial values, etc.)
 171  * You should know what you are doing if you make changes here.
 172  */
 173 /*-----------------------------------------------------------------------
 174  * Internal Memory Mapped Register
 175  */
 176 #define CONFIG_SYS_IMMR         0xFF000000
 177
 178 /*-----------------------------------------------------------------------
 179  * Definitions for initial stack pointer and data area (in DPRAM)
 180  */
 181 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 182 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 183 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 184 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 185
 186 /*-----------------------------------------------------------------------
 187  * Start addresses for the final memory configuration
 188  * (Set up by the startup code)
 189  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 190  */
 191 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 192 #define CONFIG_SYS_FLASH_BASE           0x40000000
 193 #if defined(DEBUG)
 194 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 195 #else
 196 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor   */
 197 #endif
 198 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 199 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 200
 201 /*
 202  * For booting Linux, the board info and command line data
 203  * have to be in the first 8 MB of memory, since this is
 204  * the maximum mapped by the Linux kernel during initialization.
 205  */
 206 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 207
 208 /*-----------------------------------------------------------------------
 209  * FLASH organization
 210  */
 211 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 212 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max number of sectors on one chip    */
 213
 214 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 215 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 216
 217 #define CONFIG_ENV_IS_IN_FLASH  1
 218 #define CONFIG_ENV_OFFSET               0x40000 /* Offset of Environment                */
 219 #define CONFIG_ENV_SECT_SIZE    0x20000 /* Total Size of Environment sector     */
 220 #define CONFIG_ENV_SIZE         0x4000  /* Used Size of Environment sector      */
 221 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 222
 223 /*-----------------------------------------------------------------------
 224  * Cache Configuration
 225  */
 226 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 227 #if defined(CONFIG_CMD_KGDB)
 228 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 229 #endif
 230
 231 /*-----------------------------------------------------------------------
 232  * SYPCR - System Protection Control                            11-9
 233  * SYPCR can only be written once after reset!
 234  *-----------------------------------------------------------------------
 235  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 236  */
 237 #if defined(CONFIG_WATCHDOG)
 238 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 239                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 240 #else
 241 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 242 #endif
 243
 244 /*-----------------------------------------------------------------------
 245  * SIUMCR - SIU Module Configuration                            11-6
 246  *-----------------------------------------------------------------------
 247  * PCMCIA config., multi-function pin tri-state
 248  */
 249 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 250
 251 /*-----------------------------------------------------------------------
 252  * TBSCR - Time Base Status and Control                         11-26
 253  *-----------------------------------------------------------------------
 254  * Clear Reference Interrupt Status, Timebase freezing enabled
 255  */
 256 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 257
 258 /*-----------------------------------------------------------------------
 259  * RTCSC - Real-Time Clock Status and Control Register          11-27
 260  *-----------------------------------------------------------------------
 261  */
 262 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 263
 264 /*-----------------------------------------------------------------------
 265  * PISCR - Periodic Interrupt Status and Control                11-31
 266  *-----------------------------------------------------------------------
 267  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 268  */
 269 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 270
 271 /*-----------------------------------------------------------------------
 272  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 273  *-----------------------------------------------------------------------
 274  * Reset PLL lock status sticky bit, timer expired status bit and timer
 275  * interrupt status bit
 276  *
 277  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 278  */
 279 #ifdef  CONFIG_80MHz    /* for 80 MHz, we use a 16 MHz clock * 5 */
 280 #define CONFIG_SYS_PLPRCR                                                       \
 281                 ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
 282 #else                   /* up to 50 MHz we use a 1:1 clock */
 283 #define CONFIG_SYS_PLPRCR       (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 284 #endif  /* CONFIG_80MHz */
 285
 286 /*-----------------------------------------------------------------------
 287  * SCCR - System Clock and reset Control Register               15-27
 288  *-----------------------------------------------------------------------
 289  * Set clock output, timebase and RTC source and divider,
 290  * power management and some other internal clocks
 291  */
 292 #define SCCR_MASK       SCCR_EBDF11
 293 #define CONFIG_SYS_SCCR (SCCR_TBS     | \
 294                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 295                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 296                          SCCR_DFALCD00)
 297
 298 /*-----------------------------------------------------------------------
 299  * PCMCIA stuff
 300  *-----------------------------------------------------------------------
 301  *
 302  */
 303 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 304 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 305 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 306 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 307 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 308 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 309 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 310 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 311
 312 /*-----------------------------------------------------------------------
 313  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 314  *-----------------------------------------------------------------------
 315  */
 316
 317 #if 1
 318 #define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 319 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 320
 321 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 322 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 323 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 324
 325 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 326 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 327
 328 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 329
 330 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 331
 332 /* Offset for data I/O                  */
 333 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 334
 335 /* Offset for normal register accesses  */
 336 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 337
 338 /* Offset for alternate registers       */
 339 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 340 #endif
 341
 342 /*-----------------------------------------------------------------------
 343  *
 344  *-----------------------------------------------------------------------
 345  *
 346  */
 347 #define CONFIG_SYS_DER  0
 348
 349 /*
 350  * Init Memory Controller:
 351  *
 352  * BR0/1 and OR0/1 (FLASH)
 353  */
 354
 355 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 356
 357 /* used to re-map FLASH both when starting from SRAM or FLASH:
 358  * restrict access enough to keep SRAM working (if any)
 359  * but not too much to meddle with FLASH accesses
 360  */
 361 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 362 #define CONFIG_SYS_PRELIM_OR_AM 0xFF000000      /* OR addr mask */
 363
 364 /*
 365  * FLASH timing:
 366  */
 367 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_ACS_DIV1 | OR_SCY_7_CLK | OR_BI)
 368
 369 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 370 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 371 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 372
 373
 374 /*
 375  * BR2 and OR2 (SDRAM)
 376  *
 377  */
 378 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 379 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 380
 381 #define CONFIG_SYS_PRELIM_OR2_AM        0xF8000000      /* OR addr mask */
 382
 383 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 384 #define CONFIG_SYS_OR_TIMING_SDRAM      (OR_ACS_DIV1  | OR_CSNT_SAM | \
 385                                  OR_SCY_0_CLK | OR_G5LS)
 386
 387 #define CONFIG_SYS_OR2_PRELIM   (CONFIG_SYS_PRELIM_OR2_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 388 #define CONFIG_SYS_BR2_PRELIM   ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 389
 390 /*
 391  * BR3 and OR3 (CAN Controller)
 392  */
 393 #ifdef CONFIG_CAN_DRIVER
 394 #define CONFIG_SYS_CAN_BASE             0xC0000000      /* CAN base address   */
 395 #define CONFIG_SYS_CAN_OR_AM            0xFFFF8000      /* 32 kB address mask */
 396 #define CONFIG_SYS_OR3_CAN              (CONFIG_SYS_CAN_OR_AM | OR_G5LA |OR_BI)
 397 #define CONFIG_SYS_BR3_CAN              ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 398                                  BR_PS_8 | BR_MS_UPMB | BR_V)
 399 #endif  /* CONFIG_CAN_DRIVER */
 400
 401
 402 /*
 403  * Memory Periodic Timer Prescaler
 404  *
 405  * The Divider for PTA (refresh timer) configuration is based on an
 406  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 407  * the number of chip selects (NCS) and the actually needed refresh
 408  * rate is done by setting MPTPR.
 409  *
 410  * PTA is calculated from
 411  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 412  *
 413  *      gclk      CPU clock (not bus clock!)
 414  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 415  *
 416  * 4096  Rows from SDRAM example configuration
 417  * 1000  factor s -> ms
 418  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 419  *    4  Number of refresh cycles per period
 420  *   64  Refresh cycle in ms per number of rows
 421  * --------------------------------------------
 422  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 423  *
 424  * 50 MHz => 50.000.000 / Divider =  98
 425  * 66 Mhz => 66.000.000 / Divider = 129
 426  * 80 Mhz => 80.000.000 / Divider = 156
 427  */
 428 #if   defined(CONFIG_80MHz)
 429 #define CONFIG_SYS_MAMR_PTA             156
 430 #elif defined(CONFIG_66MHz)
 431 #define CONFIG_SYS_MAMR_PTA             129
 432 #else           /*   50 MHz */
 433 #define CONFIG_SYS_MAMR_PTA              98
 434 #endif  /*CONFIG_??MHz */
 435
 436 /*
 437  * For 16 MBit, refresh rates could be 31.3 us
 438  * (= 64 ms / 2K = 125 / quad bursts).
 439  * For a simpler initialization, 15.6 us is used instead.
 440  *
 441  * #define CONFIG_SYS_MPTPR_2BK_2K      MPTPR_PTP_DIV32         for 2 banks
 442  * #define CONFIG_SYS_MPTPR_1BK_2K      MPTPR_PTP_DIV64         for 1 bank
 443  */
 444 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 445 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 446
 447 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 448 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 449 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 450
 451 /*
 452  * MAMR settings for SDRAM
 453  */
 454
 455 /* 8 column SDRAM */
 456 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 457                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 458                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 459 /* 9 column SDRAM */
 460 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 461                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 462                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 463
 464 #endif  /* __CONFIG_H */