include/configs/RBC823.h

   1 /*
   2  * (C) Copyright 2000, 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * Modified by Udi Finkelstein udif@udif.com
   6  * For the RBC823 board.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /*
  12  * board/config.h - configuration options, board specific
  13  */
  14
  15 #ifndef __CONFIG_H
  16 #define __CONFIG_H
  17
  18 /*
  19  * High Level Configuration Options
  20  * (easy to change)
  21  */
  22
  23 #define CONFIG_MPC823           1       /* This is a MPC823 CPU         */
  24 #define CONFIG_RBC823           1       /* ...on a RBC823 module        */
  25
  26 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  27
  28 #if 0
  29 #define DEBUG                   1
  30 #define CONFIG_LAST_STAGE_INIT
  31 #endif
  32 #define CONFIG_KEYBOARD         1       /* This board has a custom keybpard */
  33 #define CONFIG_LCD              1       /* use LCD controller ...       */
  34 #define CONFIG_MPC8XX_LCD
  35 #define CONFIG_HITACHI_SP19X001_Z1A     /* The LCD type we use */
  36
  37 #define CONFIG_8xx_CONS_SMC2    1       /* Console is on SMC2           */
  38 #undef  CONFIG_8xx_CONS_SMC1
  39 #undef  CONFIG_8xx_CONS_NONE
  40 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  41 #if 1
  42 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  43 #else
  44 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  45 #endif
  46
  47 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  48 #define CONFIG_8xx_GCLK_FREQ    48000000L
  49
  50 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  51
  52 #undef  CONFIG_BOOTARGS
  53 #define CONFIG_BOOTCOMMAND                                                      \
  54         "bootp; "                                                               \
  55         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
  56         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
  57         "bootm"
  58
  59 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  60 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  61
  62 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  63
  64 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  65
  66 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  67
  68 /*
  69  * BOOTP options
  70  */
  71 #define CONFIG_BOOTP_SUBNETMASK
  72 #define CONFIG_BOOTP_GATEWAY
  73 #define CONFIG_BOOTP_HOSTNAME
  74 #define CONFIG_BOOTP_BOOTPATH
  75 #define CONFIG_BOOTP_BOOTFILESIZE
  76
  77
  78 #undef CONFIG_MAC_PARTITION
  79 #define CONFIG_DOS_PARTITION
  80
  81 #undef  CONFIG_RTC_MPC8xx               /* don't use internal RTC of MPC8xx (no battery)        */
  82
  83 #define CONFIG_HARD_I2C
  84 #define CONFIG_SYS_I2C_SPEED 40000
  85 #define CONFIG_SYS_I2C_SLAVE 0xfe
  86 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
  87 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
  88 #define CONFIG_SYS_EEPROM_WRITE_BITS            4
  89 #define CONFIG_SYS_EEPROM_WRITE_DELAY_MS        10
  90
  91 /*
  92  * Command line configuration.
  93  */
  94 #include <config_cmd_default.h>
  95
  96 #define CONFIG_CMD_ASKENV
  97 #define CONFIG_CMD_BEDBUG
  98 #define CONFIG_CMD_BMP
  99 #define CONFIG_CMD_CACHE
 100 #define CONFIG_CMD_CDP
 101 #define CONFIG_CMD_DHCP
 102 #define CONFIG_CMD_DIAG
 103 #define CONFIG_CMD_EEPROM
 104 #define CONFIG_CMD_ELF
 105 #define CONFIG_CMD_FAT
 106 #define CONFIG_CMD_I2C
 107 #define CONFIG_CMD_IMMAP
 108 #define CONFIG_CMD_KGDB
 109 #define CONFIG_CMD_PING
 110 #define CONFIG_CMD_PORTIO
 111 #define CONFIG_CMD_REGINFO
 112 #define CONFIG_CMD_SAVES
 113 #define CONFIG_CMD_SDRAM
 114
 115 #undef CONFIG_CMD_SETGETDCR
 116 #undef CONFIG_CMD_XIMG
 117
 118 /*
 119  * Miscellaneous configurable options
 120  */
 121 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 122 #if defined(CONFIG_CMD_KGDB)
 123 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 124 #else
 125 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 126 #endif
 127 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 128 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 129 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 130
 131 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 132 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 133
 134 #define CONFIG_SYS_LOAD_ADDR            0x0100000       /* default load address */
 135
 136 /*
 137  * Low Level Configuration Settings
 138  * (address mappings, register initial values, etc.)
 139  * You should know what you are doing if you make changes here.
 140  */
 141 /*-----------------------------------------------------------------------
 142  * Internal Memory Mapped Register
 143  */
 144 #define CONFIG_SYS_IMMR         0xFF000000
 145
 146 /*-----------------------------------------------------------------------
 147  * Definitions for initial stack pointer and data area (in DPRAM)
 148  */
 149 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 150 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 151 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 152 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 153
 154 /*-----------------------------------------------------------------------
 155  * Start addresses for the final memory configuration
 156  * (Set up by the startup code)
 157  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 158  */
 159 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 160 #define CONFIG_SYS_FLASH_BASE           0xFFF00000
 161 #if defined(DEBUG)
 162 #define CONFIG_SYS_MONITOR_LEN          (384 << 10)     /* Reserve 256 kB for Monitor   */
 163 #else
 164 #define CONFIG_SYS_MONITOR_LEN          (384 << 10)     /* Reserve 192 kB for Monitor   */
 165 #endif
 166 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 167 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 168
 169 /*
 170  * For booting Linux, the board info and command line data
 171  * have to be in the first 8 MB of memory, since this is
 172  * the maximum mapped by the Linux kernel during initialization.
 173  */
 174 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 175
 176 /*-----------------------------------------------------------------------
 177  * FLASH organization
 178  */
 179 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 180 #define CONFIG_SYS_MAX_FLASH_SECT       67      /* max number of sectors on one chip    */
 181
 182 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 183 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 184
 185 #define CONFIG_ENV_IS_IN_FLASH  1
 186 #define CONFIG_ENV_OFFSET               0x10000 /*   Offset   of Environment Sector     */
 187 #define CONFIG_ENV_SIZE         0x10000 /* Total Size of Environment Sector     */
 188
 189 /*-----------------------------------------------------------------------
 190  * Cache Configuration
 191  */
 192 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 193 #if defined(CONFIG_CMD_KGDB)
 194 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 195 #endif
 196
 197 /*-----------------------------------------------------------------------
 198  * SYPCR - System Protection Control                            11-9
 199  * SYPCR can only be written once after reset!
 200  *-----------------------------------------------------------------------
 201  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 202  */
 203 #if defined(CONFIG_WATCHDOG)
 204 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 205                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 206 #else
 207 /*
 208 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 209 */
 210 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWRI | SYPCR_SWP)
 211 #endif
 212
 213 /*-----------------------------------------------------------------------
 214  * SIUMCR - SIU Module Configuration                            11-6
 215  *-----------------------------------------------------------------------
 216  * PCMCIA config., multi-function pin tri-state
 217  */
 218 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_FRC)
 219
 220 /*-----------------------------------------------------------------------
 221  * TBSCR - Time Base Status and Control                         11-26
 222  *-----------------------------------------------------------------------
 223  * Clear Reference Interrupt Status, Timebase freezing enabled
 224  */
 225 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 226
 227 /*-----------------------------------------------------------------------
 228  * RTCSC - Real-Time Clock Status and Control Register          11-27
 229  *-----------------------------------------------------------------------
 230  */
 231 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 232
 233 /*-----------------------------------------------------------------------
 234  * PISCR - Periodic Interrupt Status and Control                11-31
 235  *-----------------------------------------------------------------------
 236  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 237  */
 238 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 239
 240 /*-----------------------------------------------------------------------
 241  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 242  *-----------------------------------------------------------------------
 243  * Reset PLL lock status sticky bit, timer expired status bit and timer
 244  * interrupt status bit
 245  *
 246  */
 247
 248 /*
 249  * for 48 MHz, we use a 4 MHz clock * 12
 250  */
 251 #define CONFIG_SYS_PLPRCR                                                       \
 252                 ( (12-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_LOLRE )
 253
 254 /*-----------------------------------------------------------------------
 255  * SCCR - System Clock and reset Control Register               15-27
 256  *-----------------------------------------------------------------------
 257  * Set clock output, timebase and RTC source and divider,
 258  * power management and some other internal clocks
 259  */
 260 #define SCCR_MASK       SCCR_EBDF11
 261 #define CONFIG_SYS_SCCR (SCCR_RTDIV   | SCCR_RTSEL    | SCCR_CRQEN    | \
 262                          SCCR_PRQEN   | SCCR_EBDF00   | \
 263                          SCCR_COM01   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 264                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD001 | \
 265                          SCCR_DFALCD00)
 266
 267 #ifdef NOT_USED
 268 /*-----------------------------------------------------------------------
 269  * PCMCIA stuff
 270  *-----------------------------------------------------------------------
 271  *
 272  */
 273 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 274 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 275 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 276 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 277 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 278 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 279 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 280 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 281
 282 /*-----------------------------------------------------------------------
 283  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 284  *-----------------------------------------------------------------------
 285  */
 286
 287 #define CONFIG_IDE_PCCARD       1       /* Use IDE with PC Card Adapter */
 288
 289 #undef  CONFIG_IDE_PCMCIA               /* Direct IDE    not supported  */
 290 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 291 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 292
 293 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 294 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 295
 296 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 297
 298 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 299
 300 /* Offset for data I/O                  */
 301 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 302
 303 /* Offset for normal register accesses  */
 304 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 305
 306 /* Offset for alternate registers       */
 307 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 308
 309 #endif
 310
 311 /*-----------------------------------------------------------------------
 312  *
 313  *-----------------------------------------------------------------------
 314  *
 315  */
 316 /*#define       CONFIG_SYS_DER  0x2002000F*/
 317 #define CONFIG_SYS_DER  0
 318
 319 /*
 320  * Init Memory Controller:
 321  *
 322  * BR0/1 and OR0/1 (FLASH)
 323  */
 324
 325 #define FLASH_BASE0_PRELIM      0xFFF00000      /* FLASH bank #0        */
 326 #define FLASH_BASE1_PRELIM      0x04000000      /* D.O.C Millenium      */
 327
 328 /* used to re-map FLASH both when starting from SRAM or FLASH:
 329  * restrict access enough to keep SRAM working (if any)
 330  * but not too much to meddle with FLASH accesses
 331  */
 332 #define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000      /* OR addr mask */
 333
 334 /* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 7, EHTR = 1        */
 335 #define CONFIG_SYS_OR_TIMING_FLASH  (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR)
 336
 337 #define CONFIG_SYS_OR_TIMING_MSYS   (OR_ACS_DIV1 | OR_BI)
 338
 339 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 340 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
 341
 342 #define CONFIG_SYS_OR1_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_MSYS)
 343 #define CONFIG_SYS_BR1_PRELIM   ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | \
 344                           BR_PS_8 | BR_V)
 345
 346 /*
 347  * BR4 and OR4 (SDRAM)
 348  *
 349  */
 350 #define SDRAM_BASE4_PRELIM      0x00000000      /* SDRAM bank #0        */
 351 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 352
 353 /*
 354  * SDRAM timing:
 355  */
 356 #define CONFIG_SYS_OR_TIMING_SDRAM      (OR_CSNT_SAM)
 357
 358 #define CONFIG_SYS_OR4_PRELIM   (~(SDRAM_MAX_SIZE-1) | CONFIG_SYS_OR_TIMING_SDRAM )
 359 #define CONFIG_SYS_BR4_PRELIM   ((SDRAM_BASE4_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 360
 361 /*
 362  * Memory Periodic Timer Prescaler
 363  */
 364
 365 /* periodic timer for refresh */
 366 #define CONFIG_SYS_MAMR_PTA     187             /* start with divider for 48 MHz        */
 367
 368 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit     */
 369 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 370 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 371
 372 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 373 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 374 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 375
 376 /*
 377  * MAMR settings for SDRAM
 378  */
 379
 380 /* 8 column SDRAM */
 381 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 382                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 383                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 384 /* 9 column SDRAM */
 385 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 386                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 387                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 388
 389 /*
 390  * JFFS2 partitions
 391  *
 392  */
 393 /* No command line, one static partition, whole device */
 394 #undef CONFIG_CMD_MTDPARTS
 395 #define CONFIG_JFFS2_DEV                "nor0"
 396 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 397 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 398
 399 /* mtdparts command line support */
 400 /* Note: fake mtd_id used, no linux mtd map file */
 401 /*
 402 #define CONFIG_CMD_MTDPARTS
 403 #define MTDIDS_DEFAULT          ""
 404 #define MTDPARTS_DEFAULT        ""
 405 */
 406
 407 #endif  /* __CONFIG_H */