include/configs/RPXlite.h

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 /* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
  29  * U-Boot port on RPXlite board
  30  */
  31
  32 #ifndef __CONFIG_H
  33 #define __CONFIG_H
  34
  35 #define RPXLite_50MHz
  36
  37 /*
  38  * High Level Configuration Options
  39  * (easy to change)
  40  */
  41
  42 #undef CONFIG_MPC860
  43 #define CONFIG_MPC850           1       /* This is a MPC850 CPU         */
  44 #define CONFIG_RPXLITE          1
  45
  46 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  47 #undef  CONFIG_8xx_CONS_SMC2
  48 #undef  CONFIG_8xx_CONS_NONE
  49 #define CONFIG_BAUDRATE         9600    /* console baudrate = 9600bps   */
  50 #if 0
  51 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  52 #else
  53 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  54 #endif
  55
  56 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  57
  58 #undef  CONFIG_BOOTARGS
  59 #define CONFIG_BOOTCOMMAND                                                      \
  60         "bootp; "                                                               \
  61         "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "     \
  62         "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; "   \
  63         "bootm"
  64
  65 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  66 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
  67
  68 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  69
  70 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
  71
  72 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  73 #include <cmd_confdefs.h>
  74
  75 /*
  76  * Miscellaneous configurable options
  77  */
  78 #define CFG_LONGHELP                    /* undef to save memory         */
  79 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
  80 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  81 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
  82 #else
  83 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
  84 #endif
  85 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  86 #define CFG_MAXARGS     16              /* max number of command args   */
  87 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
  88
  89 #define CFG_MEMTEST_START       0x0040000       /* memtest works on     */
  90 #define CFG_MEMTEST_END         0x00C0000       /* 4 ... 12 MB in DRAM  */
  91
  92 #define CFG_LOAD_ADDR           0x100000        /* default load address */
  93
  94 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
  95
  96 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
  97
  98 /*
  99  * Low Level Configuration Settings
 100  * (address mappings, register initial values, etc.)
 101  * You should know what you are doing if you make changes here.
 102  */
 103 /*-----------------------------------------------------------------------
 104  * Internal Memory Mapped Register
 105  */
 106 #define CFG_IMMR                0xFA200000
 107
 108 /*-----------------------------------------------------------------------
 109  * Definitions for initial stack pointer and data area (in DPRAM)
 110  */
 111 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 112 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 113 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 114 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 115 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 116
 117 /*-----------------------------------------------------------------------
 118  * Start addresses for the final memory configuration
 119  * (Set up by the startup code)
 120  * Please note that CFG_SDRAM_BASE _must_ start at 0
 121  */
 122 #define CFG_SDRAM_BASE          0x00000000
 123 #define CFG_FLASH_BASE  0xFFC00000
 124 /*%%% #define CFG_FLASH_BASE            0xFFF00000 */
 125 #if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
 126 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 127 #else
 128 #define CFG_MONITOR_LEN         (128 << 10)     /* Reserve 128 kB for Monitor   */
 129 #endif
 130 #define CFG_MONITOR_BASE        0xFFF00000
 131 /*%%% #define CFG_MONITOR_BASE  CFG_FLASH_BASE */
 132 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 133
 134 /*
 135  * For booting Linux, the board info and command line data
 136  * have to be in the first 8 MB of memory, since this is
 137  * the maximum mapped by the Linux kernel during initialization.
 138  */
 139 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 140
 141 /*-----------------------------------------------------------------------
 142  * FLASH organization
 143  */
 144 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 145 #define CFG_MAX_FLASH_SECT      19      /* max number of sectors on one chip    */
 146
 147 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 148 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 149
 150 #define CFG_ENV_IS_IN_FLASH     1
 151 #define CFG_ENV_OFFSET          0x8000  /*   Offset   of Environment Sector     */
 152 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
 153
 154 /*-----------------------------------------------------------------------
 155  * Cache Configuration
 156  */
 157 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 158 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 159 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 160 #endif
 161
 162 /*-----------------------------------------------------------------------
 163  * SYPCR - System Protection Control                            11-9
 164  * SYPCR can only be written once after reset!
 165  *-----------------------------------------------------------------------
 166  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 167  */
 168 #if defined(CONFIG_WATCHDOG)
 169 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 170                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 171 #else
 172 #define CFG_SYPCR       (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 173 #endif
 174
 175 /*-----------------------------------------------------------------------
 176  * SIUMCR - SIU Module Configuration                            11-6
 177  *-----------------------------------------------------------------------
 178  * PCMCIA config., multi-function pin tri-state
 179  */
 180 #define CFG_SIUMCR      (SIUMCR_MLRC10)
 181
 182 /*-----------------------------------------------------------------------
 183  * TBSCR - Time Base Status and Control                         11-26
 184  *-----------------------------------------------------------------------
 185  * Clear Reference Interrupt Status, Timebase freezing enabled
 186  */
 187 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
 188
 189 /*-----------------------------------------------------------------------
 190  * RTCSC - Real-Time Clock Status and Control Register          11-27
 191  *-----------------------------------------------------------------------
 192  */
 193 /*%%%#define CFG_RTCSC  (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
 194 #define CFG_RTCSC       (RTCSC_SEC | RTCSC_RTE)
 195
 196 /*-----------------------------------------------------------------------
 197  * PISCR - Periodic Interrupt Status and Control                11-31
 198  *-----------------------------------------------------------------------
 199  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 200  */
 201 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
 202
 203 /*-----------------------------------------------------------------------
 204  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 205  *-----------------------------------------------------------------------
 206  * Reset PLL lock status sticky bit, timer expired status bit and timer
 207  * interrupt status bit
 208  *
 209  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 210  */
 211 /* up to 50 MHz we use a 1:1 clock */
 212 #define CFG_PLPRCR      ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
 213
 214 /*-----------------------------------------------------------------------
 215  * SCCR - System Clock and reset Control Register               15-27
 216  *-----------------------------------------------------------------------
 217  * Set clock output, timebase and RTC source and divider,
 218  * power management and some other internal clocks
 219  */
 220 #define SCCR_MASK       SCCR_EBDF00
 221 /* up to 50 MHz we use a 1:1 clock */
 222 #define CFG_SCCR        (SCCR_COM11 | SCCR_TBS)
 223
 224 /*-----------------------------------------------------------------------
 225  * PCMCIA stuff
 226  *-----------------------------------------------------------------------
 227  *
 228  */
 229 #define CFG_PCMCIA_MEM_ADDR     (0xE0000000)
 230 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 231 #define CFG_PCMCIA_DMA_ADDR     (0xE4000000)
 232 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 233 #define CFG_PCMCIA_ATTRB_ADDR   (0xE8000000)
 234 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 235 #define CFG_PCMCIA_IO_ADDR      (0xEC000000)
 236 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 237
 238 /*-----------------------------------------------------------------------
 239  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 240  *-----------------------------------------------------------------------
 241  */
 242
 243 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 244
 245 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 246 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 247 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 248
 249 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 250 #define CFG_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus     */
 251
 252 #define CFG_ATA_IDE0_OFFSET     0x0000
 253
 254 #define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
 255
 256 /* Offset for data I/O                  */
 257 #define CFG_ATA_DATA_OFFSET     (CFG_PCMCIA_MEM_SIZE + 0x320)
 258
 259 /* Offset for normal register accesses  */
 260 #define CFG_ATA_REG_OFFSET      (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
 261
 262 /* Offset for alternate registers       */
 263 #define CFG_ATA_ALT_OFFSET      0x0100
 264
 265 /*-----------------------------------------------------------------------
 266  *
 267  *-----------------------------------------------------------------------
 268  *
 269  */
 270 /*#define       CFG_DER 0x2002000F*/
 271 #define CFG_DER 0
 272
 273 /*
 274  * Init Memory Controller:
 275  *
 276  * BR0 and OR0 (FLASH)
 277  */
 278
 279 #define FLASH_BASE_PRELIM       0xFE000000      /* FLASH base */
 280 #define CFG_PRELIM_OR_AM        0xFE000000      /* OR addr mask */
 281
 282 /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
 283 #define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
 284
 285 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 286 #define CFG_BR0_PRELIM  ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
 287
 288 /*
 289  * BR1 and OR1 (SDRAM)
 290  *
 291  */
 292 #define SDRAM_BASE_PRELIM       0x00000000      /* SDRAM base   */
 293 #define SDRAM_MAX_SIZE          0x01000000      /* max 16 MB */
 294
 295 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 296 #define CFG_OR_TIMING_SDRAM     0x00000E00
 297
 298 #define CFG_OR1_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
 299 #define CFG_BR1_PRELIM  ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 300
 301 /* RPXLITE mem setting */
 302 #define CFG_BR3_PRELIM  0xFA400001              /* BCSR */
 303 #define CFG_OR3_PRELIM  0xFFFF8910
 304 #define CFG_BR4_PRELIM  0xFA000401              /* NVRAM&SRAM */
 305 #define CFG_OR4_PRELIM  0xFFFE0970
 306
 307 /*
 308  * Memory Periodic Timer Prescaler
 309  */
 310
 311 /* periodic timer for refresh */
 312 #define CFG_MAMR_PTA    58
 313
 314 /*
 315  * Refresh clock Prescalar
 316  */
 317 #define CFG_MPTPR       MPTPR_PTP_DIV8
 318
 319 /*
 320  * MAMR settings for SDRAM
 321  */
 322
 323 /* 10 column SDRAM */
 324 #define CFG_MAMR_10COL  ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 325                          MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 |   \
 326                          MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
 327
 328 /*
 329  * Internal Definitions
 330  *
 331  * Boot Flags
 332  */
 333 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 334 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 335
 336
 337 /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
 338 /* Configuration variable added by yooth. */
 339 /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
 340
 341 /*
 342  * BCSRx
 343  *
 344  * Board Status and Control Registers
 345  *
 346  */
 347
 348 #define BCSR0 0xFA400000
 349 #define BCSR1 0xFA400001
 350 #define BCSR2 0xFA400002
 351 #define BCSR3 0xFA400003
 352
 353 #define BCSR0_ENMONXCVR 0x01    /* Monitor XVCR Control */
 354 #define BCSR0_ENNVRAM   0x02    /* CS4# Control */
 355 #define BCSR0_LED5              0x04    /* LED5 control 0='on' 1='off' */
 356 #define BCSR0_LED4              0x08    /* LED4 control 0='on' 1='off' */
 357 #define BCSR0_FULLDPLX  0x10    /* Ethernet XCVR Control */
 358 #define BCSR0_COLTEST   0x20
 359 #define BCSR0_ETHLPBK   0x40
 360 #define BCSR0_ETHEN             0x80
 361
 362 #define BCSR1_PCVCTL7   0x01    /* PC Slot B Control */
 363 #define BCSR1_PCVCTL6   0x02
 364 #define BCSR1_PCVCTL5   0x04
 365 #define BCSR1_PCVCTL4   0x08
 366 #define BCSR1_IPB5SEL   0x10
 367
 368 #define BCSR2_ENPA5HDR  0x08    /* USB Control */
 369 #define BCSR2_ENUSBCLK  0x10
 370 #define BCSR2_USBPWREN  0x20
 371 #define BCSR2_USBSPD    0x40
 372 #define BCSR2_USBSUSP   0x80
 373
 374 #define BCSR3_BWRTC             0x01    /* Real Time Clock Battery */
 375 #define BCSR3_BWNVR             0x02    /* NVRAM Battery */
 376 #define BCSR3_RDY_BSY   0x04    /* Flash Operation */
 377 #define BCSR3_RPXL              0x08    /* Reserved (reads back '1') */
 378 #define BCSR3_D27               0x10    /* Dip Switch settings */
 379 #define BCSR3_D26               0x20
 380 #define BCSR3_D25               0x40
 381 #define BCSR3_D24               0x80
 382
 383
 384 /*
 385  * Environment setting
 386  */
 387
 388 #define CONFIG_ETHADDR  00:10:EC:00:1D:0B
 389 #define CONFIG_IPADDR   192.168.1.65
 390 #define CONFIG_SERVERIP 192.168.1.27
 391
 392 #endif  /* __CONFIG_H */