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git.ipfire.org Git - thirdparty/u-boot.git/blob - include/configs/RPXlite.h
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
8 /* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
9 * U-Boot port on RPXlite board
18 * High Level Configuration Options
23 #define CONFIG_MPC850 1 /* This is a MPC850 CPU */
24 #define CONFIG_RPXLITE 1
26 #define CONFIG_SYS_TEXT_BASE 0xfff00000
28 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
29 #undef CONFIG_8xx_CONS_SMC2
30 #undef CONFIG_8xx_CONS_NONE
31 #define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
33 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
35 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
38 #undef CONFIG_BOOTARGS
39 #define CONFIG_BOOTCOMMAND \
41 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
42 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
45 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
46 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
48 #define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
49 #undef CONFIG_WATCHDOG /* watchdog disabled */
54 #define CONFIG_BOOTP_SUBNETMASK
55 #define CONFIG_BOOTP_GATEWAY
56 #define CONFIG_BOOTP_HOSTNAME
57 #define CONFIG_BOOTP_BOOTPATH
58 #define CONFIG_BOOTP_BOOTFILESIZE
62 * Command line configuration.
64 #include <config_cmd_default.h>
68 * Miscellaneous configurable options
70 #define CONFIG_SYS_LONGHELP /* undef to save memory */
71 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
72 #if defined(CONFIG_CMD_KGDB)
73 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
75 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
77 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
78 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
79 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
81 #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
82 #define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
84 #define CONFIG_SYS_RESET_ADDRESS 0x09900000
86 #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
88 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
91 * Low Level Configuration Settings
92 * (address mappings, register initial values, etc.)
93 * You should know what you are doing if you make changes here.
95 /*-----------------------------------------------------------------------
96 * Internal Memory Mapped Register
98 #define CONFIG_SYS_IMMR 0xFA200000
100 /*-----------------------------------------------------------------------
101 * Definitions for initial stack pointer and data area (in DPRAM)
103 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
104 #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
105 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
106 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
108 /*-----------------------------------------------------------------------
109 * Start addresses for the final memory configuration
110 * (Set up by the startup code)
111 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
113 #define CONFIG_SYS_SDRAM_BASE 0x00000000
114 #define CONFIG_SYS_FLASH_BASE 0xFFC00000
115 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
116 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
118 #define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve ~4 MB for malloc() */
120 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
121 #endif /* CONFIG_BZIP2 */
124 * For booting Linux, the board info and command line data
125 * have to be in the first 8 MB of memory, since this is
126 * the maximum mapped by the Linux kernel during initialization.
128 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
130 /*-----------------------------------------------------------------------
133 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
134 #define CONFIG_SYS_MAX_FLASH_SECT 19 /* max number of sectors on one chip */
136 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
137 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
139 #define CONFIG_SYS_DIRECT_FLASH_TFTP
141 #define CONFIG_ENV_IS_IN_FLASH 1
142 #define CONFIG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */
143 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
145 #define CONFIG_ENV_OVERWRITE
147 /*-----------------------------------------------------------------------
148 * Cache Configuration
150 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
151 #if defined(CONFIG_CMD_KGDB)
152 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
155 /*-----------------------------------------------------------------------
156 * SYPCR - System Protection Control 11-9
157 * SYPCR can only be written once after reset!
158 *-----------------------------------------------------------------------
159 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
161 #if defined(CONFIG_WATCHDOG)
162 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
163 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
165 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
168 /*-----------------------------------------------------------------------
169 * SIUMCR - SIU Module Configuration 11-6
170 *-----------------------------------------------------------------------
171 * PCMCIA config., multi-function pin tri-state
173 #define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10)
175 /*-----------------------------------------------------------------------
176 * TBSCR - Time Base Status and Control 11-26
177 *-----------------------------------------------------------------------
178 * Clear Reference Interrupt Status, Timebase freezing enabled
180 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
182 /*-----------------------------------------------------------------------
183 * RTCSC - Real-Time Clock Status and Control Register 11-27
184 *-----------------------------------------------------------------------
186 /*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
187 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_RTE)
189 /*-----------------------------------------------------------------------
190 * PISCR - Periodic Interrupt Status and Control 11-31
191 *-----------------------------------------------------------------------
192 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
194 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
196 /*-----------------------------------------------------------------------
197 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
198 *-----------------------------------------------------------------------
199 * Reset PLL lock status sticky bit, timer expired status bit and timer
200 * interrupt status bit
202 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
204 /* up to 50 MHz we use a 1:1 clock */
205 #define CONFIG_SYS_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
207 /*-----------------------------------------------------------------------
208 * SCCR - System Clock and reset Control Register 15-27
209 *-----------------------------------------------------------------------
210 * Set clock output, timebase and RTC source and divider,
211 * power management and some other internal clocks
213 #define SCCR_MASK SCCR_EBDF00
214 /* up to 50 MHz we use a 1:1 clock */
215 #define CONFIG_SYS_SCCR (SCCR_COM11 | SCCR_TBS)
217 /*-----------------------------------------------------------------------
219 *-----------------------------------------------------------------------
222 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
223 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
224 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
225 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
226 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
227 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
228 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
229 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
231 /*-----------------------------------------------------------------------
232 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
233 *-----------------------------------------------------------------------
236 #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
237 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
239 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
240 #undef CONFIG_IDE_LED /* LED for ide not supported */
241 #undef CONFIG_IDE_RESET /* reset for ide not supported */
243 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
244 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
246 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
248 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
250 /* Offset for data I/O */
251 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
253 /* Offset for normal register accesses */
254 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
256 /* Offset for alternate registers */
257 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
259 /*-----------------------------------------------------------------------
261 *-----------------------------------------------------------------------
264 /*#define CONFIG_SYS_DER 0x2002000F*/
265 #define CONFIG_SYS_DER 0
268 * Init Memory Controller:
270 * BR0 and OR0 (FLASH)
273 #define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */
274 #define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
276 /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
277 #define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
279 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
280 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
283 * BR1 and OR1 (SDRAM)
286 #define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
287 #define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
289 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
290 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00
292 #define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
293 #define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
295 /* RPXLITE mem setting */
296 #define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* BCSR */
297 #define CONFIG_SYS_OR3_PRELIM 0xFFFF8910
298 #define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
299 #define CONFIG_SYS_OR4_PRELIM 0xFFFE0970
302 * Memory Periodic Timer Prescaler
305 /* periodic timer for refresh */
306 #define CONFIG_SYS_MAMR_PTA 58
309 * Refresh clock Prescalar
311 #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV8
314 * MAMR settings for SDRAM
317 /* 10 column SDRAM */
318 #define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
319 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \
320 MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
322 /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
323 /* Configuration variable added by yooth. */
324 /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
329 * Board Status and Control Registers
333 #define BCSR0 0xFA400000
334 #define BCSR1 0xFA400001
335 #define BCSR2 0xFA400002
336 #define BCSR3 0xFA400003
338 #define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
339 #define BCSR0_ENNVRAM 0x02 /* CS4# Control */
340 #define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
341 #define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
342 #define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
343 #define BCSR0_COLTEST 0x20
344 #define BCSR0_ETHLPBK 0x40
345 #define BCSR0_ETHEN 0x80
347 #define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
348 #define BCSR1_PCVCTL6 0x02
349 #define BCSR1_PCVCTL5 0x04
350 #define BCSR1_PCVCTL4 0x08
351 #define BCSR1_IPB5SEL 0x10
353 #define BCSR2_ENPA5HDR 0x08 /* USB Control */
354 #define BCSR2_ENUSBCLK 0x10
355 #define BCSR2_USBPWREN 0x20
356 #define BCSR2_USBSPD 0x40
357 #define BCSR2_USBSUSP 0x80
359 #define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
360 #define BCSR3_BWNVR 0x02 /* NVRAM Battery */
361 #define BCSR3_RDY_BSY 0x04 /* Flash Operation */
362 #define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
363 #define BCSR3_D27 0x10 /* Dip Switch settings */
364 #define BCSR3_D26 0x20
365 #define BCSR3_D25 0x40
366 #define BCSR3_D24 0x80
368 #endif /* __CONFIG_H */