include/configs/RPXlite.h

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
  25  * U-Boot port on RPXlite board
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 #define RPXLite_50MHz
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37
  38 #undef CONFIG_MPC860
  39 #define CONFIG_MPC850           1       /* This is a MPC850 CPU         */
  40 #define CONFIG_RPXLITE          1
  41
  42 #define CONFIG_SYS_TEXT_BASE    0xfff00000
  43
  44 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  45 #undef  CONFIG_8xx_CONS_SMC2
  46 #undef  CONFIG_8xx_CONS_NONE
  47 #define CONFIG_BAUDRATE         9600    /* console baudrate = 9600bps   */
  48 #if 0
  49 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  50 #else
  51 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  52 #endif
  53
  54 #undef  CONFIG_BOOTARGS
  55 #define CONFIG_BOOTCOMMAND                                                      \
  56         "bootp; "                                                               \
  57         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
  58         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
  59         "bootm"
  60
  61 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  62 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  63
  64 #define CONFIG_BZIP2            /* Include support for bzip2 compressed images  */
  65 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  66
  67 /*
  68  * BOOTP options
  69  */
  70 #define CONFIG_BOOTP_SUBNETMASK
  71 #define CONFIG_BOOTP_GATEWAY
  72 #define CONFIG_BOOTP_HOSTNAME
  73 #define CONFIG_BOOTP_BOOTPATH
  74 #define CONFIG_BOOTP_BOOTFILESIZE
  75
  76
  77 /*
  78  * Command line configuration.
  79  */
  80 #include <config_cmd_default.h>
  81
  82
  83 /*
  84  * Miscellaneous configurable options
  85  */
  86 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  87 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
  88 #if defined(CONFIG_CMD_KGDB)
  89 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  90 #else
  91 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  92 #endif
  93 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  94 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  95 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  96
  97 #define CONFIG_SYS_MEMTEST_START        0x00400000      /* memtest works on     */
  98 #define CONFIG_SYS_MEMTEST_END          0x00C00000      /* 4 ... 12 MB in DRAM  */
  99
 100 #define CONFIG_SYS_RESET_ADDRESS        0x09900000
 101
 102 #define CONFIG_SYS_LOAD_ADDR            0x400000        /* default load address */
 103
 104 #define CONFIG_SYS_HZ                   1000            /* decrementer freq: 1 ms ticks */
 105
 106 /*
 107  * Low Level Configuration Settings
 108  * (address mappings, register initial values, etc.)
 109  * You should know what you are doing if you make changes here.
 110  */
 111 /*-----------------------------------------------------------------------
 112  * Internal Memory Mapped Register
 113  */
 114 #define CONFIG_SYS_IMMR         0xFA200000
 115
 116 /*-----------------------------------------------------------------------
 117  * Definitions for initial stack pointer and data area (in DPRAM)
 118  */
 119 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 120 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 121 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 122 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 123
 124 /*-----------------------------------------------------------------------
 125  * Start addresses for the final memory configuration
 126  * (Set up by the startup code)
 127  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 128  */
 129 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 130 #define CONFIG_SYS_FLASH_BASE           0xFFC00000
 131 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 132 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 133 #ifdef CONFIG_BZIP2
 134 #define CONFIG_SYS_MALLOC_LEN           (4096 << 10)    /* Reserve ~4 MB for malloc()   */
 135 #else
 136 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 KB for malloc()  */
 137 #endif /* CONFIG_BZIP2 */
 138
 139 /*
 140  * For booting Linux, the board info and command line data
 141  * have to be in the first 8 MB of memory, since this is
 142  * the maximum mapped by the Linux kernel during initialization.
 143  */
 144 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 145
 146 /*-----------------------------------------------------------------------
 147  * FLASH organization
 148  */
 149 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 150 #define CONFIG_SYS_MAX_FLASH_SECT       19      /* max number of sectors on one chip    */
 151
 152 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 153 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 154
 155 #define CONFIG_SYS_DIRECT_FLASH_TFTP
 156
 157 #define CONFIG_ENV_IS_IN_FLASH  1
 158 #define CONFIG_ENV_SECT_SIZE    0x40000 /* We use one complete sector           */
 159 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 160
 161 #define CONFIG_ENV_OVERWRITE
 162
 163 /*-----------------------------------------------------------------------
 164  * Cache Configuration
 165  */
 166 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 167 #if defined(CONFIG_CMD_KGDB)
 168 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 169 #endif
 170
 171 /*-----------------------------------------------------------------------
 172  * SYPCR - System Protection Control                            11-9
 173  * SYPCR can only be written once after reset!
 174  *-----------------------------------------------------------------------
 175  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 176  */
 177 #if defined(CONFIG_WATCHDOG)
 178 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 179                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 180 #else
 181 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 182 #endif
 183
 184 /*-----------------------------------------------------------------------
 185  * SIUMCR - SIU Module Configuration                            11-6
 186  *-----------------------------------------------------------------------
 187  * PCMCIA config., multi-function pin tri-state
 188  */
 189 #define CONFIG_SYS_SIUMCR       (SIUMCR_MLRC10)
 190
 191 /*-----------------------------------------------------------------------
 192  * TBSCR - Time Base Status and Control                         11-26
 193  *-----------------------------------------------------------------------
 194  * Clear Reference Interrupt Status, Timebase freezing enabled
 195  */
 196 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
 197
 198 /*-----------------------------------------------------------------------
 199  * RTCSC - Real-Time Clock Status and Control Register          11-27
 200  *-----------------------------------------------------------------------
 201  */
 202 /*%%%#define CONFIG_SYS_RTCSC   (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
 203 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_RTE)
 204
 205 /*-----------------------------------------------------------------------
 206  * PISCR - Periodic Interrupt Status and Control                11-31
 207  *-----------------------------------------------------------------------
 208  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 209  */
 210 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
 211
 212 /*-----------------------------------------------------------------------
 213  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 214  *-----------------------------------------------------------------------
 215  * Reset PLL lock status sticky bit, timer expired status bit and timer
 216  * interrupt status bit
 217  *
 218  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 219  */
 220 /* up to 50 MHz we use a 1:1 clock */
 221 #define CONFIG_SYS_PLPRCR       ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
 222
 223 /*-----------------------------------------------------------------------
 224  * SCCR - System Clock and reset Control Register               15-27
 225  *-----------------------------------------------------------------------
 226  * Set clock output, timebase and RTC source and divider,
 227  * power management and some other internal clocks
 228  */
 229 #define SCCR_MASK       SCCR_EBDF00
 230 /* up to 50 MHz we use a 1:1 clock */
 231 #define CONFIG_SYS_SCCR (SCCR_COM11 | SCCR_TBS)
 232
 233 /*-----------------------------------------------------------------------
 234  * PCMCIA stuff
 235  *-----------------------------------------------------------------------
 236  *
 237  */
 238 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 239 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 240 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 241 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 242 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 243 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 244 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 245 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 246
 247 /*-----------------------------------------------------------------------
 248  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 249  *-----------------------------------------------------------------------
 250  */
 251
 252 #define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 253 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 254
 255 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 256 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 257 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 258
 259 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 260 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 261
 262 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 263
 264 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 265
 266 /* Offset for data I/O                  */
 267 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 268
 269 /* Offset for normal register accesses  */
 270 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 271
 272 /* Offset for alternate registers       */
 273 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 274
 275 /*-----------------------------------------------------------------------
 276  *
 277  *-----------------------------------------------------------------------
 278  *
 279  */
 280 /*#define       CONFIG_SYS_DER  0x2002000F*/
 281 #define CONFIG_SYS_DER  0
 282
 283 /*
 284  * Init Memory Controller:
 285  *
 286  * BR0 and OR0 (FLASH)
 287  */
 288
 289 #define FLASH_BASE_PRELIM       0xFE000000      /* FLASH base */
 290 #define CONFIG_SYS_PRELIM_OR_AM 0xFE000000      /* OR addr mask */
 291
 292 /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
 293 #define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
 294
 295 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 296 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
 297
 298 /*
 299  * BR1 and OR1 (SDRAM)
 300  *
 301  */
 302 #define SDRAM_BASE_PRELIM       0x00000000      /* SDRAM base   */
 303 #define SDRAM_MAX_SIZE          0x01000000      /* max 16 MB */
 304
 305 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 306 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000E00
 307
 308 #define CONFIG_SYS_OR1_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 309 #define CONFIG_SYS_BR1_PRELIM   ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 310
 311 /* RPXLITE mem setting */
 312 #define CONFIG_SYS_BR3_PRELIM   0xFA400001              /* BCSR */
 313 #define CONFIG_SYS_OR3_PRELIM   0xFFFF8910
 314 #define CONFIG_SYS_BR4_PRELIM   0xFA000401              /* NVRAM&SRAM */
 315 #define CONFIG_SYS_OR4_PRELIM   0xFFFE0970
 316
 317 /*
 318  * Memory Periodic Timer Prescaler
 319  */
 320
 321 /* periodic timer for refresh */
 322 #define CONFIG_SYS_MAMR_PTA     58
 323
 324 /*
 325  * Refresh clock Prescalar
 326  */
 327 #define CONFIG_SYS_MPTPR        MPTPR_PTP_DIV8
 328
 329 /*
 330  * MAMR settings for SDRAM
 331  */
 332
 333 /* 10 column SDRAM */
 334 #define CONFIG_SYS_MAMR_10COL   ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 335                          MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 |   \
 336                          MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
 337
 338 /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
 339 /* Configuration variable added by yooth. */
 340 /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
 341
 342 /*
 343  * BCSRx
 344  *
 345  * Board Status and Control Registers
 346  *
 347  */
 348
 349 #define BCSR0 0xFA400000
 350 #define BCSR1 0xFA400001
 351 #define BCSR2 0xFA400002
 352 #define BCSR3 0xFA400003
 353
 354 #define BCSR0_ENMONXCVR 0x01    /* Monitor XVCR Control */
 355 #define BCSR0_ENNVRAM   0x02    /* CS4# Control */
 356 #define BCSR0_LED5      0x04    /* LED5 control 0='on' 1='off' */
 357 #define BCSR0_LED4      0x08    /* LED4 control 0='on' 1='off' */
 358 #define BCSR0_FULLDPLX  0x10    /* Ethernet XCVR Control */
 359 #define BCSR0_COLTEST   0x20
 360 #define BCSR0_ETHLPBK   0x40
 361 #define BCSR0_ETHEN     0x80
 362
 363 #define BCSR1_PCVCTL7   0x01    /* PC Slot B Control */
 364 #define BCSR1_PCVCTL6   0x02
 365 #define BCSR1_PCVCTL5   0x04
 366 #define BCSR1_PCVCTL4   0x08
 367 #define BCSR1_IPB5SEL   0x10
 368
 369 #define BCSR2_ENPA5HDR  0x08    /* USB Control */
 370 #define BCSR2_ENUSBCLK  0x10
 371 #define BCSR2_USBPWREN  0x20
 372 #define BCSR2_USBSPD    0x40
 373 #define BCSR2_USBSUSP   0x80
 374
 375 #define BCSR3_BWRTC     0x01    /* Real Time Clock Battery */
 376 #define BCSR3_BWNVR     0x02    /* NVRAM Battery */
 377 #define BCSR3_RDY_BSY   0x04    /* Flash Operation */
 378 #define BCSR3_RPXL      0x08    /* Reserved (reads back '1') */
 379 #define BCSR3_D27       0x10    /* Dip Switch settings */
 380 #define BCSR3_D26       0x20
 381 #define BCSR3_D25       0x40
 382 #define BCSR3_D24       0x80
 383
 384 #endif  /* __CONFIG_H */