include/configs/RPXlite.h

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
  25  * U-Boot port on RPXlite board
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 #define RPXLite_50MHz
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37
  38 #undef CONFIG_MPC860
  39 #define CONFIG_MPC850           1       /* This is a MPC850 CPU         */
  40 #define CONFIG_RPXLITE          1
  41
  42 #define CONFIG_SYS_TEXT_BASE    0xfff00000
  43
  44 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  45 #undef  CONFIG_8xx_CONS_SMC2
  46 #undef  CONFIG_8xx_CONS_NONE
  47 #define CONFIG_BAUDRATE         9600    /* console baudrate = 9600bps   */
  48 #if 0
  49 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  50 #else
  51 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  52 #endif
  53
  54 #undef  CONFIG_BOOTARGS
  55 #define CONFIG_BOOTCOMMAND                                                      \
  56         "bootp; "                                                               \
  57         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
  58         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
  59         "bootm"
  60
  61 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  62 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  63
  64 #define CONFIG_BZIP2            /* Include support for bzip2 compressed images  */
  65
  66 /* enable I2C and select the hardware/software driver */
  67 #define CONFIG_SYS_I2C
  68 #define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
  69 #define CONFIG_SYS_I2C_SOFT_SPEED       40000   /* 40 kHz is supposed to work */
  70 #define CONFIG_SYS_I2C_SOFT_SLAVE       0xFE
  71 /* Software (bit-bang) I2C driver configuration */
  72 #define PB_SCL          0x00000020      /* PB 26 */
  73 #define PB_SDA          0x00000010      /* PB 27 */
  74
  75 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
  76 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
  77 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
  78 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
  79 #define I2C_SDA(bit)    if (bit) \
  80                                 immr->im_cpm.cp_pbdat |=  PB_SDA; \
  81                         else \
  82                                 immr->im_cpm.cp_pbdat &= ~PB_SDA
  83 #define I2C_SCL(bit)    if (bit) \
  84                                 immr->im_cpm.cp_pbdat |=  PB_SCL; \
  85                         else \
  86                                 immr->im_cpm.cp_pbdat &= ~PB_SCL
  87 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
  88
  89 /* M41T11 Serial Access Timekeeper(R) SRAM */
  90 #define CONFIG_RTC_M41T11 1
  91 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  92 /* play along with the linux driver */
  93 #define CONFIG_SYS_M41T11_BASE_YEAR 1900
  94
  95 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  96
  97 /*
  98  * BOOTP options
  99  */
 100 #define CONFIG_BOOTP_SUBNETMASK
 101 #define CONFIG_BOOTP_GATEWAY
 102 #define CONFIG_BOOTP_HOSTNAME
 103 #define CONFIG_BOOTP_BOOTPATH
 104 #define CONFIG_BOOTP_BOOTFILESIZE
 105
 106
 107 /*
 108  * Command line configuration.
 109  */
 110 #include <config_cmd_default.h>
 111
 112
 113 /*
 114  * Miscellaneous configurable options
 115  */
 116 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 117 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 118 #if defined(CONFIG_CMD_KGDB)
 119 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 120 #else
 121 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 122 #endif
 123 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 124 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 125 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 126
 127 #define CONFIG_SYS_MEMTEST_START        0x00400000      /* memtest works on     */
 128 #define CONFIG_SYS_MEMTEST_END          0x00C00000      /* 4 ... 12 MB in DRAM  */
 129
 130 #define CONFIG_SYS_RESET_ADDRESS        0x09900000
 131
 132 #define CONFIG_SYS_LOAD_ADDR            0x400000        /* default load address */
 133
 134 #define CONFIG_SYS_HZ                   1000            /* decrementer freq: 1 ms ticks */
 135
 136 /*
 137  * Low Level Configuration Settings
 138  * (address mappings, register initial values, etc.)
 139  * You should know what you are doing if you make changes here.
 140  */
 141 /*-----------------------------------------------------------------------
 142  * Internal Memory Mapped Register
 143  */
 144 #define CONFIG_SYS_IMMR         0xFA200000
 145
 146 /*-----------------------------------------------------------------------
 147  * Definitions for initial stack pointer and data area (in DPRAM)
 148  */
 149 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 150 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 151 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 152 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 153
 154 /*-----------------------------------------------------------------------
 155  * Start addresses for the final memory configuration
 156  * (Set up by the startup code)
 157  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 158  */
 159 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 160 #define CONFIG_SYS_FLASH_BASE           0xFFC00000
 161 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 162 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 163 #ifdef CONFIG_BZIP2
 164 #define CONFIG_SYS_MALLOC_LEN           (4096 << 10)    /* Reserve ~4 MB for malloc()   */
 165 #else
 166 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 KB for malloc()  */
 167 #endif /* CONFIG_BZIP2 */
 168
 169 /*
 170  * For booting Linux, the board info and command line data
 171  * have to be in the first 8 MB of memory, since this is
 172  * the maximum mapped by the Linux kernel during initialization.
 173  */
 174 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 175
 176 /*-----------------------------------------------------------------------
 177  * FLASH organization
 178  */
 179 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 180 #define CONFIG_SYS_MAX_FLASH_SECT       19      /* max number of sectors on one chip    */
 181
 182 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 183 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 184
 185 #define CONFIG_SYS_DIRECT_FLASH_TFTP
 186
 187 #define CONFIG_ENV_IS_IN_FLASH  1
 188 #define CONFIG_ENV_SECT_SIZE    0x40000 /* We use one complete sector           */
 189 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 190
 191 #define CONFIG_ENV_OVERWRITE
 192
 193 /*-----------------------------------------------------------------------
 194  * Cache Configuration
 195  */
 196 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 197 #if defined(CONFIG_CMD_KGDB)
 198 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 199 #endif
 200
 201 /*-----------------------------------------------------------------------
 202  * SYPCR - System Protection Control                            11-9
 203  * SYPCR can only be written once after reset!
 204  *-----------------------------------------------------------------------
 205  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 206  */
 207 #if defined(CONFIG_WATCHDOG)
 208 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 209                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 210 #else
 211 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 212 #endif
 213
 214 /*-----------------------------------------------------------------------
 215  * SIUMCR - SIU Module Configuration                            11-6
 216  *-----------------------------------------------------------------------
 217  * PCMCIA config., multi-function pin tri-state
 218  */
 219 #define CONFIG_SYS_SIUMCR       (SIUMCR_MLRC10)
 220
 221 /*-----------------------------------------------------------------------
 222  * TBSCR - Time Base Status and Control                         11-26
 223  *-----------------------------------------------------------------------
 224  * Clear Reference Interrupt Status, Timebase freezing enabled
 225  */
 226 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
 227
 228 /*-----------------------------------------------------------------------
 229  * RTCSC - Real-Time Clock Status and Control Register          11-27
 230  *-----------------------------------------------------------------------
 231  */
 232 /*%%%#define CONFIG_SYS_RTCSC   (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
 233 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_RTE)
 234
 235 /*-----------------------------------------------------------------------
 236  * PISCR - Periodic Interrupt Status and Control                11-31
 237  *-----------------------------------------------------------------------
 238  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 239  */
 240 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
 241
 242 /*-----------------------------------------------------------------------
 243  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 244  *-----------------------------------------------------------------------
 245  * Reset PLL lock status sticky bit, timer expired status bit and timer
 246  * interrupt status bit
 247  *
 248  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 249  */
 250 /* up to 50 MHz we use a 1:1 clock */
 251 #define CONFIG_SYS_PLPRCR       ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
 252
 253 /*-----------------------------------------------------------------------
 254  * SCCR - System Clock and reset Control Register               15-27
 255  *-----------------------------------------------------------------------
 256  * Set clock output, timebase and RTC source and divider,
 257  * power management and some other internal clocks
 258  */
 259 #define SCCR_MASK       SCCR_EBDF00
 260 /* up to 50 MHz we use a 1:1 clock */
 261 #define CONFIG_SYS_SCCR (SCCR_COM11 | SCCR_TBS)
 262
 263 /*-----------------------------------------------------------------------
 264  * PCMCIA stuff
 265  *-----------------------------------------------------------------------
 266  *
 267  */
 268 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 269 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 270 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 271 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 272 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 273 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 274 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 275 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 276
 277 /*-----------------------------------------------------------------------
 278  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 279  *-----------------------------------------------------------------------
 280  */
 281
 282 #define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 283 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 284
 285 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 286 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 287 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 288
 289 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 290 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 291
 292 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 293
 294 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 295
 296 /* Offset for data I/O                  */
 297 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 298
 299 /* Offset for normal register accesses  */
 300 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 301
 302 /* Offset for alternate registers       */
 303 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 304
 305 /*-----------------------------------------------------------------------
 306  *
 307  *-----------------------------------------------------------------------
 308  *
 309  */
 310 /*#define       CONFIG_SYS_DER  0x2002000F*/
 311 #define CONFIG_SYS_DER  0
 312
 313 /*
 314  * Init Memory Controller:
 315  *
 316  * BR0 and OR0 (FLASH)
 317  */
 318
 319 #define FLASH_BASE_PRELIM       0xFE000000      /* FLASH base */
 320 #define CONFIG_SYS_PRELIM_OR_AM 0xFE000000      /* OR addr mask */
 321
 322 /* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
 323 #define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
 324
 325 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 326 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
 327
 328 /*
 329  * BR1 and OR1 (SDRAM)
 330  *
 331  */
 332 #define SDRAM_BASE_PRELIM       0x00000000      /* SDRAM base   */
 333 #define SDRAM_MAX_SIZE          0x01000000      /* max 16 MB */
 334
 335 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 336 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000E00
 337
 338 #define CONFIG_SYS_OR1_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 339 #define CONFIG_SYS_BR1_PRELIM   ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 340
 341 /* RPXLITE mem setting */
 342 #define CONFIG_SYS_BR3_PRELIM   0xFA400001              /* BCSR */
 343 #define CONFIG_SYS_OR3_PRELIM   0xFFFF8910
 344 #define CONFIG_SYS_BR4_PRELIM   0xFA000401              /* NVRAM&SRAM */
 345 #define CONFIG_SYS_OR4_PRELIM   0xFFFE0970
 346
 347 /*
 348  * Memory Periodic Timer Prescaler
 349  */
 350
 351 /* periodic timer for refresh */
 352 #define CONFIG_SYS_MAMR_PTA     58
 353
 354 /*
 355  * Refresh clock Prescalar
 356  */
 357 #define CONFIG_SYS_MPTPR        MPTPR_PTP_DIV8
 358
 359 /*
 360  * MAMR settings for SDRAM
 361  */
 362
 363 /* 10 column SDRAM */
 364 #define CONFIG_SYS_MAMR_10COL   ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 365                          MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 |   \
 366                          MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
 367
 368 /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
 369 /* Configuration variable added by yooth. */
 370 /*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
 371
 372 /*
 373  * BCSRx
 374  *
 375  * Board Status and Control Registers
 376  *
 377  */
 378
 379 #define BCSR0 0xFA400000
 380 #define BCSR1 0xFA400001
 381 #define BCSR2 0xFA400002
 382 #define BCSR3 0xFA400003
 383
 384 #define BCSR0_ENMONXCVR 0x01    /* Monitor XVCR Control */
 385 #define BCSR0_ENNVRAM   0x02    /* CS4# Control */
 386 #define BCSR0_LED5      0x04    /* LED5 control 0='on' 1='off' */
 387 #define BCSR0_LED4      0x08    /* LED4 control 0='on' 1='off' */
 388 #define BCSR0_FULLDPLX  0x10    /* Ethernet XCVR Control */
 389 #define BCSR0_COLTEST   0x20
 390 #define BCSR0_ETHLPBK   0x40
 391 #define BCSR0_ETHEN     0x80
 392
 393 #define BCSR1_PCVCTL7   0x01    /* PC Slot B Control */
 394 #define BCSR1_PCVCTL6   0x02
 395 #define BCSR1_PCVCTL5   0x04
 396 #define BCSR1_PCVCTL4   0x08
 397 #define BCSR1_IPB5SEL   0x10
 398
 399 #define BCSR2_ENPA5HDR  0x08    /* USB Control */
 400 #define BCSR2_ENUSBCLK  0x10
 401 #define BCSR2_USBPWREN  0x20
 402 #define BCSR2_USBSPD    0x40
 403 #define BCSR2_USBSUSP   0x80
 404
 405 #define BCSR3_BWRTC     0x01    /* Real Time Clock Battery */
 406 #define BCSR3_BWNVR     0x02    /* NVRAM Battery */
 407 #define BCSR3_RDY_BSY   0x04    /* Flash Operation */
 408 #define BCSR3_RPXL      0x08    /* Reserved (reads back '1') */
 409 #define BCSR3_D27       0x10    /* Dip Switch settings */
 410 #define BCSR3_D26       0x20
 411 #define BCSR3_D25       0x40
 412 #define BCSR3_D24       0x80
 413
 414 #endif  /* __CONFIG_H */