include/configs/RPXsuper.h

   1 #ifndef __CONFIG_H
   2 #define __CONFIG_H
   3
   4
   5 /*****************************************************************************
   6  *
   7  * These settings must match the way _your_ board is set up
   8  *
   9  *****************************************************************************/
  10 /* for the AY-Revision which does not use the HRCW */
  11 #define CFG_DEFAULT_IMMR        0x00010000
  12
  13 /* What is the oscillator's (UX2) frequency in Hz? */
  14 #define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
  15
  16 /* How is switch S2 set? We really only want the MODCK[1-3] bits, so
  17  * only the 3 least significant bits are important.
  18 */
  19 #define CFG_SBC_S2  0x04
  20
  21 /* What should MODCK_H be? It is dependent on the oscillator
  22  * frequency, MODCK[1-3], and desired CPM and core frequencies.
  23  * Some example values (all frequencies are in MHz):
  24  *
  25  * MODCK_H   MODCK[1-3]  Osc    CPM    Core
  26  * 0x2       0x2         33     133    133
  27  * 0x2       0x4         33     133    200
  28  * 0x5       0x5         66     133    133
  29  * 0x5       0x7         66     133    200
  30  */
  31 #define CFG_SBC_MODCK_H 0x06
  32
  33 #define CFG_SBC_BOOT_LOW 1      /* only for HRCW */
  34 #undef CFG_SBC_BOOT_LOW
  35
  36 /* What should the base address of the main FLASH be and how big is
  37  * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk
  38  * The main FLASH is whichever is connected to *CS0. U-Boot expects
  39  * this to be the SIMM.
  40  */
  41 #define CFG_FLASH0_BASE 0x80000000
  42 #define CFG_FLASH0_SIZE 16
  43
  44 /* What should the base address of the secondary FLASH be and how big
  45  * is it (in Mbytes)? The secondary FLASH is whichever is connected
  46  * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
  47  * want it enabled, don't define these constants.
  48  */
  49 #define CFG_FLASH1_BASE 0
  50 #define CFG_FLASH1_SIZE 0
  51 #undef CFG_FLASH1_BASE
  52 #undef CFG_FLASH1_SIZE
  53
  54 /* What should be the base address of SDRAM DIMM and how big is
  55  * it (in Mbytes)?
  56 */
  57 #define CFG_SDRAM0_BASE 0x00000000
  58 #define CFG_SDRAM0_SIZE 64
  59
  60 /* What should be the base address of SDRAM DIMM and how big is
  61  * it (in Mbytes)?
  62 */
  63 #define CFG_SDRAM1_BASE 0x04000000
  64 #define CFG_SDRAM1_SIZE 32
  65
  66 /* What should be the base address of the LEDs and switch S0?
  67  * If you don't want them enabled, don't define this.
  68  */
  69 #define CFG_LED_BASE 0x00000000
  70
  71 /*
  72  * select serial console configuration
  73  *
  74  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  75  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  76  * for SCC).
  77  *
  78  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  79  * defined elsewhere.
  80  */
  81 #define CONFIG_CONS_ON_SMC          /* define if console on SMC */
  82 #undef  CONFIG_CONS_ON_SCC          /* define if console on SCC */
  83 #undef  CONFIG_CONS_NONE            /* define if console on neither */
  84 #define CONFIG_CONS_INDEX    1      /* which SMC/SCC channel for console */
  85
  86 /*
  87  * select ethernet configuration
  88  *
  89  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  90  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  91  * for FCC)
  92  *
  93  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  94  * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
  95  * from CONFIG_COMMANDS to remove support for networking.
  96  */
  97 #undef  CONFIG_ETHER_ON_SCC           /* define if ethernet on SCC    */
  98 #define CONFIG_ETHER_ON_FCC           /* define if ethernet on FCC    */
  99 #undef  CONFIG_ETHER_NONE             /* define if ethernet on neither */
 100 #define CONFIG_ETHER_INDEX      3     /* which SCC/FCC channel for ethernet */
 101
 102 #if ( CONFIG_ETHER_INDEX == 3 )
 103
 104 /*
 105  * - Rx-CLK is CLK15
 106  * - Tx-CLK is CLK16
 107  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 108  * - Enable Half Duplex in FSMR
 109  */
 110 # define CFG_CMXFCR_MASK        (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
 111 # define CFG_CMXFCR_VALUE       (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
 112 # define CFG_CPMFCR_RAMTYPE     0
 113 /*#define CFG_FCC_PSMR          (FCC_PSMR_FDE|FCC_PSMR_LPB) */
 114 # define CFG_FCC_PSMR           0
 115
 116 #else /* CONFIG_ETHER_INDEX */
 117 # error "on RPX Super ethernet must be FCC3"
 118 #endif /* CONFIG_ETHER_INDEX */
 119
 120 #define CONFIG_HARD_I2C         1       /* I2C with hardware support    */
 121 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 122 #define CFG_I2C_SLAVE           0x7F
 123
 124
 125 /* Define this to reserve an entire FLASH sector (256 KB) for
 126  * environment variables. Otherwise, the environment will be
 127  * put in the same sector as U-Boot, and changing variables
 128  * will erase U-Boot temporarily
 129  */
 130 #define CFG_ENV_IN_OWN_SECT
 131
 132 /* Define to allow the user to overwrite serial and ethaddr */
 133 #define CONFIG_ENV_OVERWRITE
 134
 135 /* What should the console's baud rate be? */
 136 #define CONFIG_BAUDRATE         115200
 137
 138 /* Ethernet MAC address */
 139 #define CONFIG_ETHADDR          08:00:22:50:70:63
 140
 141 #define CONFIG_IPADDR           192.168.1.99
 142 #define CONFIG_SERVERIP         192.168.1.3
 143
 144 /* Set to a positive value to delay for running BOOTCOMMAND */
 145 #define CONFIG_BOOTDELAY        -1
 146
 147 /* undef this to save memory */
 148 #define CFG_LONGHELP
 149
 150 /* Monitor Command Prompt       */
 151 #define CFG_PROMPT              "=> "
 152
 153 /* What U-Boot subsytems do you want enabled? */
 154 #define CONFIG_COMMANDS         ( CONFIG_CMD_DFL | \
 155                                   CFG_CMD_IMMAP  | \
 156                                   CFG_CMD_ASKENV | \
 157                                   CFG_CMD_ECHO   | \
 158                                   CFG_CMD_I2C    | \
 159                                   CFG_CMD_REGINFO & \
 160                                  ~CFG_CMD_KGDB )
 161
 162 /* Where do the internal registers live? */
 163 #define CFG_IMMR               0xF0000000
 164
 165 /* Where do the on board registers (CS4) live? */
 166 #define CFG_REGS_BASE          0xFA000000
 167
 168 /*****************************************************************************
 169  *
 170  * You should not have to modify any of the following settings
 171  *
 172  *****************************************************************************/
 173
 174 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
 175 #define CONFIG_RPXSUPER         1       /* on an Embedded Planet RPX Super Board  */
 176
 177 #define CONFIG_BOARD_PRE_INIT   1       /* Call board_pre_init  */
 178
 179 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 180 #include <cmd_confdefs.h>
 181
 182 /*
 183  * Miscellaneous configurable options
 184  */
 185 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 186 #  define CFG_CBSIZE              1024       /* Console I/O Buffer Size      */
 187 #else
 188 #  define CFG_CBSIZE              256        /* Console I/O Buffer Size      */
 189 #endif
 190
 191 /* Print Buffer Size */
 192 #define CFG_PBSIZE        (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
 193
 194 #define CFG_MAXARGS       8            /* max number of command args   */
 195
 196 #define CFG_BARGSIZE      CFG_CBSIZE   /* Boot Argument Buffer Size    */
 197
 198 #define CFG_MEMTEST_START 0x04000000   /* memtest works on  */
 199 #define CFG_MEMTEST_END   0x06000000   /* 64-96 MB in SDRAM */
 200
 201 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
 202
 203 #define CFG_LOAD_ADDR     0x100000     /* default load address */
 204 #define CFG_HZ            1000         /* decrementer freq: 1 ms ticks */
 205
 206 /* valid baudrates */
 207 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 208
 209 /*
 210  * Low Level Configuration Settings
 211  * (address mappings, register initial values, etc.)
 212  * You should know what you are doing if you make changes here.
 213  */
 214
 215 #define CFG_FLASH_BASE    CFG_FLASH0_BASE
 216 #define CFG_SDRAM_BASE    CFG_SDRAM0_BASE
 217
 218 /*-----------------------------------------------------------------------
 219  * Hard Reset Configuration Words
 220  */
 221 #if defined(CFG_SBC_BOOT_LOW)
 222 #  define  CFG_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
 223 #else
 224 #  define  CFG_SBC_HRCW_BOOT_FLAGS  (0)
 225 #endif /* defined(CFG_SBC_BOOT_LOW) */
 226
 227 /* get the HRCW ISB field from CFG_IMMR */
 228 #define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\
 229                             ((CFG_IMMR & 0x01000000) >> 7)  |\
 230                             ((CFG_IMMR & 0x00100000) >> 4) )
 231
 232 #define CFG_HRCW_MASTER (HRCW_BPS11                           |\
 233                          HRCW_DPPC11                          |\
 234                          CFG_SBC_HRCW_IMMR                    |\
 235                          HRCW_MMR00                           |\
 236                          HRCW_LBPC11                          |\
 237                          HRCW_APPC10                          |\
 238                          HRCW_CS10PC00                        |\
 239                          (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) |\
 240                          CFG_SBC_HRCW_BOOT_FLAGS)
 241
 242 /* no slaves */
 243 #define CFG_HRCW_SLAVE1 0
 244 #define CFG_HRCW_SLAVE2 0
 245 #define CFG_HRCW_SLAVE3 0
 246 #define CFG_HRCW_SLAVE4 0
 247 #define CFG_HRCW_SLAVE5 0
 248 #define CFG_HRCW_SLAVE6 0
 249 #define CFG_HRCW_SLAVE7 0
 250
 251 /*-----------------------------------------------------------------------
 252  * Definitions for initial stack pointer and data area (in DPRAM)
 253  */
 254 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 255 #define CFG_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
 256 #define CFG_GBL_DATA_SIZE      128     /* bytes reserved for initial data */
 257 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 258 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 259
 260 /*-----------------------------------------------------------------------
 261  * Start addresses for the final memory configuration
 262  * (Set up by the startup code)
 263  * Please note that CFG_SDRAM_BASE _must_ start at 0
 264  * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
 265  */
 266 #define CFG_MONITOR_BASE        (CFG_FLASH0_BASE + 0x00F00000)
 267
 268 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 269 #  define CFG_RAMBOOT
 270 #endif
 271
 272 #define CFG_MONITOR_LEN      (256 << 10)     /* Reserve 256 kB for Monitor   */
 273 #define CFG_MALLOC_LEN       (128 << 10)     /* Reserve 128 kB for malloc()  */
 274
 275 /*
 276  * For booting Linux, the board info and command line data
 277  * have to be in the first 8 MB of memory, since this is
 278  * the maximum mapped by the Linux kernel during initialization.
 279  */
 280 #define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 281
 282 /*-----------------------------------------------------------------------
 283  * FLASH and environment organization
 284  */
 285 #define CFG_MAX_FLASH_BANKS   1       /* max number of memory banks         */
 286 #define CFG_MAX_FLASH_SECT    71      /* max number of sectors on one chip  */
 287
 288 #define CFG_FLASH_ERASE_TOUT  8000    /* Timeout for Flash Erase (in ms)    */
 289 #define CFG_FLASH_WRITE_TOUT  1       /* Timeout for Flash Write (in ms)    */
 290
 291 #ifndef CFG_RAMBOOT
 292 #  define CFG_ENV_IS_IN_FLASH  1
 293
 294 #  ifdef CFG_ENV_IN_OWN_SECT
 295 #    define CFG_ENV_ADDR       (CFG_MONITOR_BASE + 0x40000)
 296 #    define CFG_ENV_SECT_SIZE  0x40000
 297 #  else
 298 #    define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
 299 #    define CFG_ENV_SIZE       0x1000  /* Total Size of Environment Sector */
 300 #    define CFG_ENV_SECT_SIZE  0x10000 /* see README - env sect real size */
 301 #  endif /* CFG_ENV_IN_OWN_SECT */
 302 #else
 303 #  define CFG_ENV_IS_IN_NVRAM  1
 304 #  define CFG_ENV_ADDR         (CFG_MONITOR_BASE - 0x1000)
 305 #  define CFG_ENV_SIZE         0x200
 306 #endif /* CFG_RAMBOOT */
 307
 308 /*-----------------------------------------------------------------------
 309  * Cache Configuration
 310  */
 311 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU */
 312
 313 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 314 #  define CFG_CACHELINE_SHIFT     5     /* log base 2 of the above value */
 315 #endif
 316
 317 /*-----------------------------------------------------------------------
 318  * HIDx - Hardware Implementation-dependent Registers                    2-11
 319  *-----------------------------------------------------------------------
 320  * HID0 also contains cache control - initially enable both caches and
 321  * invalidate contents, then the final state leaves only the instruction
 322  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 323  * but Soft reset does not.
 324  *
 325  * HID1 has only read-only information - nothing to set.
 326  */
 327 #define CFG_HID0_INIT   (/*HID0_ICE  |*/\
 328                          /*HID0_DCE  |*/\
 329                          HID0_ICFI |\
 330                          HID0_DCI  |\
 331                          HID0_IFEM |\
 332                          HID0_ABE)
 333
 334 #define CFG_HID0_FINAL  (/*HID0_ICE  |*/\
 335                          HID0_IFEM |\
 336                          HID0_ABE  |\
 337                          HID0_EMCP)
 338 #define CFG_HID2        0
 339
 340 /*-----------------------------------------------------------------------
 341  * RMR - Reset Mode Register
 342  *-----------------------------------------------------------------------
 343  */
 344 #define CFG_RMR         0
 345
 346 /*-----------------------------------------------------------------------
 347  * BCR - Bus Configuration                                       4-25
 348  *-----------------------------------------------------------------------
 349  */
 350 #define CFG_BCR         (BCR_EBM   |\
 351                          BCR_PLDP  |\
 352                          BCR_EAV   |\
 353                          BCR_NPQM0)
 354
 355 /*-----------------------------------------------------------------------
 356  * SIUMCR - SIU Module Configuration                             4-31
 357  *-----------------------------------------------------------------------
 358  */
 359
 360 #define CFG_SIUMCR      (SIUMCR_L2CPC01 |\
 361                          SIUMCR_APPC10  |\
 362                          SIUMCR_CS10PC01)
 363
 364
 365 /*-----------------------------------------------------------------------
 366  * SYPCR - System Protection Control                            11-9
 367  * SYPCR can only be written once after reset!
 368  *-----------------------------------------------------------------------
 369  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 370  */
 371 #define CFG_SYPCR       (SYPCR_SWTC |\
 372                          SYPCR_BMT  |\
 373                          SYPCR_PBME |\
 374                          SYPCR_LBME |\
 375                          SYPCR_SWRI |\
 376                          SYPCR_SWP)
 377
 378 /*-----------------------------------------------------------------------
 379  * TMCNTSC - Time Counter Status and Control                     4-40
 380  *-----------------------------------------------------------------------
 381  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 382  * and enable Time Counter
 383  */
 384 #define CFG_TMCNTSC     (TMCNTSC_SEC |\
 385                          TMCNTSC_ALR |\
 386                          TMCNTSC_TCF |\
 387                          TMCNTSC_TCE)
 388
 389 /*-----------------------------------------------------------------------
 390  * PISCR - Periodic Interrupt Status and Control                 4-42
 391  *-----------------------------------------------------------------------
 392  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 393  * Periodic timer
 394  */
 395 #define CFG_PISCR       (PISCR_PS  |\
 396                          PISCR_PTF |\
 397                          PISCR_PTE)
 398
 399 /*-----------------------------------------------------------------------
 400  * SCCR - System Clock Control                                   9-8
 401  *-----------------------------------------------------------------------
 402  */
 403 #define CFG_SCCR        (SCCR_DFBRG01)
 404
 405 /*-----------------------------------------------------------------------
 406  * RCCR - RISC Controller Configuration                         13-7
 407  *-----------------------------------------------------------------------
 408  */
 409 #define CFG_RCCR        0
 410
 411 /*
 412  * Init Memory Controller:
 413  *
 414  * Bank Bus     Machine PortSz  Device
 415  * ---- ---     ------- ------  ------
 416  *  0   60x     GPCM    64 bit  FLASH (BGA - 16MB AMD AM29DL323DB90)
 417  *  1   60x     SDRAM   64 bit  SDRAM (BGA - 64MB Hitachi HM5225325FBP-B60)
 418  *  2   Local   SDRAM   32 bit  SDRAM (BGA - 32MB Hitachi HM5225325FBP-B60)
 419  *  3   unused
 420  *  4   60x     GPCM     8 bit  Board Regs, LEDs, switches
 421  *  5   unused
 422  *  6   unused
 423  *  7   unused
 424  *  8   PCMCIA
 425  *  9   unused
 426  * 10   unused
 427  * 11   unused
 428 */
 429
 430 /* Bank 0 - FLASH
 431  *
 432  */
 433 #define CFG_BR0_PRELIM  ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
 434                          BRx_PS_64                      |\
 435                          BRx_DECC_NONE                  |\
 436                          BRx_MS_GPCM_P                  |\
 437                          BRx_V)
 438
 439 #define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH0_SIZE)     |\
 440                          ORxG_CSNT                      |\
 441                          ORxG_ACS_DIV1                  |\
 442                          ORxG_SCY_6_CLK                 |\
 443                          ORxG_EHTR)
 444
 445 /* Bank 1 - SDRAM
 446  *
 447  */
 448 #define CFG_BR1_PRELIM  ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
 449                          BRx_PS_64                      |\
 450                          BRx_MS_SDRAM_P                 |\
 451                          BRx_V)
 452
 453 #define CFG_OR1_PRELIM  (MEG_TO_AM(CFG_SDRAM0_SIZE)     |\
 454                          ORxS_BPD_4                     |\
 455                          ORxS_ROWST_PBI0_A8             |\
 456                          ORxS_NUMR_12                   |\
 457                          ORxS_IBID)
 458
 459 #define CFG_PSDMR       0x014DA412
 460 #define CFG_PSRT        0x79
 461
 462
 463 /* Bank 2 - SDRAM
 464  *
 465  */
 466 #define CFG_BR2_PRELIM  ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
 467                          BRx_PS_32                      |\
 468                          BRx_MS_SDRAM_L                 |\
 469                          BRx_V)
 470
 471 #define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM1_SIZE)     |\
 472                          ORxS_BPD_4                     |\
 473                          ORxS_ROWST_PBI0_A9             |\
 474                          ORxS_NUMR_12)
 475
 476 #define CFG_LSDMR       0x0169A512
 477 #define CFG_LSRT        0x79
 478
 479 #define CFG_MPTPR       (0x0800 & MPTPR_PTP_MSK)
 480
 481 /* Bank 4 - On board registers
 482  *
 483  */
 484 #define CFG_BR4_PRELIM   ((CFG_REGS_BASE & BRx_BA_MSK)  |\
 485                            BRx_PS_8                     |\
 486                            BRx_MS_GPCM_P                |\
 487                            BRx_V)
 488
 489 #define CFG_OR4_PRELIM    (ORxG_AM_MSK                 |\
 490                            ORxG_CSNT                   |\
 491                            ORxG_ACS_DIV1               |\
 492                            ORxG_SCY_5_CLK              |\
 493                            ORxG_TRLX)
 494
 495 /*
 496  * Internal Definitions
 497  *
 498  * Boot Flags
 499  */
 500 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH  */
 501 #define BOOTFLAG_WARM   0x02    /* Software reboot                   */
 502
 503 #endif  /* __CONFIG_H */