include/configs/RPXsuper.h

   1 #ifndef __CONFIG_H
   2 #define __CONFIG_H
   3
   4 #define CONFIG_SYS_TEXT_BASE    0x80F00000
   5
   6 /*****************************************************************************
   7  *
   8  * These settings must match the way _your_ board is set up
   9  *
  10  *****************************************************************************/
  11 /* for the AY-Revision which does not use the HRCW */
  12 #define CONFIG_SYS_DEFAULT_IMMR 0x00010000
  13
  14 /* What is the oscillator's (UX2) frequency in Hz? */
  15 #define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
  16
  17 /* How is switch S2 set? We really only want the MODCK[1-3] bits, so
  18  * only the 3 least significant bits are important.
  19 */
  20 #define CONFIG_SYS_SBC_S2  0x04
  21
  22 /* What should MODCK_H be? It is dependent on the oscillator
  23  * frequency, MODCK[1-3], and desired CPM and core frequencies.
  24  * Some example values (all frequencies are in MHz):
  25  *
  26  * MODCK_H   MODCK[1-3]  Osc    CPM    Core
  27  * 0x2       0x2         33     133    133
  28  * 0x2       0x4         33     133    200
  29  * 0x5       0x5         66     133    133
  30  * 0x5       0x7         66     133    200
  31  */
  32 #define CONFIG_SYS_SBC_MODCK_H 0x06
  33
  34 #define CONFIG_SYS_SBC_BOOT_LOW 1       /* only for HRCW */
  35 #undef CONFIG_SYS_SBC_BOOT_LOW
  36
  37 /* What should the base address of the main FLASH be and how big is
  38  * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE.
  39  * The main FLASH is whichever is connected to *CS0. U-Boot expects
  40  * this to be the SIMM.
  41  */
  42 #define CONFIG_SYS_FLASH0_BASE 0x80000000
  43 #define CONFIG_SYS_FLASH0_SIZE 16
  44
  45 /* What should the base address of the secondary FLASH be and how big
  46  * is it (in Mbytes)? The secondary FLASH is whichever is connected
  47  * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
  48  * want it enabled, don't define these constants.
  49  */
  50 #define CONFIG_SYS_FLASH1_BASE 0
  51 #define CONFIG_SYS_FLASH1_SIZE 0
  52 #undef CONFIG_SYS_FLASH1_BASE
  53 #undef CONFIG_SYS_FLASH1_SIZE
  54
  55 /* What should be the base address of SDRAM DIMM and how big is
  56  * it (in Mbytes)?
  57 */
  58 #define CONFIG_SYS_SDRAM0_BASE 0x00000000
  59 #define CONFIG_SYS_SDRAM0_SIZE 64
  60
  61 /* What should be the base address of SDRAM DIMM and how big is
  62  * it (in Mbytes)?
  63 */
  64 #define CONFIG_SYS_SDRAM1_BASE 0x04000000
  65 #define CONFIG_SYS_SDRAM1_SIZE 32
  66
  67 /* What should be the base address of the LEDs and switch S0?
  68  * If you don't want them enabled, don't define this.
  69  */
  70 #define CONFIG_SYS_LED_BASE 0x00000000
  71
  72 /*
  73  * select serial console configuration
  74  *
  75  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  76  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  77  * for SCC).
  78  *
  79  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  80  * defined elsewhere.
  81  */
  82 #define CONFIG_CONS_ON_SMC          /* define if console on SMC */
  83 #undef  CONFIG_CONS_ON_SCC          /* define if console on SCC */
  84 #undef  CONFIG_CONS_NONE            /* define if console on neither */
  85 #define CONFIG_CONS_INDEX    1      /* which SMC/SCC channel for console */
  86
  87 /*
  88  * select ethernet configuration
  89  *
  90  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  91  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  92  * for FCC)
  93  *
  94  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  95  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
  96  */
  97 #undef  CONFIG_ETHER_ON_SCC           /* define if ethernet on SCC    */
  98 #define CONFIG_ETHER_ON_FCC           /* define if ethernet on FCC    */
  99 #undef  CONFIG_ETHER_NONE             /* define if ethernet on neither */
 100 #define CONFIG_ETHER_INDEX      3     /* which SCC/FCC channel for ethernet */
 101
 102 #if ( CONFIG_ETHER_INDEX == 3 )
 103
 104 /*
 105  * - Rx-CLK is CLK15
 106  * - Tx-CLK is CLK16
 107  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 108  * - Enable Half Duplex in FSMR
 109  */
 110 # define CONFIG_SYS_CMXFCR_MASK3        (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
 111 # define CONFIG_SYS_CMXFCR_VALUE3       (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
 112 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
 113 /*#define CONFIG_SYS_FCC_PSMR           (FCC_PSMR_FDE|FCC_PSMR_LPB) */
 114 # define CONFIG_SYS_FCC_PSMR            0
 115
 116 #else /* CONFIG_ETHER_INDEX */
 117 # error "on RPX Super ethernet must be FCC3"
 118 #endif /* CONFIG_ETHER_INDEX */
 119
 120 #define CONFIG_HARD_I2C         1       /* I2C with hardware support    */
 121 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address  */
 122 #define CONFIG_SYS_I2C_SLAVE            0x7F
 123
 124
 125 /* Define this to reserve an entire FLASH sector (256 KB) for
 126  * environment variables. Otherwise, the environment will be
 127  * put in the same sector as U-Boot, and changing variables
 128  * will erase U-Boot temporarily
 129  */
 130 #define CONFIG_ENV_IN_OWN_SECT
 131
 132 /* Define to allow the user to overwrite serial and ethaddr */
 133 #define CONFIG_ENV_OVERWRITE
 134
 135 /* What should the console's baud rate be? */
 136 #define CONFIG_BAUDRATE         115200
 137
 138 /* Ethernet MAC address */
 139 #define CONFIG_ETHADDR          08:00:22:50:70:63
 140
 141 #define CONFIG_IPADDR           192.168.1.99
 142 #define CONFIG_SERVERIP         192.168.1.3
 143
 144 /* Set to a positive value to delay for running BOOTCOMMAND */
 145 #define CONFIG_BOOTDELAY        -1
 146
 147 /* undef this to save memory */
 148 #define CONFIG_SYS_LONGHELP
 149
 150 /* Monitor Command Prompt       */
 151 #define CONFIG_SYS_PROMPT              "=> "
 152
 153
 154 /*
 155  * BOOTP options
 156  */
 157 #define CONFIG_BOOTP_BOOTFILESIZE
 158 #define CONFIG_BOOTP_BOOTPATH
 159 #define CONFIG_BOOTP_GATEWAY
 160 #define CONFIG_BOOTP_HOSTNAME
 161
 162
 163 /*
 164  * Command line configuration.
 165  */
 166 #include <config_cmd_default.h>
 167
 168 #define CONFIG_CMD_IMMAP
 169 #define CONFIG_CMD_ASKENV
 170 #define CONFIG_CMD_I2C
 171 #define CONFIG_CMD_REGINFO
 172
 173 #undef CONFIG_CMD_KGDB
 174
 175
 176 /* Where do the internal registers live? */
 177 #define CONFIG_SYS_IMMR               0xF0000000
 178
 179 /* Where do the on board registers (CS4) live? */
 180 #define CONFIG_SYS_REGS_BASE          0xFA000000
 181
 182 /*****************************************************************************
 183  *
 184  * You should not have to modify any of the following settings
 185  *
 186  *****************************************************************************/
 187
 188 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
 189 #define CONFIG_RPXSUPER         1       /* on an Embedded Planet RPX Super Board  */
 190 #define CONFIG_CPM2             1       /* Has a CPM2 */
 191
 192 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
 193 #define CONFIG_RESET_PHY_R      1       /* Call reset_phy()             */
 194
 195 /*
 196  * Miscellaneous configurable options
 197  */
 198 #if defined(CONFIG_CMD_KGDB)
 199 #  define CONFIG_SYS_CBSIZE              1024       /* Console I/O Buffer Size      */
 200 #else
 201 #  define CONFIG_SYS_CBSIZE              256        /* Console I/O Buffer Size      */
 202 #endif
 203
 204 /* Print Buffer Size */
 205 #define CONFIG_SYS_PBSIZE        (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
 206
 207 #define CONFIG_SYS_MAXARGS       8            /* max number of command args   */
 208
 209 #define CONFIG_SYS_BARGSIZE      CONFIG_SYS_CBSIZE   /* Boot Argument Buffer Size    */
 210
 211 #define CONFIG_SYS_MEMTEST_START 0x04000000   /* memtest works on  */
 212 #define CONFIG_SYS_MEMTEST_END   0x06000000   /* 64-96 MB in SDRAM */
 213
 214 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
 215
 216 #define CONFIG_SYS_LOAD_ADDR     0x100000     /* default load address */
 217 #define CONFIG_SYS_HZ            1000         /* decrementer freq: 1 ms ticks */
 218
 219 /*
 220  * Low Level Configuration Settings
 221  * (address mappings, register initial values, etc.)
 222  * You should know what you are doing if you make changes here.
 223  */
 224
 225 #define CONFIG_SYS_FLASH_BASE    CONFIG_SYS_FLASH0_BASE
 226 #define CONFIG_SYS_SDRAM_BASE    CONFIG_SYS_SDRAM0_BASE
 227
 228 /*-----------------------------------------------------------------------
 229  * Hard Reset Configuration Words
 230  */
 231 #if defined(CONFIG_SYS_SBC_BOOT_LOW)
 232 #  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
 233 #else
 234 #  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (0)
 235 #endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
 236
 237 /* get the HRCW ISB field from CONFIG_SYS_IMMR */
 238 #define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) |\
 239                             ((CONFIG_SYS_IMMR & 0x01000000) >> 7)  |\
 240                             ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
 241
 242 #define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11                           |\
 243                          HRCW_DPPC11                          |\
 244                          CONFIG_SYS_SBC_HRCW_IMMR                    |\
 245                          HRCW_MMR00                           |\
 246                          HRCW_LBPC11                          |\
 247                          HRCW_APPC10                          |\
 248                          HRCW_CS10PC00                        |\
 249                          (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) |\
 250                          CONFIG_SYS_SBC_HRCW_BOOT_FLAGS)
 251
 252 /* no slaves */
 253 #define CONFIG_SYS_HRCW_SLAVE1 0
 254 #define CONFIG_SYS_HRCW_SLAVE2 0
 255 #define CONFIG_SYS_HRCW_SLAVE3 0
 256 #define CONFIG_SYS_HRCW_SLAVE4 0
 257 #define CONFIG_SYS_HRCW_SLAVE5 0
 258 #define CONFIG_SYS_HRCW_SLAVE6 0
 259 #define CONFIG_SYS_HRCW_SLAVE7 0
 260
 261 /*-----------------------------------------------------------------------
 262  * Definitions for initial stack pointer and data area (in DPRAM)
 263  */
 264 #define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_SYS_IMMR
 265 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000  /* Size of used area in DPRAM    */
 266 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 267 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 268
 269 /*-----------------------------------------------------------------------
 270  * Start addresses for the final memory configuration
 271  * (Set up by the startup code)
 272  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 273  * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
 274  */
 275 #define CONFIG_SYS_MONITOR_BASE        (CONFIG_SYS_FLASH0_BASE + 0x00F00000)
 276
 277 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 278 #  define CONFIG_SYS_RAMBOOT
 279 #endif
 280
 281 #define CONFIG_SYS_MONITOR_LEN      (256 << 10)     /* Reserve 256 kB for Monitor   */
 282 #define CONFIG_SYS_MALLOC_LEN       (128 << 10)     /* Reserve 128 kB for malloc()  */
 283
 284 /*
 285  * For booting Linux, the board info and command line data
 286  * have to be in the first 8 MB of memory, since this is
 287  * the maximum mapped by the Linux kernel during initialization.
 288  */
 289 #define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 290
 291 /*-----------------------------------------------------------------------
 292  * FLASH and environment organization
 293  */
 294 #define CONFIG_SYS_MAX_FLASH_BANKS   1       /* max number of memory banks         */
 295 #define CONFIG_SYS_MAX_FLASH_SECT    71      /* max number of sectors on one chip  */
 296
 297 #define CONFIG_SYS_FLASH_ERASE_TOUT  8000    /* Timeout for Flash Erase (in ms)    */
 298 #define CONFIG_SYS_FLASH_WRITE_TOUT  1       /* Timeout for Flash Write (in ms)    */
 299
 300 #ifndef CONFIG_SYS_RAMBOOT
 301 #  define CONFIG_ENV_IS_IN_FLASH  1
 302
 303 #  ifdef CONFIG_ENV_IN_OWN_SECT
 304 #    define CONFIG_ENV_ADDR       (CONFIG_SYS_MONITOR_BASE + 0x40000)
 305 #    define CONFIG_ENV_SECT_SIZE  0x40000
 306 #  else
 307 #    define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
 308 #    define CONFIG_ENV_SIZE       0x1000  /* Total Size of Environment Sector */
 309 #    define CONFIG_ENV_SECT_SIZE  0x10000 /* see README - env sect real size */
 310 #  endif /* CONFIG_ENV_IN_OWN_SECT */
 311 #else
 312 #  define CONFIG_ENV_IS_IN_NVRAM  1
 313 #  define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 314 #  define CONFIG_ENV_SIZE         0x200
 315 #endif /* CONFIG_SYS_RAMBOOT */
 316
 317 /*-----------------------------------------------------------------------
 318  * Cache Configuration
 319  */
 320 #define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU */
 321
 322 #if defined(CONFIG_CMD_KGDB)
 323 #  define CONFIG_SYS_CACHELINE_SHIFT     5     /* log base 2 of the above value */
 324 #endif
 325
 326 /*-----------------------------------------------------------------------
 327  * HIDx - Hardware Implementation-dependent Registers                    2-11
 328  *-----------------------------------------------------------------------
 329  * HID0 also contains cache control - initially enable both caches and
 330  * invalidate contents, then the final state leaves only the instruction
 331  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 332  * but Soft reset does not.
 333  *
 334  * HID1 has only read-only information - nothing to set.
 335  */
 336 #define CONFIG_SYS_HID0_INIT   (/*HID0_ICE  |*/\
 337                          /*HID0_DCE  |*/\
 338                          HID0_ICFI |\
 339                          HID0_DCI  |\
 340                          HID0_IFEM |\
 341                          HID0_ABE)
 342
 343 #define CONFIG_SYS_HID0_FINAL  (/*HID0_ICE  |*/\
 344                          HID0_IFEM |\
 345                          HID0_ABE  |\
 346                          HID0_EMCP)
 347 #define CONFIG_SYS_HID2        0
 348
 349 /*-----------------------------------------------------------------------
 350  * RMR - Reset Mode Register
 351  *-----------------------------------------------------------------------
 352  */
 353 #define CONFIG_SYS_RMR         0
 354
 355 /*-----------------------------------------------------------------------
 356  * BCR - Bus Configuration                                       4-25
 357  *-----------------------------------------------------------------------
 358  */
 359 #define CONFIG_SYS_BCR         (BCR_EBM   |\
 360                          BCR_PLDP  |\
 361                          BCR_EAV   |\
 362                          BCR_NPQM0)
 363
 364 /*-----------------------------------------------------------------------
 365  * SIUMCR - SIU Module Configuration                             4-31
 366  *-----------------------------------------------------------------------
 367  */
 368
 369 #define CONFIG_SYS_SIUMCR      (SIUMCR_L2CPC01 |\
 370                          SIUMCR_APPC10  |\
 371                          SIUMCR_CS10PC01)
 372
 373
 374 /*-----------------------------------------------------------------------
 375  * SYPCR - System Protection Control                            11-9
 376  * SYPCR can only be written once after reset!
 377  *-----------------------------------------------------------------------
 378  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 379  */
 380 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC |\
 381                          SYPCR_BMT  |\
 382                          SYPCR_PBME |\
 383                          SYPCR_LBME |\
 384                          SYPCR_SWRI |\
 385                          SYPCR_SWP)
 386
 387 /*-----------------------------------------------------------------------
 388  * TMCNTSC - Time Counter Status and Control                     4-40
 389  *-----------------------------------------------------------------------
 390  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 391  * and enable Time Counter
 392  */
 393 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC |\
 394                          TMCNTSC_ALR |\
 395                          TMCNTSC_TCF |\
 396                          TMCNTSC_TCE)
 397
 398 /*-----------------------------------------------------------------------
 399  * PISCR - Periodic Interrupt Status and Control                 4-42
 400  *-----------------------------------------------------------------------
 401  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 402  * Periodic timer
 403  */
 404 #define CONFIG_SYS_PISCR       (PISCR_PS  |\
 405                          PISCR_PTF |\
 406                          PISCR_PTE)
 407
 408 /*-----------------------------------------------------------------------
 409  * SCCR - System Clock Control                                   9-8
 410  *-----------------------------------------------------------------------
 411  */
 412 #define CONFIG_SYS_SCCR        (SCCR_DFBRG01)
 413
 414 /*-----------------------------------------------------------------------
 415  * RCCR - RISC Controller Configuration                         13-7
 416  *-----------------------------------------------------------------------
 417  */
 418 #define CONFIG_SYS_RCCR        0
 419
 420 /*
 421  * Init Memory Controller:
 422  *
 423  * Bank Bus     Machine PortSz  Device
 424  * ---- ---     ------- ------  ------
 425  *  0   60x     GPCM    64 bit  FLASH (BGA - 16MB AMD AM29DL323DB90)
 426  *  1   60x     SDRAM   64 bit  SDRAM (BGA - 64MB Hitachi HM5225325FBP-B60)
 427  *  2   Local   SDRAM   32 bit  SDRAM (BGA - 32MB Hitachi HM5225325FBP-B60)
 428  *  3   unused
 429  *  4   60x     GPCM     8 bit  Board Regs, LEDs, switches
 430  *  5   unused
 431  *  6   unused
 432  *  7   unused
 433  *  8   PCMCIA
 434  *  9   unused
 435  * 10   unused
 436  * 11   unused
 437 */
 438
 439 /* Bank 0 - FLASH
 440  *
 441  */
 442 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
 443                          BRx_PS_64                      |\
 444                          BRx_DECC_NONE                  |\
 445                          BRx_MS_GPCM_P                  |\
 446                          BRx_V)
 447
 448 #define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE)     |\
 449                          ORxG_CSNT                      |\
 450                          ORxG_ACS_DIV1                  |\
 451                          ORxG_SCY_6_CLK                 |\
 452                          ORxG_EHTR)
 453
 454 /* Bank 1 - SDRAM
 455  *
 456  */
 457 #define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
 458                          BRx_PS_64                      |\
 459                          BRx_MS_SDRAM_P                 |\
 460                          BRx_V)
 461
 462 #define CONFIG_SYS_OR1_PRELIM  (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE)     |\
 463                          ORxS_BPD_4                     |\
 464                          ORxS_ROWST_PBI0_A8             |\
 465                          ORxS_NUMR_12                   |\
 466                          ORxS_IBID)
 467
 468 #define CONFIG_SYS_PSDMR       0x014DA412
 469 #define CONFIG_SYS_PSRT 0x79
 470
 471
 472 /* Bank 2 - SDRAM
 473  *
 474  */
 475 #define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\
 476                          BRx_PS_32                      |\
 477                          BRx_MS_SDRAM_L                 |\
 478                          BRx_V)
 479
 480 #define CONFIG_SYS_OR2_PRELIM  (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE)     |\
 481                          ORxS_BPD_4                     |\
 482                          ORxS_ROWST_PBI0_A9             |\
 483                          ORxS_NUMR_12)
 484
 485 #define CONFIG_SYS_LSDMR       0x0169A512
 486 #define CONFIG_SYS_LSRT 0x79
 487
 488 #define CONFIG_SYS_MPTPR        (0x0800 & MPTPR_PTP_MSK)
 489
 490 /* Bank 4 - On board registers
 491  *
 492  */
 493 #define CONFIG_SYS_BR4_PRELIM   ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK)  |\
 494                            BRx_PS_8                     |\
 495                            BRx_MS_GPCM_P                |\
 496                            BRx_V)
 497
 498 #define CONFIG_SYS_OR4_PRELIM    (ORxG_AM_MSK                 |\
 499                            ORxG_CSNT                   |\
 500                            ORxG_ACS_DIV1               |\
 501                            ORxG_SCY_5_CLK              |\
 502                            ORxG_TRLX)
 503
 504 #endif  /* __CONFIG_H */