include/configs/RRvision.h

   1 /*
   2  * (C) Copyright 2000, 2001, 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC823           1       /* This is a MPC823 CPU         */
  21 #define CONFIG_RRVISION         1       /* ...on a RRvision board       */
  22
  23 #define CONFIG_SYS_TEXT_BASE    0x40000000
  24
  25 #define CONFIG_8xx_GCLK_FREQ 64000000
  26
  27 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  28 #undef  CONFIG_8xx_CONS_SMC2
  29 #undef  CONFIG_8xx_CONS_NONE
  30 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  31 #if 0
  32 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  33 #else
  34 #define CONFIG_BOOTDELAY        3       /* autoboot after 5 seconds     */
  35 #endif
  36
  37 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  38
  39 #define CONFIG_PREBOOT  "setenv stdout serial"
  40
  41 #undef  CONFIG_BOOTARGS
  42 #define CONFIG_ETHADDR                00:50:C2:00:E0:70
  43 #define CONFIG_OVERWRITE_ETHADDR_ONCE 1
  44 #define CONFIG_IPADDR                 10.0.0.5
  45 #define CONFIG_SERVERIP               10.0.0.2
  46 #define CONFIG_NETMASK                255.0.0.0
  47 #define CONFIG_ROOTPATH               "/opt/eldk/ppc_8xx"
  48 #define CONFIG_BOOTCOMMAND            "run flash_self"
  49
  50 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  51         "netdev=eth0\0"                                                 \
  52         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  53         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  54                 "nfsroot=${serverip}:${rootpath}\0"                     \
  55         "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}"    \
  56                 ":${gatewayip}:${netmask}:${hostname}:${netdev}:off\0"  \
  57         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
  58         "load=tftp 100000 /tftpboot/u-boot.bin\0"                       \
  59         "update=protect off 1:0-8;era 1:0-8;"                           \
  60                 "cp.b 100000 40000000 ${filesize};"                     \
  61                 "setenv filesize;saveenv\0"                             \
  62         "kernel_addr=40040000\0"                                        \
  63         "ramdisk_addr=40100000\0"                                       \
  64         "kernel_img=/tftpboot/uImage\0"                                 \
  65         "kernel_load=tftp 200000 ${kernel_img}\0"                       \
  66         "net_nfs=run kernel_load nfsargs addip addtty;bootm\0"          \
  67         "flash_nfs=run nfsargs addip addtty;bootm ${kernel_addr}\0"     \
  68         "flash_self=run ramargs addip addtty;"                          \
  69                 "bootm ${kernel_addr} ${ramdisk_addr}\0"
  70
  71
  72 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  73 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  74
  75 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  76
  77 #undef  CONFIG_STATUS_LED               /* disturbs display             */
  78
  79 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  80
  81 /*
  82  * BOOTP options
  83  */
  84 #define CONFIG_BOOTP_SUBNETMASK
  85 #define CONFIG_BOOTP_GATEWAY
  86 #define CONFIG_BOOTP_HOSTNAME
  87 #define CONFIG_BOOTP_BOOTPATH
  88 #define CONFIG_BOOTP_BOOTFILESIZE
  89
  90
  91 #define CONFIG_MAC_PARTITION
  92 #define CONFIG_DOS_PARTITION
  93
  94 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  95
  96
  97 #ifdef CONFIG_LCD
  98 #define CONFIG_MPC8XX_LCD
  99 #else
 100 #define CONFIG_VIDEO            1       /* To enable the video initialization */
 101
 102 /* Video related */
 103 #define CONFIG_VIDEO_LOGO                       1       /* Show the logo */
 104 #define CONFIG_VIDEO_ENCODER_AD7179             1       /* Enable this encoder */
 105 #define CONFIG_VIDEO_ENCODER_AD7179_ADDR        0x2A    /* ALSB to ground */
 106 #endif
 107
 108 /* enable I2C and select the hardware/software driver */
 109 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 110 #define CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 111
 112 # define CONFIG_SYS_I2C_SPEED           50000   /* 50 kHz is supposed to work   */
 113 # define CONFIG_SYS_I2C_SLAVE           0xFE
 114
 115 #ifdef CONFIG_SOFT_I2C
 116 /*
 117  * Software (bit-bang) I2C driver configuration
 118  */
 119 #define PB_SCL          0x00000020      /* PB 26 */
 120 #define PB_SDA          0x00000010      /* PB 27 */
 121
 122 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 123 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 124 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 125 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 126 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 127                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 128 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 129                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 130 #define I2C_DELAY       udelay(1)       /* 1/4 I2C clock duration */
 131 #endif  /* CONFIG_SOFT_I2C */
 132
 133
 134 /*
 135  * Command line configuration.
 136  */
 137 #include <config_cmd_default.h>
 138
 139 #define CONFIG_CMD_DHCP
 140 #define CONFIG_CMD_I2C
 141 #define CONFIG_CMD_IDE
 142 #define CONFIG_CMD_DATE
 143
 144 #undef CONFIG_CMD_PCMCIA
 145 #undef CONFIG_CMD_IDE
 146
 147
 148 /*
 149  * Miscellaneous configurable options
 150  */
 151 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 152 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 153 #if defined(CONFIG_CMD_KGDB)
 154 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 155 #else
 156 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 157 #endif
 158 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 159 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 160 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 161
 162 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 163 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 164
 165 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 166
 167 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 168
 169 /*
 170  * Low Level Configuration Settings
 171  * (address mappings, register initial values, etc.)
 172  * You should know what you are doing if you make changes here.
 173  */
 174 /*-----------------------------------------------------------------------
 175  * Internal Memory Mapped Register
 176  */
 177 #define CONFIG_SYS_IMMR         0xFFF00000
 178
 179 /*-----------------------------------------------------------------------
 180  * Definitions for initial stack pointer and data area (in DPRAM)
 181  */
 182 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 183 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 184 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 185 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 186
 187 /*-----------------------------------------------------------------------
 188  * Start addresses for the final memory configuration
 189  * (Set up by the startup code)
 190  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 191  */
 192 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 193 #define CONFIG_SYS_FLASH_BASE           0x40000000
 194 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 195 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 196 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 197
 198 /*
 199  * For booting Linux, the board info and command line data
 200  * have to be in the first 8 MB of memory, since this is
 201  * the maximum mapped by the Linux kernel during initialization.
 202  */
 203 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 204
 205 /*-----------------------------------------------------------------------
 206  * FLASH organization
 207  */
 208 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 209 #define CONFIG_SYS_MAX_FLASH_SECT       71      /* max number of sectors on one chip    */
 210
 211 /* timeout values are in ticks = ms */
 212 #define CONFIG_SYS_FLASH_ERASE_TOUT     (120*CONFIG_SYS_HZ)     /* Timeout for Flash Erase      */
 213 #define CONFIG_SYS_FLASH_WRITE_TOUT     (1 * CONFIG_SYS_HZ)     /* Timeout for Flash Write      */
 214
 215 #define CONFIG_ENV_IS_IN_FLASH  1
 216 #define CONFIG_ENV_OFFSET               0x8000  /*   Offset   of Environment Sector     */
 217 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 218
 219 /* Address and size of Redundant Environment Sector     */
 220 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
 221 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 222
 223 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 224
 225 /*-----------------------------------------------------------------------
 226  * Cache Configuration
 227  */
 228 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 229 #if defined(CONFIG_CMD_KGDB)
 230 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 231 #endif
 232
 233 /*-----------------------------------------------------------------------
 234  * SYPCR - System Protection Control                            11-9
 235  * SYPCR can only be written once after reset!
 236  *-----------------------------------------------------------------------
 237  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 238  */
 239 #if defined(CONFIG_WATCHDOG)
 240 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 241                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 242 #else
 243 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 244 #endif
 245
 246 /*-----------------------------------------------------------------------
 247  * SIUMCR - SIU Module Configuration                            11-6
 248  *-----------------------------------------------------------------------
 249  * PCMCIA config., multi-function pin tri-state
 250  */
 251 #ifndef CONFIG_CAN_DRIVER
 252 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 253 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 254 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 255 #endif  /* CONFIG_CAN_DRIVER */
 256
 257 /*-----------------------------------------------------------------------
 258  * TBSCR - Time Base Status and Control                         11-26
 259  *-----------------------------------------------------------------------
 260  * Clear Reference Interrupt Status, Timebase freezing enabled
 261  */
 262 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 263
 264 /*-----------------------------------------------------------------------
 265  * RTCSC - Real-Time Clock Status and Control Register          11-27
 266  *-----------------------------------------------------------------------
 267  */
 268 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 269
 270 /*-----------------------------------------------------------------------
 271  * PISCR - Periodic Interrupt Status and Control                11-31
 272  *-----------------------------------------------------------------------
 273  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 274  */
 275 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF | PISCR_PTE)
 276
 277 /*-----------------------------------------------------------------------
 278  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 279  *-----------------------------------------------------------------------
 280  * Reset PLL lock status sticky bit, timer expired status bit and timer
 281  * interrupt status bit
 282  */
 283
 284 /* for 64 MHz, we use a 16 MHz clock * 4 */
 285 #define CONFIG_SYS_PLPRCR ( (4-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
 286
 287 /*-----------------------------------------------------------------------
 288  * SCCR - System Clock and reset Control Register               15-27
 289  *-----------------------------------------------------------------------
 290  * Set clock output, timebase and RTC source and divider,
 291  * power management and some other internal clocks
 292  */
 293 #define SCCR_MASK       SCCR_EBDF11
 294 #define CONFIG_SYS_SCCR (/* SCCR_TBS  | */ SCCR_RTSEL | SCCR_RTDIV    | \
 295                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 296                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 297                          SCCR_DFALCD00)
 298
 299 /*-----------------------------------------------------------------------
 300  * PCMCIA stuff
 301  *-----------------------------------------------------------------------
 302  *
 303  */
 304 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 305 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 306 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 307 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 308 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 309 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 310 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 311 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 312
 313 /*-----------------------------------------------------------------------
 314  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 315  *-----------------------------------------------------------------------
 316  */
 317
 318 #define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 319 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 320
 321 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 322 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 323 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 324
 325 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 326 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 327
 328 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 329
 330 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 331
 332 /* Offset for data I/O                  */
 333 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 334
 335 /* Offset for normal register accesses  */
 336 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 337
 338 /* Offset for alternate registers       */
 339 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 340
 341 /*-----------------------------------------------------------------------
 342  *
 343  *-----------------------------------------------------------------------
 344  *
 345  */
 346 /*#define       CONFIG_SYS_DER  0x2002000F*/
 347 #define CONFIG_SYS_DER  0
 348
 349 /*
 350  * Init Memory Controller:
 351  *
 352  * BR0/1 (FLASH)
 353  */
 354
 355 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 356
 357 /* used to re-map FLASH both when starting from SRAM or FLASH:
 358  * restrict access enough to keep SRAM working (if any)
 359  * but not too much to meddle with FLASH accesses
 360  */
 361 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 362 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 363
 364 /*
 365  * FLASH timing:
 366  */
 367 /* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
 368 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 369                                  OR_SCY_3_CLK | OR_EHTR | OR_BI)
 370
 371 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 372 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 373 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 374
 375 /*
 376  * BR2/3 and OR2/3 (SDRAM)
 377  *
 378  */
 379 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 380 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 381 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 382
 383 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 384 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000A00
 385
 386 #define CONFIG_SYS_OR2_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 387 #define CONFIG_SYS_BR2_PRELIM   ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 388
 389 #ifndef CONFIG_CAN_DRIVER
 390 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 391 #define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 392 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 393 #define CONFIG_SYS_CAN_BASE             0xC0000000      /* CAN mapped at 0xC0000000     */
 394 #define CONFIG_SYS_CAN_OR_AM            0xFFFF8000      /* 32 kB address mask           */
 395 #define CONFIG_SYS_OR3_CAN              (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
 396 #define CONFIG_SYS_BR3_CAN              ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 397                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 398 #endif  /* CONFIG_CAN_DRIVER */
 399
 400 /*
 401  * Memory Periodic Timer Prescaler
 402  *
 403  * The Divider for PTA (refresh timer) configuration is based on an
 404  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 405  * the number of chip selects (NCS) and the actually needed refresh
 406  * rate is done by setting MPTPR.
 407  *
 408  * PTA is calculated from
 409  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 410  *
 411  *      gclk      CPU clock (not bus clock!)
 412  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 413  *
 414  * 4096  Rows from SDRAM example configuration
 415  * 1000  factor s -> ms
 416  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 417  *    4  Number of refresh cycles per period
 418  *   64  Refresh cycle in ms per number of rows
 419  * --------------------------------------------
 420  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 421  *
 422  * 50 MHz => 50.000.000 / Divider =  98
 423  * 66 Mhz => 66.000.000 / Divider = 129
 424  * 80 Mhz => 80.000.000 / Divider = 156
 425  */
 426 #define CONFIG_SYS_MAMR_PTA             129
 427
 428 /*
 429  * For 16 MBit, refresh rates could be 31.3 us
 430  * (= 64 ms / 2K = 125 / quad bursts).
 431  * For a simpler initialization, 15.6 us is used instead.
 432  *
 433  * #define CONFIG_SYS_MPTPR_2BK_2K      MPTPR_PTP_DIV32         for 2 banks
 434  * #define CONFIG_SYS_MPTPR_1BK_2K      MPTPR_PTP_DIV64         for 1 bank
 435  */
 436 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 437 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 438
 439 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 440 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 441 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 442
 443 /*
 444  * MAMR settings for SDRAM
 445  */
 446
 447 /* 8 column SDRAM */
 448 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 449                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 450                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 451 /* 9 column SDRAM */
 452 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 453                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 454                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 455
 456
 457 #endif  /* __CONFIG_H */