include/configs/Rattler.h

   1 /*
   2  * Copyright (C) 2004 Arabella Software Ltd.
   3  * Yuli Barcohen <yuli@arabellasw.com>
   4  *
   5  * U-Boot configuration for Analogue&Micro Rattler boards.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #ifdef CONFIG_MPC8248
  14 #define CPU_ID_STR              "MPC8248"
  15 #else
  16 #define CONFIG_MPC8260
  17 #define CPU_ID_STR              "MPC8250"
  18 #endif /* CONFIG_MPC8248 */
  19
  20 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  21
  22 #define CONFIG_CPM2             1       /* Has a CPM2 */
  23
  24 #define CONFIG_RATTLER                  /* Analogue&Micro Rattler board */
  25
  26 /* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
  27 #define CONFIG_ENV_OVERWRITE
  28
  29 /*
  30  * Select serial console configuration
  31  *
  32  * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  33  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  34  * for SCC).
  35  */
  36 #define CONFIG_CONS_ON_SMC              /* Console is on SMC         */
  37 #undef  CONFIG_CONS_ON_SCC              /* It's not on SCC           */
  38 #undef  CONFIG_CONS_NONE                /* It's not on external UART */
  39 #define CONFIG_CONS_INDEX       1       /* SMC1 is used for console  */
  40
  41 /*
  42  * Select ethernet configuration
  43  *
  44  * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
  45  * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
  46  * SCC, 1-3 for FCC)
  47  *
  48  * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
  49  * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
  50  * must be unset.
  51  */
  52 #undef  CONFIG_ETHER_ON_SCC             /* Ethernet is not on SCC */
  53 #define CONFIG_ETHER_ON_FCC             /* Ethernet is on FCC     */
  54 #undef  CONFIG_ETHER_NONE               /* No external Ethernet   */
  55
  56 #ifdef CONFIG_ETHER_ON_FCC
  57
  58 #define CONFIG_ETHER_INDEX      1       /* FCC1 is used for Ethernet */
  59
  60 #if   (CONFIG_ETHER_INDEX == 1)
  61
  62 /* - Rx clock is CLK11
  63  * - Tx clock is CLK10
  64  * - BDs/buffers on 60x bus
  65  * - Full duplex
  66  */
  67 #define CONFIG_SYS_CMXFCR_MASK1         (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
  68 #define CONFIG_SYS_CMXFCR_VALUE1        (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
  69 #define CONFIG_SYS_CPMFCR_RAMTYPE       0
  70 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)
  71
  72 #elif (CONFIG_ETHER_INDEX == 2)
  73
  74 /* - Rx clock is CLK15
  75  * - Tx clock is CLK14
  76  * - BDs/buffers on 60x bus
  77  * - Full duplex
  78  */
  79 #define CONFIG_SYS_CMXFCR_MASK2         (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  80 #define CONFIG_SYS_CMXFCR_VALUE2        (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK14)
  81 #define CONFIG_SYS_CPMFCR_RAMTYPE       0
  82 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)
  83
  84 #endif /* CONFIG_ETHER_INDEX */
  85
  86 #define CONFIG_MII                      /* MII PHY management        */
  87 #define CONFIG_BITBANGMII               /* Bit-banged MDIO interface */
  88 /*
  89  * GPIO pins used for bit-banged MII communications
  90  */
  91 #define MDIO_PORT               2       /* Port C */
  92 #define MDIO_DECLARE            volatile ioport_t *iop = ioport_addr ( \
  93                                         (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
  94 #define MDC_DECLARE             MDIO_DECLARE
  95
  96 #define MDIO_ACTIVE             (iop->pdir |=  0x00400000)
  97 #define MDIO_TRISTATE           (iop->pdir &= ~0x00400000)
  98 #define MDIO_READ               ((iop->pdat &  0x00400000) != 0)
  99
 100 #define MDIO(bit)               if(bit) iop->pdat |=  0x00400000; \
 101                                 else    iop->pdat &= ~0x00400000
 102
 103 #define MDC(bit)                if(bit) iop->pdat |=  0x00800000; \
 104                                 else    iop->pdat &= ~0x00800000
 105
 106 #define MIIDELAY                udelay(1)
 107
 108 #endif /* CONFIG_ETHER_ON_FCC */
 109
 110 #ifndef CONFIG_8260_CLKIN
 111 #define CONFIG_8260_CLKIN       100000000       /* in Hz */
 112 #endif
 113
 114 #define CONFIG_BAUDRATE         38400
 115
 116
 117 /*
 118  * BOOTP options
 119  */
 120 #define CONFIG_BOOTP_BOOTFILESIZE
 121 #define CONFIG_BOOTP_BOOTPATH
 122 #define CONFIG_BOOTP_GATEWAY
 123 #define CONFIG_BOOTP_HOSTNAME
 124
 125
 126 /*
 127  * Command line configuration.
 128  */
 129 #include <config_cmd_default.h>
 130
 131 #define CONFIG_CMD_DHCP
 132 #define CONFIG_CMD_IMMAP
 133 #define CONFIG_CMD_JFFS2
 134 #define CONFIG_CMD_MII
 135 #define CONFIG_CMD_PING
 136
 137
 138 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 139 #define CONFIG_BOOTCOMMAND      "bootm FE040000"        /* autoboot command */
 140 #define CONFIG_BOOTARGS         "root=/dev/mtdblock2 rw mtdparts=phys:1M(ROM)ro,-(root)"
 141
 142 #if defined(CONFIG_CMD_KGDB)
 143 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
 144 #define CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
 145 #undef  CONFIG_KGDB_NONE                /* define if kgdb on something else */
 146 #define CONFIG_KGDB_INDEX       2       /* which serial channel for kgdb */
 147 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port at */
 148 #endif
 149
 150 #define CONFIG_BZIP2    /* include support for bzip2 compressed images */
 151 #undef  CONFIG_WATCHDOG                 /* disable platform specific watchdog */
 152
 153 /*
 154  * Miscellaneous configurable options
 155  */
 156 #define CONFIG_SYS_HUSH_PARSER
 157 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 158 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt   */
 159 #if defined(CONFIG_CMD_KGDB)
 160 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 161 #else
 162 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 163 #endif
 164 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size  */
 165 #define CONFIG_SYS_MAXARGS              16              /* max number of command args */
 166 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size  */
 167
 168 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 169 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 170
 171 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 172
 173 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 174
 175 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
 176
 177 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 178 #define CONFIG_SYS_FLASH_CFI
 179 #define CONFIG_FLASH_CFI_DRIVER
 180 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks       */
 181 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max num of sects on one chip */
 182
 183 #define CONFIG_SYS_DIRECT_FLASH_TFTP
 184
 185 #if defined(CONFIG_CMD_JFFS2)
 186 #define CONFIG_SYS_JFFS2_NUM_BANKS      CONFIG_SYS_MAX_FLASH_BANKS
 187 #define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
 188
 189 /*
 190  * JFFS2 partitions
 191  *
 192  */
 193 /* No command line, one static partition */
 194 #undef CONFIG_CMD_MTDPARTS
 195 #define CONFIG_JFFS2_DEV                "nor0"
 196 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 197 #define CONFIG_JFFS2_PART_OFFSET        0x00100000
 198
 199 /* mtdparts command line support */
 200 /* Note: fake mtd_id used, no linux mtd map file */
 201 /*
 202 #define CONFIG_CMD_MTDPARTS
 203 #define MTDIDS_DEFAULT          "nor0=rattler-0"
 204 #define MTDPARTS_DEFAULT        "mtdparts=rattler-0:-@1m(jffs2)"
 205 */
 206 #endif /* CONFIG_CMD_JFFS2 */
 207
 208 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 209 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 210 #define CONFIG_SYS_RAMBOOT
 211 #endif
 212
 213 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 214
 215 #define CONFIG_ENV_IS_IN_FLASH
 216
 217 #ifdef CONFIG_ENV_IS_IN_FLASH
 218 #define CONFIG_ENV_SECT_SIZE    0x10000
 219 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 220 #endif /* CONFIG_ENV_IS_IN_FLASH */
 221
 222 #define CONFIG_SYS_DEFAULT_IMMR 0xFF010000
 223
 224 #define CONFIG_SYS_IMMR         0xF0000000
 225
 226 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 227 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000  /* Size of used area in DPRAM   */
 228 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 229 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 230
 231 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 232 #define CONFIG_SYS_SDRAM_SIZE           32
 233 #define CONFIG_SYS_SDRAM_BR             (CONFIG_SYS_SDRAM_BASE | 0x00000041)
 234 #define CONFIG_SYS_SDRAM_OR             0xFE002EC0
 235
 236 #define CONFIG_SYS_BCSR         0xFC000000
 237
 238 /* Hard reset configuration word */
 239 #define CONFIG_SYS_HRCW_MASTER          0x0A06875A /* Not used - provided by FPGA */
 240 /* No slaves */
 241 #define CONFIG_SYS_HRCW_SLAVE1          0
 242 #define CONFIG_SYS_HRCW_SLAVE2          0
 243 #define CONFIG_SYS_HRCW_SLAVE3          0
 244 #define CONFIG_SYS_HRCW_SLAVE4          0
 245 #define CONFIG_SYS_HRCW_SLAVE5          0
 246 #define CONFIG_SYS_HRCW_SLAVE6          0
 247 #define CONFIG_SYS_HRCW_SLAVE7          0
 248
 249 #define CONFIG_SYS_MALLOC_LEN           (4096 << 10)    /* Reserve 4 MB for malloc()    */
 250 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 251
 252 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPUs */
 253 #if defined(CONFIG_CMD_KGDB)
 254 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 255 #endif
 256
 257 #define CONFIG_SYS_HID0_INIT            0
 258 #define CONFIG_SYS_HID0_FINAL           (HID0_ICE | HID0_IFEM | HID0_ABE)
 259
 260 #define CONFIG_SYS_HID2         0
 261
 262 #define CONFIG_SYS_SIUMCR               0x0E04C000
 263 #define CONFIG_SYS_SYPCR                0xFFFFFFC3
 264 #define CONFIG_SYS_BCR                  0x00000000
 265 #define CONFIG_SYS_SCCR         SCCR_DFBRG01
 266
 267 #define CONFIG_SYS_RMR                  RMR_CSRE
 268 #define CONFIG_SYS_TMCNTSC              (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 269 #define CONFIG_SYS_PISCR                (PISCR_PS|PISCR_PTF|PISCR_PTE)
 270 #define CONFIG_SYS_RCCR         0
 271
 272 #define CONFIG_SYS_PSDMR                0x8249A452
 273 #define CONFIG_SYS_PSRT         0x1F
 274 #define CONFIG_SYS_MPTPR                0x2000
 275
 276 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | 0x00001001)
 277 #define CONFIG_SYS_OR0_PRELIM           0xFF001ED6
 278 #define CONFIG_SYS_BR7_PRELIM           (CONFIG_SYS_BCSR | 0x00000801)
 279 #define CONFIG_SYS_OR7_PRELIM           0xFFFF87F6
 280
 281 #define CONFIG_SYS_RESET_ADDRESS        0xC0000000
 282
 283 #endif /* __CONFIG_H */