include/configs/Rattler.h

   1 /*
   2  * Copyright (C) 2004 Arabella Software Ltd.
   3  * Yuli Barcohen <yuli@arabellasw.com>
   4  *
   5  * U-Boot configuration for Analogue&Micro Rattler boards.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #ifndef __CONFIG_H
  27 #define __CONFIG_H
  28
  29 #ifdef CONFIG_MPC8248
  30 #define CPU_ID_STR              "MPC8248"
  31 #else
  32 #define CONFIG_MPC8260
  33 #define CPU_ID_STR              "MPC8250"
  34 #endif /* CONFIG_MPC8248 */
  35
  36 #define CONFIG_CPM2             1       /* Has a CPM2 */
  37
  38 #define CONFIG_RATTLER                  /* Analogue&Micro Rattler board */
  39
  40 /* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
  41 #define CONFIG_ENV_OVERWRITE
  42
  43 /*
  44  * Select serial console configuration
  45  *
  46  * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  47  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  48  * for SCC).
  49  */
  50 #define CONFIG_CONS_ON_SMC              /* Console is on SMC         */
  51 #undef  CONFIG_CONS_ON_SCC              /* It's not on SCC           */
  52 #undef  CONFIG_CONS_NONE                /* It's not on external UART */
  53 #define CONFIG_CONS_INDEX       1       /* SMC1 is used for console  */
  54
  55 /*
  56  * Select ethernet configuration
  57  *
  58  * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
  59  * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
  60  * SCC, 1-3 for FCC)
  61  *
  62  * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
  63  * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
  64  * must be unset.
  65  */
  66 #undef  CONFIG_ETHER_ON_SCC             /* Ethernet is not on SCC */
  67 #define CONFIG_ETHER_ON_FCC             /* Ethernet is on FCC     */
  68 #undef  CONFIG_ETHER_NONE               /* No external Ethernet   */
  69
  70 #ifdef CONFIG_ETHER_ON_FCC
  71
  72 #define CONFIG_ETHER_INDEX      1       /* FCC1 is used for Ethernet */
  73
  74 #if   (CONFIG_ETHER_INDEX == 1)
  75
  76 /* - Rx clock is CLK11
  77  * - Tx clock is CLK10
  78  * - BDs/buffers on 60x bus
  79  * - Full duplex
  80  */
  81 #define CONFIG_SYS_CMXFCR_MASK  (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
  82 #define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
  83 #define CONFIG_SYS_CPMFCR_RAMTYPE       0
  84 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)
  85
  86 #elif (CONFIG_ETHER_INDEX == 2)
  87
  88 /* - Rx clock is CLK15
  89  * - Tx clock is CLK14
  90  * - BDs/buffers on 60x bus
  91  * - Full duplex
  92  */
  93 #define CONFIG_SYS_CMXFCR_MASK  (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  94 #define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK14)
  95 #define CONFIG_SYS_CPMFCR_RAMTYPE       0
  96 #define CONFIG_SYS_FCC_PSMR             (FCC_PSMR_FDE | FCC_PSMR_LPB)
  97
  98 #endif /* CONFIG_ETHER_INDEX */
  99
 100 #define CONFIG_MII                      /* MII PHY management        */
 101 #define CONFIG_BITBANGMII               /* Bit-banged MDIO interface */
 102 /*
 103  * GPIO pins used for bit-banged MII communications
 104  */
 105 #define MDIO_PORT               2       /* Port C */
 106 #define MDIO_DECLARE            volatile ioport_t *iop = ioport_addr ( \
 107                                         (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
 108 #define MDC_DECLARE             MDIO_DECLARE
 109
 110 #define MDIO_ACTIVE             (iop->pdir |=  0x00400000)
 111 #define MDIO_TRISTATE           (iop->pdir &= ~0x00400000)
 112 #define MDIO_READ               ((iop->pdat &  0x00400000) != 0)
 113
 114 #define MDIO(bit)               if(bit) iop->pdat |=  0x00400000; \
 115                                 else    iop->pdat &= ~0x00400000
 116
 117 #define MDC(bit)                if(bit) iop->pdat |=  0x00800000; \
 118                                 else    iop->pdat &= ~0x00800000
 119
 120 #define MIIDELAY                udelay(1)
 121
 122 #endif /* CONFIG_ETHER_ON_FCC */
 123
 124 #ifndef CONFIG_8260_CLKIN
 125 #define CONFIG_8260_CLKIN       100000000       /* in Hz */
 126 #endif
 127
 128 #define CONFIG_BAUDRATE         38400
 129
 130
 131 /*
 132  * BOOTP options
 133  */
 134 #define CONFIG_BOOTP_BOOTFILESIZE
 135 #define CONFIG_BOOTP_BOOTPATH
 136 #define CONFIG_BOOTP_GATEWAY
 137 #define CONFIG_BOOTP_HOSTNAME
 138
 139
 140 /*
 141  * Command line configuration.
 142  */
 143 #include <config_cmd_default.h>
 144
 145 #define CONFIG_CMD_DHCP
 146 #define CONFIG_CMD_IMMAP
 147 #define CONFIG_CMD_JFFS2
 148 #define CONFIG_CMD_MII
 149 #define CONFIG_CMD_PING
 150
 151
 152 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 153 #define CONFIG_BOOTCOMMAND      "bootm FE040000"        /* autoboot command */
 154 #define CONFIG_BOOTARGS         "root=/dev/mtdblock2 rw mtdparts=phys:1M(ROM)ro,-(root)"
 155
 156 #if defined(CONFIG_CMD_KGDB)
 157 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
 158 #define CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
 159 #undef  CONFIG_KGDB_NONE                /* define if kgdb on something else */
 160 #define CONFIG_KGDB_INDEX       2       /* which serial channel for kgdb */
 161 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port at */
 162 #endif
 163
 164 #define CONFIG_BZIP2    /* include support for bzip2 compressed images */
 165 #undef  CONFIG_WATCHDOG                 /* disable platform specific watchdog */
 166
 167 /*
 168  * Miscellaneous configurable options
 169  */
 170 #define CONFIG_SYS_HUSH_PARSER
 171 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 172 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 173 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt   */
 174 #if defined(CONFIG_CMD_KGDB)
 175 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 176 #else
 177 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 178 #endif
 179 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size  */
 180 #define CONFIG_SYS_MAXARGS              16              /* max number of command args */
 181 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size  */
 182
 183 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 184 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 185
 186 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 187
 188 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 189
 190 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
 191
 192 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 193 #define CONFIG_SYS_FLASH_CFI
 194 #define CONFIG_FLASH_CFI_DRIVER
 195 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks       */
 196 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max num of sects on one chip */
 197
 198 #define CONFIG_SYS_DIRECT_FLASH_TFTP
 199
 200 #if defined(CONFIG_CMD_JFFS2)
 201 #define CONFIG_SYS_JFFS2_NUM_BANKS      CONFIG_SYS_MAX_FLASH_BANKS
 202 #define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
 203
 204 /*
 205  * JFFS2 partitions
 206  *
 207  */
 208 /* No command line, one static partition */
 209 #undef CONFIG_CMD_MTDPARTS
 210 #define CONFIG_JFFS2_DEV                "nor0"
 211 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 212 #define CONFIG_JFFS2_PART_OFFSET        0x00100000
 213
 214 /* mtdparts command line support */
 215 /* Note: fake mtd_id used, no linux mtd map file */
 216 /*
 217 #define CONFIG_CMD_MTDPARTS
 218 #define MTDIDS_DEFAULT          "nor0=rattler-0"
 219 #define MTDPARTS_DEFAULT        "mtdparts=rattler-0:-@1m(jffs2)"
 220 */
 221 #endif /* CONFIG_CMD_JFFS2 */
 222
 223 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
 224 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 225 #define CONFIG_SYS_RAMBOOT
 226 #endif
 227
 228 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 229
 230 #define CONFIG_ENV_IS_IN_FLASH
 231
 232 #ifdef CONFIG_ENV_IS_IN_FLASH
 233 #define CONFIG_ENV_SECT_SIZE    0x10000
 234 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 235 #endif /* CONFIG_ENV_IS_IN_FLASH */
 236
 237 #define CONFIG_SYS_DEFAULT_IMMR 0xFF010000
 238
 239 #define CONFIG_SYS_IMMR         0xF0000000
 240
 241 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 242 #define CONFIG_SYS_INIT_RAM_END 0x2000  /* End of used area in DPRAM    */
 243 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* size in bytes reserved for initial data */
 244 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 245 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 246
 247 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 248 #define CONFIG_SYS_SDRAM_SIZE           32
 249 #define CONFIG_SYS_SDRAM_BR             (CONFIG_SYS_SDRAM_BASE | 0x00000041)
 250 #define CONFIG_SYS_SDRAM_OR             0xFE002EC0
 251
 252 #define CONFIG_SYS_BCSR         0xFC000000
 253
 254 /* Hard reset configuration word */
 255 #define CONFIG_SYS_HRCW_MASTER          0x0A06875A /* Not used - provided by FPGA */
 256 /* No slaves */
 257 #define CONFIG_SYS_HRCW_SLAVE1          0
 258 #define CONFIG_SYS_HRCW_SLAVE2          0
 259 #define CONFIG_SYS_HRCW_SLAVE3          0
 260 #define CONFIG_SYS_HRCW_SLAVE4          0
 261 #define CONFIG_SYS_HRCW_SLAVE5          0
 262 #define CONFIG_SYS_HRCW_SLAVE6          0
 263 #define CONFIG_SYS_HRCW_SLAVE7          0
 264
 265 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
 266 #define BOOTFLAG_WARM           0x02    /* Software reboot                  */
 267
 268 #define CONFIG_SYS_MALLOC_LEN           (4096 << 10)    /* Reserve 4 MB for malloc()    */
 269 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 270
 271 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPUs */
 272 #if defined(CONFIG_CMD_KGDB)
 273 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 274 #endif
 275
 276 #define CONFIG_SYS_HID0_INIT            0
 277 #define CONFIG_SYS_HID0_FINAL           (HID0_ICE | HID0_IFEM | HID0_ABE)
 278
 279 #define CONFIG_SYS_HID2         0
 280
 281 #define CONFIG_SYS_SIUMCR               0x0E04C000
 282 #define CONFIG_SYS_SYPCR                0xFFFFFFC3
 283 #define CONFIG_SYS_BCR                  0x00000000
 284 #define CONFIG_SYS_SCCR         SCCR_DFBRG01
 285
 286 #define CONFIG_SYS_RMR                  RMR_CSRE
 287 #define CONFIG_SYS_TMCNTSC              (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 288 #define CONFIG_SYS_PISCR                (PISCR_PS|PISCR_PTF|PISCR_PTE)
 289 #define CONFIG_SYS_RCCR         0
 290
 291 #define CONFIG_SYS_PSDMR                0x8249A452
 292 #define CONFIG_SYS_PSRT         0x1F
 293 #define CONFIG_SYS_MPTPR                0x2000
 294
 295 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | 0x00001001)
 296 #define CONFIG_SYS_OR0_PRELIM           0xFF001ED6
 297 #define CONFIG_SYS_BR7_PRELIM           (CONFIG_SYS_BCSR | 0x00000801)
 298 #define CONFIG_SYS_OR7_PRELIM           0xFFFF87F6
 299
 300 #define CONFIG_SYS_RESET_ADDRESS        0xC0000000
 301
 302 #endif /* __CONFIG_H */