include/configs/SCM.h

   1 /*
   2  * (C) Copyright 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC8260          1       /* This is a MPC8260 CPU                */
  37 #define CONFIG_TQM8260          200     /* ...on a TQM8260 module Rev.200       */
  38 #define CONFIG_SCM              1       /* ...on a System Controller Module     */
  39 #define CONFIG_CPM2             1       /* Has a CPM2 */
  40
  41 #if (CONFIG_TQM8260 <= 100)
  42 #  error "TQM8260 module revison not supported"
  43 #endif
  44
  45 /* We use a TQM8260 module with a 300MHz CPU */
  46 #define CONFIG_300MHz
  47
  48 /* Define 60x busmode only if your TQM8260 has L2 cache! */
  49 #ifdef CONFIG_L2_CACHE
  50 #  define CONFIG_BUSMODE_60x    1       /* bus mode: 60x                        */
  51 #else
  52 #  undef  CONFIG_BUSMODE_60x            /* bus mode: 8260                       */
  53 #endif
  54
  55 /* The board with 300MHz CPU doesn't have L2 cache, but works in 60x bus mode */
  56 #ifdef CONFIG_300MHz
  57 #  define CONFIG_BUSMODE_60x
  58 #endif
  59
  60 #define CONFIG_82xx_CONS_SMC1   1       /* console on SMC1                      */
  61
  62 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  63
  64 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  65
  66 #define CONFIG_PREBOOT  "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
  67
  68 #undef  CONFIG_BOOTARGS
  69 #define CONFIG_BOOTCOMMAND                                                      \
  70         "bootp; "                                                               \
  71         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
  72         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
  73         "bootm"
  74
  75 /* enable I2C and select the hardware/software driver */
  76 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
  77 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
  78 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
  79 #define CFG_I2C_SLAVE           0x7F
  80
  81 /*
  82  * Software (bit-bang) I2C driver configuration
  83  */
  84
  85 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
  86 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
  87 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
  88 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
  89 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
  90                         else    iop->pdat &= ~0x00010000
  91 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
  92                         else    iop->pdat &= ~0x00020000
  93 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
  94
  95 #define CFG_I2C_EEPROM_ADDR     0x50
  96 #define CFG_I2C_EEPROM_ADDR_LEN 2
  97 #define CFG_EEPROM_PAGE_WRITE_BITS      4
  98 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10      /* and takes up to 10 msec */
  99
 100 #define CONFIG_I2C_X
 101
 102 /*
 103  * select serial console configuration
 104  *
 105  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 106  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 107  * for SCC).
 108  *
 109  * if CONFIG_CONS_NONE is defined, then the serial console routines must
 110  * defined elsewhere (for example, on the cogent platform, there are serial
 111  * ports on the motherboard which are used for the serial console - see
 112  * cogent/cma101/serial.[ch]).
 113  */
 114 #define CONFIG_CONS_ON_SMC              /* define if console on SMC */
 115 #undef  CONFIG_CONS_ON_SCC              /* define if console on SCC */
 116 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
 117 #ifdef CONFIG_82xx_CONS_SMC1
 118 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
 119 #endif
 120 #ifdef CONFIG_82xx_CONS_SMC2
 121 #define CONFIG_CONS_INDEX       2       /* which serial channel for console */
 122 #endif
 123
 124 #undef  CONFIG_CONS_USE_EXTC            /* SMC/SCC use ext clock not brg_clk */
 125 #define CONFIG_CONS_EXTC_RATE   3686400 /* SMC/SCC ext clk rate in Hz */
 126 #define CONFIG_CONS_EXTC_PINSEL 0       /* pin select 0=CLK3/CLK9 */
 127
 128 /*
 129  * select ethernet configuration
 130  *
 131  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 132  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 133  * for FCC)
 134  *
 135  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 136  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 137  *
 138  * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
 139  * X.29 connector, and FCC2 is hardwired to the X.1 connector)
 140  */
 141 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
 142 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
 143 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 144 #define CONFIG_ETHER_INDEX    1         /* which SCC/FCC channel for ethernet */
 145
 146 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
 147
 148 /*
 149  * - Rx-CLK is CLK12
 150  * - Tx-CLK is CLK11
 151  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 152  * - Enable Full Duplex in FSMR
 153  */
 154 # define CFG_CMXFCR_MASK        (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
 155 # define CFG_CMXFCR_VALUE       (CMXFCR_RF1CS_CLK12|CMXFCR_TF1CS_CLK11)
 156 # define CFG_CPMFCR_RAMTYPE     0
 157 # define CFG_FCC_PSMR           (FCC_PSMR_FDE|FCC_PSMR_LPB)
 158
 159 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
 160
 161 /*
 162  * - Rx-CLK is CLK15
 163  * - Tx-CLK is CLK16
 164  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 165  * - Enable Full Duplex in FSMR
 166  */
 167 # define CFG_CMXFCR_MASK        (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
 168 # define CFG_CMXFCR_VALUE       (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
 169 # define CFG_CPMFCR_RAMTYPE     0
 170 # define CFG_FCC_PSMR           (FCC_PSMR_FDE|FCC_PSMR_LPB)
 171
 172 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 173
 174
 175 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 176 #ifndef CONFIG_300MHz
 177 #define CONFIG_8260_CLKIN       66666666        /* in Hz */
 178 #else
 179 #define CONFIG_8260_CLKIN       83333000        /* in Hz */
 180 #endif
 181
 182 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
 183 #define CONFIG_BAUDRATE         230400
 184 #else
 185 #define CONFIG_BAUDRATE         115200
 186 #endif
 187
 188 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 189 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
 190
 191 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 192
 193 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
 194
 195
 196 /*
 197  * Command line configuration.
 198  */
 199 #include <config_cmd_default.h>
 200
 201 #define CONFIG_CMD_DHCP
 202 #define CONFIG_CMD_I2C
 203 #define CONFIG_CMD_EEPROM
 204 #define CONFIG_CMD_BSP
 205
 206
 207 /*
 208  * Miscellaneous configurable options
 209  */
 210 #define CFG_LONGHELP                    /* undef to save memory         */
 211 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 212 #if defined(CONFIG_CMD_KGDB)
 213 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 214 #else
 215 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 216 #endif
 217 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 218 #define CFG_MAXARGS     16              /* max number of command args   */
 219 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 220
 221 #define CFG_MEMTEST_START 0x0400000     /* memtest works on             */
 222 #define CFG_MEMTEST_END 0x0C00000       /* 4 ... 12 MB in DRAM          */
 223
 224 #define CFG_LOAD_ADDR   0x100000        /* default load address         */
 225
 226 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 227
 228 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 229
 230 #define CFG_RESET_ADDRESS 0xFFFFFFFC    /* "bad" address                */
 231
 232 #define CONFIG_MISC_INIT_R              /* have misc_init_r() function  */
 233
 234 /*
 235  * For booting Linux, the board info and command line data
 236  * have to be in the first 8 MB of memory, since this is
 237  * the maximum mapped by the Linux kernel during initialization.
 238  */
 239 #define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 240
 241
 242 /* What should the base address of the main FLASH be and how big is
 243  * it (in MBytes)? This must contain TEXT_BASE from board/tqm8260/config.mk
 244  * The main FLASH is whichever is connected to *CS0.
 245  */
 246 #define CFG_FLASH0_BASE 0x40000000
 247 #define CFG_FLASH1_BASE 0x60000000
 248 #define CFG_FLASH0_SIZE 32
 249 #define CFG_FLASH1_SIZE 32
 250
 251 /* Flash bank size (for preliminary settings)
 252  */
 253 #define CFG_FLASH_SIZE CFG_FLASH0_SIZE
 254
 255 /*-----------------------------------------------------------------------
 256  * FLASH organization
 257  */
 258 #define CFG_MAX_FLASH_BANKS     1       /* max num of memory banks      */
 259 #define CFG_MAX_FLASH_SECT      128     /* max num of sects on one chip */
 260
 261 #define CFG_FLASH_ERASE_TOUT    240000  /* Flash Erase Timeout (in ms)  */
 262 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 263
 264 #if 0
 265 /* Start port with environment in flash; switch to EEPROM later */
 266 #define CFG_ENV_IS_IN_FLASH     1
 267 #define CFG_ENV_ADDR            (CFG_FLASH_BASE+0x40000)
 268 #define CFG_ENV_SIZE            0x40000
 269 #define CFG_ENV_SECT_SIZE       0x40000
 270 #else
 271 /* Final version: environment in EEPROM */
 272 #define CFG_ENV_IS_IN_EEPROM    1
 273 #define CFG_ENV_OFFSET          0
 274 #define CFG_ENV_SIZE            2048
 275 #endif
 276
 277 /*-----------------------------------------------------------------------
 278  * Hardware Information Block
 279  */
 280 #define CFG_HWINFO_OFFSET       0x0003FFC0      /* offset of HW Info block */
 281 #define CFG_HWINFO_SIZE         0x00000040      /* size   of HW Info block */
 282 #define CFG_HWINFO_MAGIC        0x54514D38      /* 'TQM8' */
 283
 284 /*-----------------------------------------------------------------------
 285  * Hard Reset Configuration Words
 286  *
 287  * if you change bits in the HRCW, you must also change the CFG_*
 288  * defines for the various registers affected by the HRCW e.g. changing
 289  * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
 290  */
 291 #if defined(CONFIG_266MHz)
 292 #define CFG_HRCW_MASTER         (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
 293                                                               HRCW_MODCK_H0111)
 294 #elif defined(CONFIG_300MHz)
 295 #define CFG_HRCW_MASTER         (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
 296                                                               HRCW_MODCK_H0110)
 297 #else
 298 #define CFG_HRCW_MASTER         (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
 299 #endif
 300
 301 /* no slaves so just fill with zeros */
 302 #define CFG_HRCW_SLAVE1         0
 303 #define CFG_HRCW_SLAVE2         0
 304 #define CFG_HRCW_SLAVE3         0
 305 #define CFG_HRCW_SLAVE4         0
 306 #define CFG_HRCW_SLAVE5         0
 307 #define CFG_HRCW_SLAVE6         0
 308 #define CFG_HRCW_SLAVE7         0
 309
 310 /*-----------------------------------------------------------------------
 311  * Internal Memory Mapped Register
 312  */
 313 #define CFG_IMMR                0xFFF00000
 314
 315 /*-----------------------------------------------------------------------
 316  * Definitions for initial stack pointer and data area (in DPRAM)
 317  */
 318 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 319 #define CFG_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
 320 #define CFG_GBL_DATA_SIZE       128 /* size in bytes reserved for initial data*/
 321 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 322 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 323
 324 /*-----------------------------------------------------------------------
 325  * Start addresses for the final memory configuration
 326  * (Set up by the startup code)
 327  * Please note that CFG_SDRAM_BASE _must_ start at 0
 328  *
 329  * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
 330  * is mapped at SDRAM_BASE2_PRELIM.
 331  */
 332 #define CFG_SDRAM_BASE          0x00000000
 333 #define CFG_FLASH_BASE          CFG_FLASH0_BASE
 334 #define CFG_MONITOR_BASE        TEXT_BASE
 335 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor */
 336 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()*/
 337
 338 /*
 339  * Internal Definitions
 340  *
 341  * Boot Flags
 342  */
 343 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH*/
 344 #define BOOTFLAG_WARM           0x02    /* Software reboot                 */
 345
 346
 347 /*-----------------------------------------------------------------------
 348  * Hardware Information Block
 349  */
 350 #define CFG_HWINFO_OFFSET       0x0003FFC0      /* offset of HW Info block */
 351 #define CFG_HWINFO_SIZE         0x00000040      /* size   of HW Info block */
 352 #define CFG_HWINFO_MAGIC        0x54514D38      /* 'TQM8' */
 353
 354 /*-----------------------------------------------------------------------
 355  * Cache Configuration
 356  */
 357 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 358 #if defined(CONFIG_CMD_KGDB)
 359 # define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 360 #endif
 361
 362 /*-----------------------------------------------------------------------
 363  * HIDx - Hardware Implementation-dependent Registers                    2-11
 364  *-----------------------------------------------------------------------
 365  * HID0 also contains cache control - initially enable both caches and
 366  * invalidate contents, then the final state leaves only the instruction
 367  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 368  * but Soft reset does not.
 369  *
 370  * HID1 has only read-only information - nothing to set.
 371  */
 372 #define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 373                                 HID0_IFEM|HID0_ABE)
 374 #define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
 375 #define CFG_HID2        0
 376
 377 /*-----------------------------------------------------------------------
 378  * RMR - Reset Mode Register                                     5-5
 379  *-----------------------------------------------------------------------
 380  * turn on Checkstop Reset Enable
 381  */
 382 #define CFG_RMR         RMR_CSRE
 383
 384 /*-----------------------------------------------------------------------
 385  * BCR - Bus Configuration                                       4-25
 386  *-----------------------------------------------------------------------
 387  */
 388 #ifdef  CONFIG_BUSMODE_60x
 389 #define CFG_BCR         (BCR_EBM|BCR_L2C|BCR_LETM|\
 390                          BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode  */
 391 #else
 392 #define BCR_APD01       0x10000000
 393 #define CFG_BCR         (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
 394 #endif
 395
 396 /*-----------------------------------------------------------------------
 397  * SIUMCR - SIU Module Configuration                             4-31
 398  *-----------------------------------------------------------------------
 399  */
 400 #if 0
 401 #define CFG_SIUMCR      (SIUMCR_DPPC10|SIUMCR_APPC10)
 402 #else
 403 #define CFG_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10)
 404 #endif
 405
 406
 407 /*-----------------------------------------------------------------------
 408  * SYPCR - System Protection Control                             4-35
 409  * SYPCR can only be written once after reset!
 410  *-----------------------------------------------------------------------
 411  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 412  */
 413 #if defined(CONFIG_WATCHDOG)
 414 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 415                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 416 #else
 417 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 418                          SYPCR_SWRI|SYPCR_SWP)
 419 #endif /* CONFIG_WATCHDOG */
 420
 421 /*-----------------------------------------------------------------------
 422  * TMCNTSC - Time Counter Status and Control                     4-40
 423  *-----------------------------------------------------------------------
 424  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 425  * and enable Time Counter
 426  */
 427 #define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 428
 429 /*-----------------------------------------------------------------------
 430  * PISCR - Periodic Interrupt Status and Control                 4-42
 431  *-----------------------------------------------------------------------
 432  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 433  * Periodic timer
 434  */
 435 #define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 436
 437 /*-----------------------------------------------------------------------
 438  * SCCR - System Clock Control                                   9-8
 439  *-----------------------------------------------------------------------
 440  * Ensure DFBRG is Divide by 16
 441  */
 442 #define CFG_SCCR        0
 443
 444 /*-----------------------------------------------------------------------
 445  * RCCR - RISC Controller Configuration                         13-7
 446  *-----------------------------------------------------------------------
 447  */
 448 #define CFG_RCCR        0
 449
 450 /*
 451  * Init Memory Controller:
 452  *
 453  * Bank Bus     Machine PortSz  Device
 454  * ---- ---     ------- ------  ------
 455  *  0   60x     GPCM    64 bit  FLASH
 456  *  1   60x     SDRAM   64 bit  SDRAM
 457  *  2   Local   SDRAM   32 bit  SDRAM
 458  *
 459  */
 460
 461         /* Initialize SDRAM on local bus
 462          */
 463 #define CFG_INIT_LOCAL_SDRAM
 464
 465 #define SDRAM_MAX_SIZE  0x08000000      /* max. 128 MB          */
 466
 467 /* Minimum mask to separate preliminary
 468  * address ranges for CS[0:2]
 469  */
 470 #define CFG_GLOBAL_SDRAM_LIMIT  (512<<20)       /* less than 512 MB */
 471 #define CFG_LOCAL_SDRAM_LIMIT   (128<<20)       /* less than 128 MB */
 472
 473 #define CFG_MPTPR       0x4000
 474
 475 /*-----------------------------------------------------------------------------
 476  * Address for Mode Register Set (MRS) command
 477  *-----------------------------------------------------------------------------
 478  * In fact, the address is rather configuration data presented to the SDRAM on
 479  * its address lines. Because the address lines may be mux'ed externally either
 480  * for 8 column or 9 column devices, some bits appear twice in the 8260's
 481  * address:
 482  *
 483  * |   (RFU)   |   (RFU)   | WBL |    TM    |     CL    |  BT | Burst Length |
 484  * | BA1   BA0 | A12 : A10 |  A9 |  A8   A7 |  A6 : A4  |  A3 |   A2 :  A0   |
 485  *  8 columns mux'ing:     |  A9 | A10  A21 | A22 : A24 | A25 |  A26 : A28   |
 486  *  9 columns mux'ing:     |  A8 | A20  A21 | A22 : A24 | A25 |  A26 : A28   |
 487  *  Settings:              |  0  |  0    0  |  0  1  0  |  0  |   0  1  0    |
 488  *-----------------------------------------------------------------------------
 489  */
 490 #define CFG_MRS_OFFS    0x00000110
 491
 492
 493 /* Bank 0 - FLASH
 494  */
 495 #define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
 496                          BRx_PS_64                      |\
 497                          BRx_MS_GPCM_P                  |\
 498                          BRx_V)
 499
 500 #define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH_SIZE)      |\
 501                          ORxG_CSNT                      |\
 502                          ORxG_ACS_DIV1                  |\
 503                          ORxG_SCY_3_CLK                 |\
 504                          ORxG_EHTR                      |\
 505                          ORxG_TRLX)
 506
 507         /* SDRAM on TQM8260 can have either 8 or 9 columns.
 508          * The number affects configuration values.
 509          */
 510
 511 /* Bank 1 - 60x bus SDRAM
 512  */
 513 #define CFG_PSRT        0x20
 514 #define CFG_LSRT        0x20
 515 #ifndef CFG_RAMBOOT
 516 #define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
 517                          BRx_PS_64                      |\
 518                          BRx_MS_SDRAM_P                 |\
 519                          BRx_V)
 520
 521 #define CFG_OR1_PRELIM  CFG_OR1_8COL
 522
 523
 524         /* SDRAM initialization values for 8-column chips
 525          */
 526 #define CFG_OR1_8COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 527                          ORxS_BPD_4                     |\
 528                          ORxS_ROWST_PBI1_A7             |\
 529                          ORxS_NUMR_12)
 530
 531 #define CFG_PSDMR_8COL  (PSDMR_PBI                      |\
 532                          PSDMR_SDAM_A15_IS_A5           |\
 533                          PSDMR_BSMA_A12_A14             |\
 534                          PSDMR_SDA10_PBI1_A8            |\
 535                          PSDMR_RFRC_7_CLK               |\
 536                          PSDMR_PRETOACT_2W              |\
 537                          PSDMR_ACTTORW_2W               |\
 538                          PSDMR_LDOTOPRE_1C              |\
 539                          PSDMR_WRC_2C                   |\
 540                          PSDMR_EAMUX                    |\
 541                          PSDMR_CL_2)
 542
 543         /* SDRAM initialization values for 9-column chips
 544          */
 545 #define CFG_OR1_9COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 546                          ORxS_BPD_4                     |\
 547                          ORxS_ROWST_PBI1_A5             |\
 548                          ORxS_NUMR_13)
 549
 550 #define CFG_PSDMR_9COL  (PSDMR_PBI                      |\
 551                          PSDMR_SDAM_A16_IS_A5           |\
 552                          PSDMR_BSMA_A12_A14             |\
 553                          PSDMR_SDA10_PBI1_A7            |\
 554                          PSDMR_RFRC_7_CLK               |\
 555                          PSDMR_PRETOACT_2W              |\
 556                          PSDMR_ACTTORW_2W               |\
 557                          PSDMR_LDOTOPRE_1C              |\
 558                          PSDMR_WRC_2C                   |\
 559                          PSDMR_EAMUX                    |\
 560                          PSDMR_CL_2)
 561
 562 /* Bank 2 - Local bus SDRAM
 563  */
 564 #ifdef CFG_INIT_LOCAL_SDRAM
 565 #define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
 566                          BRx_PS_32                      |\
 567                          BRx_MS_SDRAM_L                 |\
 568                          BRx_V)
 569
 570 #define CFG_OR2_PRELIM  CFG_OR2_8COL
 571
 572 #define SDRAM_BASE2_PRELIM      0x80000000
 573
 574         /* SDRAM initialization values for 8-column chips
 575          */
 576 #define CFG_OR2_8COL    ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 577                          ORxS_BPD_4                     |\
 578                          ORxS_ROWST_PBI1_A8             |\
 579                          ORxS_NUMR_12)
 580
 581 #define CFG_LSDMR_8COL  (PSDMR_PBI                      |\
 582                          PSDMR_SDAM_A15_IS_A5           |\
 583                          PSDMR_BSMA_A13_A15             |\
 584                          PSDMR_SDA10_PBI1_A9            |\
 585                          PSDMR_RFRC_7_CLK               |\
 586                          PSDMR_PRETOACT_2W              |\
 587                          PSDMR_ACTTORW_2W               |\
 588                          PSDMR_BL                       |\
 589                          PSDMR_LDOTOPRE_1C              |\
 590                          PSDMR_WRC_2C                   |\
 591                          PSDMR_CL_2)
 592
 593         /* SDRAM initialization values for 9-column chips
 594          */
 595 #define CFG_OR2_9COL    ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 596                          ORxS_BPD_4                     |\
 597                          ORxS_ROWST_PBI1_A6             |\
 598                          ORxS_NUMR_13)
 599
 600 #define CFG_LSDMR_9COL  (PSDMR_PBI                      |\
 601                          PSDMR_SDAM_A16_IS_A5           |\
 602                          PSDMR_BSMA_A13_A15             |\
 603                          PSDMR_SDA10_PBI1_A8            |\
 604                          PSDMR_RFRC_7_CLK               |\
 605                          PSDMR_PRETOACT_2W              |\
 606                          PSDMR_ACTTORW_2W               |\
 607                          PSDMR_BL                       |\
 608                          PSDMR_LDOTOPRE_1C              |\
 609                          PSDMR_WRC_2C                   |\
 610                          PSDMR_CL_2)
 611
 612 #endif /* CFG_INIT_LOCAL_SDRAM */
 613
 614 #endif /* CFG_RAMBOOT */
 615
 616 #define CFG_CAN0_BASE           0xc0000000
 617 #define CFG_CAN1_BASE           0xc0008000
 618 #define CFG_FIOX_BASE           0xc0010000
 619 #define CFG_FDOHM_BASE          0xc0018000
 620 #define CFG_EXTPROM_BASE        0xc2000000
 621
 622 #define CFG_CAN_SIZE            0x00000100
 623 #define CFG_FIOX_SIZE           0x00000020
 624 #define CFG_FDOHM_SIZE          0x00002000
 625 #define CFG_EXTPROM_BANK_SIZE   0x01000000
 626
 627 #define EXT_EEPROM_MAX_FLASH_BANKS      0x02
 628
 629 /* CS3 - CAN 0
 630  */
 631 #define CFG_CAN0_BR3   ((CFG_CAN0_BASE & BRx_BA_MSK)    |\
 632                         BRx_PS_8                        |\
 633                         BRx_MS_UPMA                     |\
 634                         BRx_V)
 635
 636 #define CFG_CAN0_OR3   (P2SZ_TO_AM(CFG_CAN_SIZE)        |\
 637                         ORxU_BI                         |\
 638                         ORxU_EHTR_4IDLE)
 639
 640 /* CS4 - CAN 1
 641  */
 642 #define CFG_CAN1_BR4   ((CFG_CAN1_BASE & BRx_BA_MSK)    |\
 643                         BRx_PS_8                        |\
 644                         BRx_MS_UPMA                     |\
 645                         BRx_V)
 646
 647 #define CFG_CAN1_OR4   (P2SZ_TO_AM(CFG_CAN_SIZE)        |\
 648                         ORxU_BI                         |\
 649                         ORxU_EHTR_4IDLE)
 650
 651 /* CS5 - Extended PROM (16MB optional)
 652  */
 653 #define CFG_EXTPROM_BR5 ((CFG_EXTPROM_BASE & BRx_BA_MSK)|\
 654                         BRx_PS_32                       |\
 655                         BRx_MS_GPCM_P                   |\
 656                         BRx_V)
 657
 658 #define CFG_EXTPROM_OR5 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\
 659                         ORxG_CSNT                       |\
 660                         ORxG_ACS_DIV4                   |\
 661                         ORxG_SCY_5_CLK                  |\
 662                         ORxG_TRLX)
 663
 664 /* CS6 - Extended PROM (16MB optional)
 665  */
 666 #define CFG_EXTPROM_BR6 (((CFG_EXTPROM_BASE + \
 667                         CFG_EXTPROM_BANK_SIZE) & BRx_BA_MSK)|\
 668                         BRx_PS_32                       |\
 669                         BRx_MS_GPCM_P                   |\
 670                         BRx_V)
 671
 672 #define CFG_EXTPROM_OR6 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\
 673                         ORxG_CSNT                       |\
 674                         ORxG_ACS_DIV4                   |\
 675                         ORxG_SCY_5_CLK                  |\
 676                         ORxG_TRLX)
 677
 678 /* CS7 - FPGA FIOX: Glue Logic
 679  */
 680 #define CFG_FIOX_BR7   ((CFG_FIOX_BASE & BRx_BA_MSK)    |\
 681                         BRx_PS_32                       |\
 682                         BRx_MS_GPCM_P                   |\
 683                         BRx_V)
 684
 685 #define CFG_FIOX_OR7   (P2SZ_TO_AM(CFG_FIOX_SIZE)       |\
 686                         ORxG_ACS_DIV4                   |\
 687                         ORxG_SCY_5_CLK                  |\
 688                         ORxG_TRLX)
 689
 690 /* CS8 - FPGA DOH Master
 691  */
 692 #define CFG_FDOHM_BR8  ((CFG_FDOHM_BASE & BRx_BA_MSK)   |\
 693                         BRx_PS_16                       |\
 694                         BRx_MS_GPCM_P                   |\
 695                         BRx_V)
 696
 697 #define CFG_FDOHM_OR8  (P2SZ_TO_AM(CFG_FDOHM_SIZE)      |\
 698                         ORxG_ACS_DIV4                   |\
 699                         ORxG_SCY_5_CLK                  |\
 700                         ORxG_TRLX)
 701
 702
 703 /* FPGA configuration */
 704 #define CFG_PD_FIOX_PROG        (1 << (31- 5))  /* PD  5 */
 705 #define CFG_PD_FIOX_DONE        (1 << (31-28))  /* PD 28 */
 706 #define CFG_PD_FIOX_INIT        (1 << (31-29))  /* PD 29 */
 707
 708 #define CFG_PD_FDOHM_PROG       (1 << (31- 4))  /* PD  4 */
 709 #define CFG_PD_FDOHM_DONE       (1 << (31-26))  /* PD 26 */
 710 #define CFG_PD_FDOHM_INIT       (1 << (31-27))  /* PD 27 */
 711
 712
 713 #endif  /* __CONFIG_H */