include/configs/SCM.h

   1 /*
   2  * (C) Copyright 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC8260          1       /* This is a MPC8260 CPU                */
  37 #define CONFIG_TQM8260          200     /* ...on a TQM8260 module Rev.200       */
  38 #define CONFIG_SCM              1       /* ...on a System Controller Module     */
  39 #define CONFIG_CPM2             1       /* Has a CPM2 */
  40
  41 #if (CONFIG_TQM8260 <= 100)
  42 #  error "TQM8260 module revison not supported"
  43 #endif
  44
  45 /* We use a TQM8260 module with a 300MHz CPU */
  46 #define CONFIG_300MHz
  47
  48 /* Define 60x busmode only if your TQM8260 has L2 cache! */
  49 #ifdef CONFIG_L2_CACHE
  50 #  define CONFIG_BUSMODE_60x    1       /* bus mode: 60x                        */
  51 #else
  52 #  undef  CONFIG_BUSMODE_60x            /* bus mode: 8260                       */
  53 #endif
  54
  55 /* The board with 300MHz CPU doesn't have L2 cache, but works in 60x bus mode */
  56 #ifdef CONFIG_300MHz
  57 #  define CONFIG_BUSMODE_60x
  58 #endif
  59
  60 #define CONFIG_82xx_CONS_SMC1   1       /* console on SMC1                      */
  61
  62 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  63
  64 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  65
  66 #define CONFIG_PREBOOT  "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
  67
  68 #undef  CONFIG_BOOTARGS
  69 #define CONFIG_BOOTCOMMAND                                                      \
  70         "bootp; "                                                               \
  71         "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "     \
  72         "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; "   \
  73         "bootm"
  74
  75 /* enable I2C and select the hardware/software driver */
  76 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
  77 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
  78 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
  79 #define CFG_I2C_SLAVE           0x7F
  80
  81 /*
  82  * Software (bit-bang) I2C driver configuration
  83  */
  84
  85 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
  86 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
  87 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
  88 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
  89 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
  90                         else    iop->pdat &= ~0x00010000
  91 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
  92                         else    iop->pdat &= ~0x00020000
  93 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
  94
  95 #define CFG_I2C_EEPROM_ADDR     0x50
  96 #define CFG_I2C_EEPROM_ADDR_LEN 2
  97 #define CFG_EEPROM_PAGE_WRITE_BITS      4
  98 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10      /* and takes up to 10 msec */
  99
 100 #define CONFIG_I2C_X
 101
 102 /*
 103  * select serial console configuration
 104  *
 105  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 106  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 107  * for SCC).
 108  *
 109  * if CONFIG_CONS_NONE is defined, then the serial console routines must
 110  * defined elsewhere (for example, on the cogent platform, there are serial
 111  * ports on the motherboard which are used for the serial console - see
 112  * cogent/cma101/serial.[ch]).
 113  */
 114 #define CONFIG_CONS_ON_SMC              /* define if console on SMC */
 115 #undef  CONFIG_CONS_ON_SCC              /* define if console on SCC */
 116 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
 117 #ifdef CONFIG_82xx_CONS_SMC1
 118 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
 119 #endif
 120 #ifdef CONFIG_82xx_CONS_SMC2
 121 #define CONFIG_CONS_INDEX       2       /* which serial channel for console */
 122 #endif
 123
 124 #undef  CONFIG_CONS_USE_EXTC            /* SMC/SCC use ext clock not brg_clk */
 125 #define CONFIG_CONS_EXTC_RATE   3686400 /* SMC/SCC ext clk rate in Hz */
 126 #define CONFIG_CONS_EXTC_PINSEL 0       /* pin select 0=CLK3/CLK9 */
 127
 128 /*
 129  * select ethernet configuration
 130  *
 131  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 132  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 133  * for FCC)
 134  *
 135  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 136  * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
 137  * from CONFIG_COMMANDS to remove support for networking.
 138  *
 139  * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
 140  * X.29 connector, and FCC2 is hardwired to the X.1 connector)
 141  */
 142 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
 143 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
 144 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 145 #define CONFIG_ETHER_INDEX    1         /* which SCC/FCC channel for ethernet */
 146
 147 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
 148
 149 /*
 150  * - Rx-CLK is CLK12
 151  * - Tx-CLK is CLK11
 152  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 153  * - Enable Full Duplex in FSMR
 154  */
 155 # define CFG_CMXFCR_MASK        (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
 156 # define CFG_CMXFCR_VALUE       (CMXFCR_RF1CS_CLK12|CMXFCR_TF1CS_CLK11)
 157 # define CFG_CPMFCR_RAMTYPE     0
 158 # define CFG_FCC_PSMR           (FCC_PSMR_FDE|FCC_PSMR_LPB)
 159
 160 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
 161
 162 /*
 163  * - Rx-CLK is CLK15
 164  * - Tx-CLK is CLK16
 165  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 166  * - Enable Full Duplex in FSMR
 167  */
 168 # define CFG_CMXFCR_MASK        (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
 169 # define CFG_CMXFCR_VALUE       (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
 170 # define CFG_CPMFCR_RAMTYPE     0
 171 # define CFG_FCC_PSMR           (FCC_PSMR_FDE|FCC_PSMR_LPB)
 172
 173 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 174
 175
 176 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 177 #ifndef CONFIG_300MHz
 178 #define CONFIG_8260_CLKIN       66666666        /* in Hz */
 179 #else
 180 #define CONFIG_8260_CLKIN       83333000        /* in Hz */
 181 #endif
 182
 183 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
 184 #define CONFIG_BAUDRATE         230400
 185 #else
 186 #define CONFIG_BAUDRATE         115200
 187 #endif
 188
 189 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 190 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
 191
 192 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 193
 194 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
 195
 196 #define CONFIG_COMMANDS         (CONFIG_CMD_DFL | \
 197                                  CFG_CMD_DHCP   | \
 198                                  CFG_CMD_I2C    | \
 199                                  CFG_CMD_EEPROM | \
 200                                  CFG_CMD_BSP)
 201
 202 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 203 #include <cmd_confdefs.h>
 204
 205 /*
 206  * Miscellaneous configurable options
 207  */
 208 #define CFG_LONGHELP                    /* undef to save memory         */
 209 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 210 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 211 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 212 #else
 213 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 214 #endif
 215 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 216 #define CFG_MAXARGS     16              /* max number of command args   */
 217 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 218
 219 #define CFG_MEMTEST_START 0x0400000     /* memtest works on             */
 220 #define CFG_MEMTEST_END 0x0C00000       /* 4 ... 12 MB in DRAM          */
 221
 222 #define CFG_LOAD_ADDR   0x100000        /* default load address         */
 223
 224 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 225
 226 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 227
 228 #define CFG_RESET_ADDRESS 0xFFFFFFFC    /* "bad" address                */
 229
 230 #define CONFIG_MISC_INIT_R              /* have misc_init_r() function  */
 231
 232 /*
 233  * For booting Linux, the board info and command line data
 234  * have to be in the first 8 MB of memory, since this is
 235  * the maximum mapped by the Linux kernel during initialization.
 236  */
 237 #define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 238
 239
 240 /* What should the base address of the main FLASH be and how big is
 241  * it (in MBytes)? This must contain TEXT_BASE from board/tqm8260/config.mk
 242  * The main FLASH is whichever is connected to *CS0.
 243  */
 244 #define CFG_FLASH0_BASE 0x40000000
 245 #define CFG_FLASH1_BASE 0x60000000
 246 #define CFG_FLASH0_SIZE 32
 247 #define CFG_FLASH1_SIZE 32
 248
 249 /* Flash bank size (for preliminary settings)
 250  */
 251 #define CFG_FLASH_SIZE CFG_FLASH0_SIZE
 252
 253 /*-----------------------------------------------------------------------
 254  * FLASH organization
 255  */
 256 #define CFG_MAX_FLASH_BANKS     1       /* max num of memory banks      */
 257 #define CFG_MAX_FLASH_SECT      128     /* max num of sects on one chip */
 258
 259 #define CFG_FLASH_ERASE_TOUT    240000  /* Flash Erase Timeout (in ms)  */
 260 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 261
 262 #if 0
 263 /* Start port with environment in flash; switch to EEPROM later */
 264 #define CFG_ENV_IS_IN_FLASH     1
 265 #define CFG_ENV_ADDR            (CFG_FLASH_BASE+0x40000)
 266 #define CFG_ENV_SIZE            0x40000
 267 #define CFG_ENV_SECT_SIZE       0x40000
 268 #else
 269 /* Final version: environment in EEPROM */
 270 #define CFG_ENV_IS_IN_EEPROM    1
 271 #define CFG_ENV_OFFSET          0
 272 #define CFG_ENV_SIZE            2048
 273 #endif
 274
 275 /*-----------------------------------------------------------------------
 276  * Hardware Information Block
 277  */
 278 #define CFG_HWINFO_OFFSET       0x0003FFC0      /* offset of HW Info block */
 279 #define CFG_HWINFO_SIZE         0x00000040      /* size   of HW Info block */
 280 #define CFG_HWINFO_MAGIC        0x54514D38      /* 'TQM8' */
 281
 282 /*-----------------------------------------------------------------------
 283  * Hard Reset Configuration Words
 284  *
 285  * if you change bits in the HRCW, you must also change the CFG_*
 286  * defines for the various registers affected by the HRCW e.g. changing
 287  * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
 288  */
 289 #if defined(CONFIG_266MHz)
 290 #define CFG_HRCW_MASTER         (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
 291                                                               HRCW_MODCK_H0111)
 292 #elif defined(CONFIG_300MHz)
 293 #define CFG_HRCW_MASTER         (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
 294                                                               HRCW_MODCK_H0110)
 295 #else
 296 #define CFG_HRCW_MASTER         (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
 297 #endif
 298
 299 /* no slaves so just fill with zeros */
 300 #define CFG_HRCW_SLAVE1         0
 301 #define CFG_HRCW_SLAVE2         0
 302 #define CFG_HRCW_SLAVE3         0
 303 #define CFG_HRCW_SLAVE4         0
 304 #define CFG_HRCW_SLAVE5         0
 305 #define CFG_HRCW_SLAVE6         0
 306 #define CFG_HRCW_SLAVE7         0
 307
 308 /*-----------------------------------------------------------------------
 309  * Internal Memory Mapped Register
 310  */
 311 #define CFG_IMMR                0xFFF00000
 312
 313 /*-----------------------------------------------------------------------
 314  * Definitions for initial stack pointer and data area (in DPRAM)
 315  */
 316 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 317 #define CFG_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
 318 #define CFG_GBL_DATA_SIZE       128 /* size in bytes reserved for initial data*/
 319 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 320 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 321
 322 /*-----------------------------------------------------------------------
 323  * Start addresses for the final memory configuration
 324  * (Set up by the startup code)
 325  * Please note that CFG_SDRAM_BASE _must_ start at 0
 326  *
 327  * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
 328  * is mapped at SDRAM_BASE2_PRELIM.
 329  */
 330 #define CFG_SDRAM_BASE          0x00000000
 331 #define CFG_FLASH_BASE          CFG_FLASH0_BASE
 332 #define CFG_MONITOR_BASE        TEXT_BASE
 333 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor */
 334 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()*/
 335
 336 /*
 337  * Internal Definitions
 338  *
 339  * Boot Flags
 340  */
 341 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH*/
 342 #define BOOTFLAG_WARM           0x02    /* Software reboot                 */
 343
 344
 345 /*-----------------------------------------------------------------------
 346  * Hardware Information Block
 347  */
 348 #define CFG_HWINFO_OFFSET       0x0003FFC0      /* offset of HW Info block */
 349 #define CFG_HWINFO_SIZE         0x00000040      /* size   of HW Info block */
 350 #define CFG_HWINFO_MAGIC        0x54514D38      /* 'TQM8' */
 351
 352 /*-----------------------------------------------------------------------
 353  * Cache Configuration
 354  */
 355 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 356 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 357 # define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 358 #endif
 359
 360 /*-----------------------------------------------------------------------
 361  * HIDx - Hardware Implementation-dependent Registers                    2-11
 362  *-----------------------------------------------------------------------
 363  * HID0 also contains cache control - initially enable both caches and
 364  * invalidate contents, then the final state leaves only the instruction
 365  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 366  * but Soft reset does not.
 367  *
 368  * HID1 has only read-only information - nothing to set.
 369  */
 370 #define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 371                                 HID0_IFEM|HID0_ABE)
 372 #define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
 373 #define CFG_HID2        0
 374
 375 /*-----------------------------------------------------------------------
 376  * RMR - Reset Mode Register                                     5-5
 377  *-----------------------------------------------------------------------
 378  * turn on Checkstop Reset Enable
 379  */
 380 #define CFG_RMR         RMR_CSRE
 381
 382 /*-----------------------------------------------------------------------
 383  * BCR - Bus Configuration                                       4-25
 384  *-----------------------------------------------------------------------
 385  */
 386 #ifdef  CONFIG_BUSMODE_60x
 387 #define CFG_BCR         (BCR_EBM|BCR_L2C|BCR_LETM|\
 388                          BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode  */
 389 #else
 390 #define BCR_APD01       0x10000000
 391 #define CFG_BCR         (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
 392 #endif
 393
 394 /*-----------------------------------------------------------------------
 395  * SIUMCR - SIU Module Configuration                             4-31
 396  *-----------------------------------------------------------------------
 397  */
 398 #if 0
 399 #define CFG_SIUMCR      (SIUMCR_DPPC10|SIUMCR_APPC10)
 400 #else
 401 #define CFG_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10)
 402 #endif
 403
 404
 405 /*-----------------------------------------------------------------------
 406  * SYPCR - System Protection Control                             4-35
 407  * SYPCR can only be written once after reset!
 408  *-----------------------------------------------------------------------
 409  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 410  */
 411 #if defined(CONFIG_WATCHDOG)
 412 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 413                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 414 #else
 415 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 416                          SYPCR_SWRI|SYPCR_SWP)
 417 #endif /* CONFIG_WATCHDOG */
 418
 419 /*-----------------------------------------------------------------------
 420  * TMCNTSC - Time Counter Status and Control                     4-40
 421  *-----------------------------------------------------------------------
 422  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 423  * and enable Time Counter
 424  */
 425 #define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 426
 427 /*-----------------------------------------------------------------------
 428  * PISCR - Periodic Interrupt Status and Control                 4-42
 429  *-----------------------------------------------------------------------
 430  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 431  * Periodic timer
 432  */
 433 #define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 434
 435 /*-----------------------------------------------------------------------
 436  * SCCR - System Clock Control                                   9-8
 437  *-----------------------------------------------------------------------
 438  * Ensure DFBRG is Divide by 16
 439  */
 440 #define CFG_SCCR        0
 441
 442 /*-----------------------------------------------------------------------
 443  * RCCR - RISC Controller Configuration                         13-7
 444  *-----------------------------------------------------------------------
 445  */
 446 #define CFG_RCCR        0
 447
 448 /*
 449  * Init Memory Controller:
 450  *
 451  * Bank Bus     Machine PortSz  Device
 452  * ---- ---     ------- ------  ------
 453  *  0   60x     GPCM    64 bit  FLASH
 454  *  1   60x     SDRAM   64 bit  SDRAM
 455  *  2   Local   SDRAM   32 bit  SDRAM
 456  *
 457  */
 458
 459         /* Initialize SDRAM on local bus
 460          */
 461 #define CFG_INIT_LOCAL_SDRAM
 462
 463 #define SDRAM_MAX_SIZE  0x08000000      /* max. 128 MB          */
 464
 465 /* Minimum mask to separate preliminary
 466  * address ranges for CS[0:2]
 467  */
 468 #define CFG_GLOBAL_SDRAM_LIMIT  (512<<20)       /* less than 512 MB */
 469 #define CFG_LOCAL_SDRAM_LIMIT   (128<<20)       /* less than 128 MB */
 470
 471 #define CFG_MPTPR       0x4000
 472
 473 /*-----------------------------------------------------------------------------
 474  * Address for Mode Register Set (MRS) command
 475  *-----------------------------------------------------------------------------
 476  * In fact, the address is rather configuration data presented to the SDRAM on
 477  * its address lines. Because the address lines may be mux'ed externally either
 478  * for 8 column or 9 column devices, some bits appear twice in the 8260's
 479  * address:
 480  *
 481  * |   (RFU)   |   (RFU)   | WBL |    TM    |     CL    |  BT | Burst Length |
 482  * | BA1   BA0 | A12 : A10 |  A9 |  A8   A7 |  A6 : A4  |  A3 |   A2 :  A0   |
 483  *  8 columns mux'ing:     |  A9 | A10  A21 | A22 : A24 | A25 |  A26 : A28   |
 484  *  9 columns mux'ing:     |  A8 | A20  A21 | A22 : A24 | A25 |  A26 : A28   |
 485  *  Settings:              |  0  |  0    0  |  0  1  0  |  0  |   0  1  0    |
 486  *-----------------------------------------------------------------------------
 487  */
 488 #define CFG_MRS_OFFS    0x00000110
 489
 490
 491 /* Bank 0 - FLASH
 492  */
 493 #define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
 494                          BRx_PS_64                      |\
 495                          BRx_MS_GPCM_P                  |\
 496                          BRx_V)
 497
 498 #define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH_SIZE)      |\
 499                          ORxG_CSNT                      |\
 500                          ORxG_ACS_DIV1                  |\
 501                          ORxG_SCY_3_CLK                 |\
 502                          ORxG_EHTR                      |\
 503                          ORxG_TRLX)
 504
 505         /* SDRAM on TQM8260 can have either 8 or 9 columns.
 506          * The number affects configuration values.
 507          */
 508
 509 /* Bank 1 - 60x bus SDRAM
 510  */
 511 #define CFG_PSRT        0x20
 512 #define CFG_LSRT        0x20
 513 #ifndef CFG_RAMBOOT
 514 #define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
 515                          BRx_PS_64                      |\
 516                          BRx_MS_SDRAM_P                 |\
 517                          BRx_V)
 518
 519 #define CFG_OR1_PRELIM  CFG_OR1_8COL
 520
 521
 522         /* SDRAM initialization values for 8-column chips
 523          */
 524 #define CFG_OR1_8COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 525                          ORxS_BPD_4                     |\
 526                          ORxS_ROWST_PBI1_A7             |\
 527                          ORxS_NUMR_12)
 528
 529 #define CFG_PSDMR_8COL  (PSDMR_PBI                      |\
 530                          PSDMR_SDAM_A15_IS_A5           |\
 531                          PSDMR_BSMA_A12_A14             |\
 532                          PSDMR_SDA10_PBI1_A8            |\
 533                          PSDMR_RFRC_7_CLK               |\
 534                          PSDMR_PRETOACT_2W              |\
 535                          PSDMR_ACTTORW_2W               |\
 536                          PSDMR_LDOTOPRE_1C              |\
 537                          PSDMR_WRC_2C                   |\
 538                          PSDMR_EAMUX                    |\
 539                          PSDMR_CL_2)
 540
 541         /* SDRAM initialization values for 9-column chips
 542          */
 543 #define CFG_OR1_9COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 544                          ORxS_BPD_4                     |\
 545                          ORxS_ROWST_PBI1_A5             |\
 546                          ORxS_NUMR_13)
 547
 548 #define CFG_PSDMR_9COL  (PSDMR_PBI                      |\
 549                          PSDMR_SDAM_A16_IS_A5           |\
 550                          PSDMR_BSMA_A12_A14             |\
 551                          PSDMR_SDA10_PBI1_A7            |\
 552                          PSDMR_RFRC_7_CLK               |\
 553                          PSDMR_PRETOACT_2W              |\
 554                          PSDMR_ACTTORW_2W               |\
 555                          PSDMR_LDOTOPRE_1C              |\
 556                          PSDMR_WRC_2C                   |\
 557                          PSDMR_EAMUX                    |\
 558                          PSDMR_CL_2)
 559
 560 /* Bank 2 - Local bus SDRAM
 561  */
 562 #ifdef CFG_INIT_LOCAL_SDRAM
 563 #define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
 564                          BRx_PS_32                      |\
 565                          BRx_MS_SDRAM_L                 |\
 566                          BRx_V)
 567
 568 #define CFG_OR2_PRELIM  CFG_OR2_8COL
 569
 570 #define SDRAM_BASE2_PRELIM      0x80000000
 571
 572         /* SDRAM initialization values for 8-column chips
 573          */
 574 #define CFG_OR2_8COL    ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 575                          ORxS_BPD_4                     |\
 576                          ORxS_ROWST_PBI1_A8             |\
 577                          ORxS_NUMR_12)
 578
 579 #define CFG_LSDMR_8COL  (PSDMR_PBI                      |\
 580                          PSDMR_SDAM_A15_IS_A5           |\
 581                          PSDMR_BSMA_A13_A15             |\
 582                          PSDMR_SDA10_PBI1_A9            |\
 583                          PSDMR_RFRC_7_CLK               |\
 584                          PSDMR_PRETOACT_2W              |\
 585                          PSDMR_ACTTORW_2W               |\
 586                          PSDMR_BL                       |\
 587                          PSDMR_LDOTOPRE_1C              |\
 588                          PSDMR_WRC_2C                   |\
 589                          PSDMR_CL_2)
 590
 591         /* SDRAM initialization values for 9-column chips
 592          */
 593 #define CFG_OR2_9COL    ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 594                          ORxS_BPD_4                     |\
 595                          ORxS_ROWST_PBI1_A6             |\
 596                          ORxS_NUMR_13)
 597
 598 #define CFG_LSDMR_9COL  (PSDMR_PBI                      |\
 599                          PSDMR_SDAM_A16_IS_A5           |\
 600                          PSDMR_BSMA_A13_A15             |\
 601                          PSDMR_SDA10_PBI1_A8            |\
 602                          PSDMR_RFRC_7_CLK               |\
 603                          PSDMR_PRETOACT_2W              |\
 604                          PSDMR_ACTTORW_2W               |\
 605                          PSDMR_BL                       |\
 606                          PSDMR_LDOTOPRE_1C              |\
 607                          PSDMR_WRC_2C                   |\
 608                          PSDMR_CL_2)
 609
 610 #endif /* CFG_INIT_LOCAL_SDRAM */
 611
 612 #endif /* CFG_RAMBOOT */
 613
 614 #define CFG_CAN0_BASE           0xc0000000
 615 #define CFG_CAN1_BASE           0xc0008000
 616 #define CFG_FIOX_BASE           0xc0010000
 617 #define CFG_FDOHM_BASE          0xc0018000
 618 #define CFG_EXTPROM_BASE        0xc2000000
 619
 620 #define CFG_CAN_SIZE            0x00000100
 621 #define CFG_FIOX_SIZE           0x00000020
 622 #define CFG_FDOHM_SIZE          0x00002000
 623 #define CFG_EXTPROM_BANK_SIZE   0x01000000
 624
 625 #define EXT_EEPROM_MAX_FLASH_BANKS      0x02
 626
 627 /* CS3 - CAN 0
 628  */
 629 #define CFG_CAN0_BR3   ((CFG_CAN0_BASE & BRx_BA_MSK)    |\
 630                         BRx_PS_8                        |\
 631                         BRx_MS_UPMA                     |\
 632                         BRx_V)
 633
 634 #define CFG_CAN0_OR3   (P2SZ_TO_AM(CFG_CAN_SIZE)        |\
 635                         ORxU_BI                         |\
 636                         ORxU_EHTR_4IDLE)
 637
 638 /* CS4 - CAN 1
 639  */
 640 #define CFG_CAN1_BR4   ((CFG_CAN1_BASE & BRx_BA_MSK)    |\
 641                         BRx_PS_8                        |\
 642                         BRx_MS_UPMA                     |\
 643                         BRx_V)
 644
 645 #define CFG_CAN1_OR4   (P2SZ_TO_AM(CFG_CAN_SIZE)        |\
 646                         ORxU_BI                         |\
 647                         ORxU_EHTR_4IDLE)
 648
 649 /* CS5 - Extended PROM (16MB optional)
 650  */
 651 #define CFG_EXTPROM_BR5 ((CFG_EXTPROM_BASE & BRx_BA_MSK)|\
 652                         BRx_PS_32                       |\
 653                         BRx_MS_GPCM_P                   |\
 654                         BRx_V)
 655
 656 #define CFG_EXTPROM_OR5 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\
 657                         ORxG_CSNT                       |\
 658                         ORxG_ACS_DIV4                   |\
 659                         ORxG_SCY_5_CLK                  |\
 660                         ORxG_TRLX)
 661
 662 /* CS6 - Extended PROM (16MB optional)
 663  */
 664 #define CFG_EXTPROM_BR6 (((CFG_EXTPROM_BASE + \
 665                         CFG_EXTPROM_BANK_SIZE) & BRx_BA_MSK)|\
 666                         BRx_PS_32                       |\
 667                         BRx_MS_GPCM_P                   |\
 668                         BRx_V)
 669
 670 #define CFG_EXTPROM_OR6 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\
 671                         ORxG_CSNT                       |\
 672                         ORxG_ACS_DIV4                   |\
 673                         ORxG_SCY_5_CLK                  |\
 674                         ORxG_TRLX)
 675
 676 /* CS7 - FPGA FIOX: Glue Logic
 677  */
 678 #define CFG_FIOX_BR7   ((CFG_FIOX_BASE & BRx_BA_MSK)    |\
 679                         BRx_PS_32                       |\
 680                         BRx_MS_GPCM_P                   |\
 681                         BRx_V)
 682
 683 #define CFG_FIOX_OR7   (P2SZ_TO_AM(CFG_FIOX_SIZE)       |\
 684                         ORxG_ACS_DIV4                   |\
 685                         ORxG_SCY_5_CLK                  |\
 686                         ORxG_TRLX)
 687
 688 /* CS8 - FPGA DOH Master
 689  */
 690 #define CFG_FDOHM_BR8  ((CFG_FDOHM_BASE & BRx_BA_MSK)   |\
 691                         BRx_PS_16                       |\
 692                         BRx_MS_GPCM_P                   |\
 693                         BRx_V)
 694
 695 #define CFG_FDOHM_OR8  (P2SZ_TO_AM(CFG_FDOHM_SIZE)      |\
 696                         ORxG_ACS_DIV4                   |\
 697                         ORxG_SCY_5_CLK                  |\
 698                         ORxG_TRLX)
 699
 700
 701 /* FPGA configuration */
 702 #define CFG_PD_FIOX_PROG        (1 << (31- 5))  /* PD  5 */
 703 #define CFG_PD_FIOX_DONE        (1 << (31-28))  /* PD 28 */
 704 #define CFG_PD_FIOX_INIT        (1 << (31-29))  /* PD 29 */
 705
 706 #define CFG_PD_FDOHM_PROG       (1 << (31- 4))  /* PD  4 */
 707 #define CFG_PD_FDOHM_DONE       (1 << (31-26))  /* PD 26 */
 708 #define CFG_PD_FDOHM_INIT       (1 << (31-27))  /* PD 27 */
 709
 710
 711 #endif  /* __CONFIG_H */