include/configs/SIMPC8313.h

   1 /*
   2  * Copyright (C) Sheldon Instruments, Inc. 2008
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22 /*
  23  * simpc8313 board configuration file
  24  */
  25
  26 #ifndef __CONFIG_H
  27 #define __CONFIG_H
  28
  29 /*
  30  * High Level Configuration Options
  31  */
  32 #define CONFIG_NAND_U_BOOT
  33
  34 #define CONFIG_E300                     1
  35 #define CONFIG_MPC83xx                  1
  36 #define CONFIG_MPC831x                  1
  37 #define CONFIG_MPC8313                  1
  38
  39 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (512 << 10)
  40 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00100000
  41 #define CONFIG_SYS_NAND_U_BOOT_START    0x00100100
  42 #define CONFIG_SYS_NAND_U_BOOT_RELOC    0x00010000
  43 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
  44
  45 #define CONFIG_SYS_TEXT_BASE    0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
  46 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
  47
  48 #ifdef CONFIG_NAND_SPL
  49 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
  50 #else
  51 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  52 #endif
  53
  54 #define CONFIG_PCI
  55 #define CONFIG_FSL_ELBC                 1
  56
  57 #define CONFIG_MISC_INIT_R
  58
  59 /*
  60  * On-board devices
  61  *
  62  * TSEC1 is Marvell PHY 88E1118
  63  */
  64
  65 #define CONFIG_SYS_33MHZ
  66
  67 #define CONFIG_83XX_CLKIN               33333333        /* in Hz */
  68
  69 #define CONFIG_SYS_CLK_FREQ             CONFIG_83XX_CLKIN
  70
  71 #define CONFIG_SYS_IMMR                 0xE0000000
  72
  73 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  74 #define CONFIG_DEFAULT_IMMR             CONFIG_SYS_IMMR
  75 #endif
  76
  77 #define CONFIG_SYS_MEMTEST_START        0x00001000
  78 #define CONFIG_SYS_MEMTEST_END          0x07f00000
  79
  80 #define CONFIG_SYS_ACR_PIPE_DEP         3       /* Arbiter pipeline depth (0-3) */
  81 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
  82
  83 /*
  84  * Device configurations
  85  */
  86 #define CONFIG_TSEC1
  87
  88 /*
  89  * DDR Setup
  90  */
  91 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is system memory*/
  92 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  93 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  94
  95 #define CONFIG_VERY_BIG_RAM
  96 #define CONFIG_MAX_MEM_MAPPED           (512 << 20)
  97
  98 #define CONFIG_SYS_DDRCDR               ( DDRCDR_EN \
  99                                         | DDRCDR_PZ_NOMZ \
 100                                         | DDRCDR_NZ_NOMZ \
 101                                         | DDRCDR_M_ODR )
 102                                         /* 0x73000002 TODO ODR & DRN ? */
 103
 104 /*
 105  * FLASH on the Local Bus
 106  */
 107 #define CONFIG_SYS_NO_FLASH
 108
 109 #if !defined(CONFIG_NAND_SPL)
 110 #define CONFIG_SYS_RAMBOOT
 111 #endif
 112
 113 #define CONFIG_SYS_INIT_RAM_LOCK        1
 114 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM address */
 115 #define CONFIG_SYS_INIT_RAM_SIZE                0x1000          /* Size of used area in RAM*/
 116
 117 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 118 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 119
 120 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 121 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 122 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)    /* Reserved for malloc */
 123
 124 /*
 125  * Local Bus LCRR and LBCR regs
 126  */
 127 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 128 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_1
 129 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_2
 130 #define CONFIG_SYS_LBC_LBCR     (0x00040000 /* TODO */ \
 131                                 | (0xFF << LBCR_BMT_SHIFT) \
 132                                 | 0xF ) /* 0x0004ff0f */
 133
 134 #define CONFIG_SYS_LBC_MRTPR    0x20000000      /* LB refresh timer prescal, 266MHz/32 */
 135
 136 /* drivers/mtd/nand/nand.c */
 137 #ifdef CONFIG_NAND_SPL
 138 #define CONFIG_SYS_NAND_BASE            0xFFF00000
 139 #else
 140 #define CONFIG_SYS_NAND_BASE            0xE2800000
 141 #endif
 142 #define CONFIG_SYS_FPGA_BASE            0xFF000000
 143
 144 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 145 #define NAND_MAX_CHIPS                  1
 146 #define CONFIG_MTD_NAND_VERIFY_WRITE
 147 #define CONFIG_CMD_NAND                 1
 148 #define CONFIG_NAND_FSL_ELBC            1
 149
 150 #define CONFIG_SYS_NAND_BR_PRELIM       ( CONFIG_SYS_NAND_BASE \
 151                                         | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 152                                         | BR_PS_8               /* Port Size = 8 bit */ \
 153                                         | BR_MS_FCM             /* MSEL = FCM */ \
 154                                         | BR_V )                /* valid */
 155
 156 #ifdef CONFIG_NAND_SP
 157 #define CONFIG_SYS_NAND_OR_PRELIM       ( 0xFFFF8000    /* length 32K */ \
 158                                         | OR_FCM_CSCT \
 159                                         | OR_FCM_CST \
 160                                         | OR_FCM_CHT \
 161                                         | OR_FCM_SCY_1 \
 162                                         | OR_FCM_TRLX \
 163                                         | OR_FCM_EHTR )
 164 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x8000000E      /* 32KB */
 165 #define CONFIG_SYS_NAND_PAGE_SIZE       (512)           /* NAND chip page size */
 166 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 << 10)      /* NAND chip block size */
 167 #define NAND_CACHE_PAGES                32
 168 #elif defined(CONFIG_NAND_LP)
 169 #define CONFIG_SYS_NAND_OR_PRELIM       ( 0xFFFC0000    /* length 256K */ \
 170                                         | OR_FCM_PGS \
 171                                         | OR_FCM_CSCT \
 172                                         | OR_FCM_CST \
 173                                         | OR_FCM_CHT \
 174                                         | OR_FCM_SCY_1 \
 175                                         | OR_FCM_TRLX \
 176                                         | OR_FCM_EHTR )
 177 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000011      /* 256KB */
 178 #define CONFIG_SYS_NAND_PAGE_SIZE       (2048)          /* NAND chip page size */
 179 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)     /* NAND chip block size */
 180 #define NAND_CACHE_PAGES                64
 181 #else
 182 #error Page size of NAND not defined.
 183 #endif /* CONFIG_NAND_SP */
 184
 185 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SYS_NAND_BLOCK_SIZE
 186
 187 #define CONFIG_SYS_BR0_PRELIM           CONFIG_SYS_NAND_BR_PRELIM
 188 #define CONFIG_SYS_OR0_PRELIM           CONFIG_SYS_NAND_OR_PRELIM
 189
 190 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_NAND_BASE
 191
 192 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM
 193 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM  CONFIG_SYS_LBLAWAR0_PRELIM
 194
 195 #define CONFIG_SYS_BR1_PRELIM           ( CONFIG_SYS_FPGA_BASE \
 196                                         | BR_PS_16 \
 197                                         | BR_MS_UPMA \
 198                                         | BR_V )
 199 #define CONFIG_SYS_OR1_PRELIM           ( OR_AM_2MB \
 200                                         | OR_UPM_BCTLD)
 201
 202 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_FPGA_BASE
 203 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_2MB)
 204
 205 /*
 206  * JFFS2 configuration
 207  */
 208 #define CONFIG_JFFS2_NAND
 209 #define CONFIG_JFFS2_DEV        "nand0"
 210
 211 /* mtdparts command line support */
 212 #define CONFIG_CMD_MTDPARTS
 213 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 214 #define MTDIDS_DEFAULT          "nand0=nand0"
 215 #define MTDPARTS_DEFAULT        "mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)"
 216
 217 /* pass open firmware flat tree */
 218 #define CONFIG_OF_LIBFDT                1
 219 #define CONFIG_OF_BOARD_SETUP           1
 220 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 221
 222 /*
 223  * Serial Port
 224  */
 225 #define CONFIG_CONS_INDEX               1
 226 #define CONFIG_SYS_NS16550
 227 #define CONFIG_SYS_NS16550_SERIAL
 228 #define CONFIG_SYS_NS16550_REG_SIZE     1
 229 #ifdef CONFIG_NAND_SPL
 230 #define CONFIG_NS16550_MIN_FUNCTIONS
 231 #endif
 232
 233 #define CONFIG_SYS_BAUDRATE_TABLE       \
 234         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 235
 236 #define CONFIG_SYS_NS16550_COM1         (CONFIG_SYS_IMMR+0x4500)
 237 #define CONFIG_SYS_NS16550_COM2         (CONFIG_SYS_IMMR+0x4600)
 238
 239 /* Use the HUSH parser */
 240 #define CONFIG_SYS_HUSH_PARSER
 241 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 242
 243 /* I2C */
 244 #define CONFIG_HARD_I2C                 /* I2C with hardware support*/
 245 #define CONFIG_FSL_I2C
 246 #define CONFIG_I2C_MULTI_BUS
 247 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 248 #define CONFIG_SYS_I2C_SLAVE            0x7F
 249 #define CONFIG_SYS_I2C_NOPROBES         {{0,0x69}} /* Don't probe these addrs */
 250 #define CONFIG_SYS_I2C_OFFSET           0x3000
 251 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 252
 253 /*
 254  * General PCI
 255  * Addresses are mapped 1-1.
 256  */
 257 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 258 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 259 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 260 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 261 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 262 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 263 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 264 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 265 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 266
 267 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 268 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1057  /* Motorola */
 269
 270 /*
 271  * TSEC
 272  */
 273 #define CONFIG_TSEC_ENET                /* TSEC ethernet support */
 274
 275 #define CONFIG_NET_MULTI
 276 #define CONFIG_GMII                     /* MII PHY management */
 277
 278 #ifdef CONFIG_TSEC1
 279 #define CONFIG_HAS_ETH0
 280 #define CONFIG_TSEC1_NAME               "TSEC0"
 281 #define CONFIG_SYS_TSEC1_OFFSET         0x24000
 282 #define TSEC1_PHY_ADDR                  0x0
 283 #define TSEC1_FLAGS                     TSEC_GIGABIT
 284 #define TSEC1_PHYIDX                    0
 285 #endif
 286
 287 #ifdef CONFIG_TSEC2
 288 #define CONFIG_HAS_ETH1
 289 #define CONFIG_TSEC2_NAME               "TSEC1"
 290 #define CONFIG_SYS_TSEC2_OFFSET         0x25000
 291 #define TSEC2_PHY_ADDR                  4
 292 #define TSEC2_FLAGS                     TSEC_GIGABIT
 293 #define TSEC2_PHYIDX                    0
 294 #endif
 295
 296
 297 /* Options are: TSEC[0-1] */
 298 #define CONFIG_ETHPRIME                 "TSEC1"
 299
 300 /*
 301  * Configure on-board RTC
 302  */
 303 #define CONFIG_RTC_DS1337
 304 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 305
 306 /*
 307  * Environment
 308  */
 309 #if defined(CONFIG_NAND_U_BOOT)
 310         #define CONFIG_ENV_IS_IN_NAND           1
 311         #define CONFIG_ENV_OFFSET               (768 * 1024)
 312         #define CONFIG_ENV_SECT_SIZE            CONFIG_SYS_NAND_BLOCK_SIZE
 313         #define CONFIG_ENV_SIZE                 CONFIG_ENV_SECT_SIZE
 314         #define CONFIG_ENV_SIZE_REDUND          CONFIG_ENV_SIZE
 315         #define CONFIG_ENV_RANGE                (CONFIG_ENV_SECT_SIZE * 4)
 316         #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
 317 #elif !defined(CONFIG_SYS_RAMBOOT)
 318         #define CONFIG_ENV_IS_IN_FLASH          1
 319         #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 320         #define CONFIG_ENV_SECT_SIZE            0x10000 /* 64K(one sector) for env */
 321         #define CONFIG_ENV_SIZE                 0x2000
 322
 323 /* Address and size of Redundant Environment Sector */
 324 #else
 325         #define CONFIG_ENV_IS_NOWHERE           1       /* Store ENV in memory only */
 326         #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE - 0x1000)
 327         #define CONFIG_ENV_SIZE                 0x2000
 328 #endif
 329
 330 #define CONFIG_LOADS_ECHO                       1       /* echo on for serial download */
 331 #define CONFIG_SYS_LOADS_BAUD_CHANGE            1       /* allow baudrate change */
 332
 333 /*
 334  * BOOTP options
 335  */
 336 #define CONFIG_BOOTP_BOOTFILESIZE
 337 #define CONFIG_BOOTP_BOOTPATH
 338 #define CONFIG_BOOTP_GATEWAY
 339 #define CONFIG_BOOTP_HOSTNAME
 340
 341
 342 /*
 343  * Command line configuration.
 344  */
 345 #include <config_cmd_default.h>
 346 #undef CONFIG_CMD_IMLS
 347 #undef CONFIG_CMD_FLASH
 348
 349 #define CONFIG_CMD_PING
 350 #define CONFIG_CMD_DHCP
 351 #define CONFIG_CMD_I2C
 352 #define CONFIG_CMD_MII
 353 #define CONFIG_CMD_DATE
 354 #define CONFIG_CMD_PCI
 355 #define CONFIG_CMD_JFFS2
 356
 357 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
 358         #undef CONFIG_CMD_SAVEENV
 359         #undef CONFIG_CMD_LOADS
 360 #endif
 361
 362 #define CONFIG_CMDLINE_EDITING          1
 363 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
 364
 365 /*
 366  * Miscellaneous configurable options
 367  */
 368 #define CONFIG_SYS_LONGHELP                             /* undef to save memory */
 369 #define CONFIG_SYS_LOAD_ADDR            0x2000000       /* default load address */
 370 #define CONFIG_SYS_PROMPT               "=> "           /* Monitor Command Prompt */
 371 #define CONFIG_SYS_CBSIZE               1024            /* Console I/O Buffer Size */
 372
 373 #define CONFIG_SYS_PBSIZE               ( CONFIG_SYS_CBSIZE             \
 374                                         + sizeof(CONFIG_SYS_PROMPT)     \
 375                                         + 16 )  /* Print Buffer Size */
 376 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 377 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 378 #define CONFIG_SYS_HZ                   1000            /* decrementer freq: 1ms ticks */
 379
 380 /*
 381  * For booting Linux, the board info and command line data
 382  * have to be in the first 256 MB of memory, since this is
 383  * the maximum mapped by the Linux kernel during initialization.
 384  */
 385 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)     /* Initial Memory map for Linux*/
 386
 387 #define CONFIG_SYS_RCWH_PCIHOST         0x80000000      /* PCIHOST */
 388
 389 #define CONFIG_SYS_HRCW_LOW             ( HRCWL_LCL_BUS_TO_SCB_CLK_1X1  \
 390                                         | 0x20000000 /* reserved */     \
 391                                         | HRCWL_DDR_TO_SCB_CLK_2X1      \
 392                                         | HRCWL_CSB_TO_CLKIN_4X1        \
 393                                         | HRCWL_CORE_TO_CSB_2_5X1 )
 394
 395 #define CONFIG_SYS_NS16550_CLK          (CONFIG_83XX_CLKIN * 4)
 396
 397 #define CONFIG_SYS_HRCW_HIGH_BASE       ( HRCWH_PCI_HOST                \
 398                                         | HRCWH_PCI1_ARBITER_ENABLE     \
 399                                         | HRCWH_CORE_ENABLE             \
 400                                         | HRCWH_BOOTSEQ_DISABLE         \
 401                                         | HRCWH_SW_WATCHDOG_DISABLE     \
 402                                         | HRCWH_TSEC1M_IN_RGMII         \
 403                                         | HRCWH_TSEC2M_IN_RGMII         \
 404                                         | HRCWH_BIG_ENDIAN              \
 405                                         | HRCWH_LALE_NORMAL )
 406
 407 #ifdef CONFIG_NAND_LP
 408 #define CONFIG_SYS_HRCW_HIGH    ( CONFIG_SYS_HRCW_HIGH_BASE             \
 409                                 | HRCWH_FROM_0XFFF00100                 \
 410                                 | HRCWH_ROM_LOC_NAND_LP_8BIT            \
 411                                 | HRCWH_RL_EXT_NAND)
 412 #else
 413 #define CONFIG_SYS_HRCW_HIGH    ( CONFIG_SYS_HRCW_HIGH_BASE             \
 414                                 | HRCWH_FROM_0XFFF00100                 \
 415                                 | HRCWH_ROM_LOC_NAND_SP_8BIT            \
 416                                 | HRCWH_RL_EXT_NAND )
 417 #endif
 418
 419 /* System IO Config */
 420 #define CONFIG_SYS_SICRH        ( SICRH_ETSEC2_B        \
 421                                 | SICRH_ETSEC2_C        \
 422                                 | SICRH_ETSEC2_D        \
 423                                 | SICRH_ETSEC2_E        \
 424                                 | SICRH_ETSEC2_F        \
 425                                 | SICRH_ETSEC2_G        \
 426                                 | SICRH_TSOBI1          \
 427                                 | SICRH_TSOBI2 )
 428 #define CONFIG_SYS_SICRL        ( SICRL_LBC             \
 429                                 | SICRL_USBDR_10        \
 430                                 | SICRL_ETSEC2_A )
 431
 432 #define CONFIG_SYS_HID0_INIT    0x000000000
 433 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 434                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 435                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT )
 436
 437 #define CONFIG_SYS_HID2         HID2_HBE
 438
 439 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 440
 441 /* DDR @ 0x00000000 */
 442 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
 443 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 444 #define CONFIG_SYS_IBAT1L       ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATL_PP_10)
 445 #define CONFIG_SYS_IBAT1U       ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATU_BL_256M | BATU_VS | BATU_VP)
 446
 447 /* PCI @ 0x80000000 */
 448 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
 449 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 450 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 451 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 452
 453 /* PCI2 not supported on 8313 */
 454 #define CONFIG_SYS_IBAT4L       (0)
 455 #define CONFIG_SYS_IBAT4U       (0)
 456
 457 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
 458 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 459 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 460
 461 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 462 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
 463 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 464
 465 #define CONFIG_SYS_IBAT7L       (0)
 466 #define CONFIG_SYS_IBAT7U       (0)
 467
 468 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 469 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 470 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 471 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 472 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 473 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 474 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 475 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 476 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 477 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 478 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 479 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 480 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 481 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 482 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 483 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 484
 485 /*
 486  * Environment Configuration
 487  */
 488 #define CONFIG_ENV_OVERWRITE
 489
 490 #define CONFIG_NETDEV           eth1
 491
 492 #define CONFIG_HOSTNAME         simpc8313
 493 #define CONFIG_ROOTPATH         /tftpboot/
 494 #define CONFIG_BOOTFILE         /tftpboot/uImage
 495 #define CONFIG_UBOOTPATH        u-boot-nand.bin /* U-Boot image on TFTP server */
 496 #define CONFIG_FDTFILE          simpc8313.dtb
 497
 498 #define CONFIG_LOADADDR         500000  /* default location for tftp and bootm */
 499 #define CONFIG_BOOTDELAY        5       /* 5 second delay */
 500 #define CONFIG_BAUDRATE         115200
 501
 502 #define CONFIG_BOOTCOMMAND      "nand read $loadaddr kernel 600000;bootm $loadaddr - $fdtaddr"
 503
 504 #define XMK_STR(x)      #x
 505 #define MK_STR(x)       XMK_STR(x)
 506
 507 #define CONFIG_EXTRA_ENV_SETTINGS \
 508         "netdev=" MK_STR(CONFIG_NETDEV) "\0"                            \
 509         "ethprime=TSEC1\0"                                              \
 510         "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                          \
 511         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 512                 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "     \
 513                 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "           \
 514                 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "   \
 515                 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "              \
 516                 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"  \
 517         "fdtaddr=ae0000\0"                                              \
 518         "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"                          \
 519         "console=ttyS0\0"                                               \
 520         "setbootargs=setenv bootargs "                                  \
 521                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 522         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "         \
 523                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 524                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"    \
 525         "load_uboot=tftp 100000 u-boot-nand.bin\0"                      \
 526         "burn_uboot=nand erase u-boot 80000; "                          \
 527                 "nand write 100000 u-boot $filesize\0"                  \
 528         "update_uboot=run load_uboot;run burn_uboot\0"                  \
 529         "mtdids=nand0=nand0\0"                                          \
 530         "mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0"      \
 531         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 532                 "nfsroot=${serverip}:${rootpath}\0"                     \
 533         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 534         "addip=setenv bootargs ${bootargs} "                            \
 535                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 536                 ":${hostname}:${netdev}:off panic=1\0"                  \
 537         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"        \
 538         "bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw "             \
 539                 "console=ttyS0,115200\0"                                \
 540         ""
 541
 542 #define CONFIG_NFSBOOTCOMMAND                                           \
 543         "setenv rootdev /dev/nfs;"                                      \
 544         "run setbootargs;"                                              \
 545         "run setipargs;"                                                \
 546         "tftp $loadaddr $bootfile;"                                     \
 547         "tftp $fdtaddr $fdtfile;"                                       \
 548         "bootm $loadaddr - $fdtaddr"
 549
 550 #define CONFIG_RAMBOOTCOMMAND                                           \
 551         "setenv rootdev /dev/ram;"                                      \
 552         "run setbootargs;"                                              \
 553         "tftp $ramdiskaddr $ramdiskfile;"                               \
 554         "tftp $loadaddr $bootfile;"                                     \
 555         "tftp $fdtaddr $fdtfile;"                                       \
 556         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 557
 558 #undef MK_STR
 559 #undef XMK_STR
 560
 561 #endif  /* __CONFIG_H */