include/configs/SIMPC8313.h

   1 /*
   2  * Copyright (C) Sheldon Instruments, Inc. 2008
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22 /*
  23  * simpc8313 board configuration file
  24  */
  25
  26 #ifndef __CONFIG_H
  27 #define __CONFIG_H
  28
  29 /*
  30  * High Level Configuration Options
  31  */
  32 #define CONFIG_NAND_U_BOOT
  33
  34 #define CONFIG_E300                     1
  35 #define CONFIG_MPC83XX                  1
  36 #define CONFIG_MPC831X                  1
  37 #define CONFIG_MPC8313                  1
  38
  39 #define CONFIG_PCI
  40 #define CONFIG_83XX_GENERIC_PCI
  41
  42 #define CONFIG_MISC_INIT_R
  43
  44 /*
  45  * On-board devices
  46  *
  47  * TSEC1 is Marvell PHY 88E1118
  48  */
  49
  50 #define CONFIG_SYS_33MHZ
  51
  52 #define CONFIG_83XX_CLKIN               33333333        /* in Hz */
  53
  54 #define CONFIG_SYS_CLK_FREQ             CONFIG_83XX_CLKIN
  55
  56 #define CONFIG_SYS_IMMR                 0xE0000000
  57
  58 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  59 #define CONFIG_DEFAULT_IMMR             CONFIG_SYS_IMMR
  60 #endif
  61
  62 #define CONFIG_SYS_MEMTEST_START        0x00001000
  63 #define CONFIG_SYS_MEMTEST_END          0x07f00000
  64
  65 #define CONFIG_SYS_ACR_PIPE_DEP         3       /* Arbiter pipeline depth (0-3) */
  66 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count (0-7) */
  67
  68 /*
  69  * Device configurations
  70  */
  71 #define CONFIG_TSEC1
  72
  73 /*
  74  * DDR Setup
  75  */
  76 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is system memory*/
  77 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  78 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  79
  80 #define CONFIG_VERY_BIG_RAM
  81 #define CONFIG_MAX_MEM_MAPPED           (512 << 20)
  82
  83 #define CONFIG_SYS_DDRCDR               ( DDRCDR_EN \
  84                                         | DDRCDR_PZ_NOMZ \
  85                                         | DDRCDR_NZ_NOMZ \
  86                                         | DDRCDR_M_ODR )
  87                                         /* 0x73000002 TODO ODR & DRN ? */
  88
  89 /*
  90  * FLASH on the Local Bus
  91  */
  92 #define CONFIG_SYS_NO_FLASH
  93
  94 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
  95
  96 #if !defined(CONFIG_NAND_SPL)
  97 #define CONFIG_SYS_RAMBOOT
  98 #endif
  99
 100 #define CONFIG_SYS_INIT_RAM_LOCK        1
 101 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM address */
 102 #define CONFIG_SYS_INIT_RAM_END         0x1000          /* End of used area in RAM*/
 103
 104 #define CONFIG_SYS_GBL_DATA_SIZE        0x100           /* num bytes initial data */
 105 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 106 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 107
 108 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 109 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 110 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)    /* Reserved for malloc */
 111
 112 /*
 113  * Local Bus LCRR and LBCR regs
 114  */
 115 #define CONFIG_SYS_LCRR         (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2)
 116 #define CONFIG_SYS_LBC_LBCR     (0x00040000 /* TODO */ \
 117                                 | (0xFF << LBCR_BMT_SHIFT) \
 118                                 | 0xF ) /* 0x0004ff0f */
 119
 120 #define CONFIG_SYS_LBC_MRTPR    0x20000000      /* LB refresh timer prescal, 266MHz/32 */
 121
 122 /* drivers/mtd/nand/nand.c */
 123 #ifdef CONFIG_NAND_SPL
 124 #define CONFIG_SYS_NAND_BASE            0xFFF00000
 125 #else
 126 #define CONFIG_SYS_NAND_BASE            0xE2800000
 127 #endif
 128
 129 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 130 #define NAND_MAX_CHIPS                  1
 131 #define CONFIG_MTD_NAND_VERIFY_WRITE
 132 #define CONFIG_CMD_NAND                 1
 133 #define CONFIG_NAND_FSL_ELBC            1
 134
 135 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (512 << 10)
 136 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00100000
 137 #define CONFIG_SYS_NAND_U_BOOT_START    0x00100100
 138 #define CONFIG_SYS_NAND_U_BOOT_RELOC    0x00010000
 139
 140 #define CONFIG_SYS_NAND_BR_PRELIM       ( CONFIG_SYS_NAND_BASE \
 141                                         | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 142                                         | BR_PS_8               /* Port Size = 8 bit */ \
 143                                         | BR_MS_FCM             /* MSEL = FCM */ \
 144                                         | BR_V )                /* valid */
 145
 146 #ifdef CONFIG_NAND_SP
 147 #define CONFIG_SYS_NAND_OR_PRELIM       ( 0xFFFF8000    /* length 32K */ \
 148                                         | OR_FCM_CSCT \
 149                                         | OR_FCM_CST \
 150                                         | OR_FCM_CHT \
 151                                         | OR_FCM_SCY_1 \
 152                                         | OR_FCM_TRLX \
 153                                         | OR_FCM_EHTR )
 154 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x8000000E      /* 32KB */
 155 #define CONFIG_SYS_NAND_PAGE_SIZE       (512)           /* NAND chip page size */
 156 #define CONFIG_SYS_NAND_BLOCK_SIZE      (16 << 10)      /* NAND chip block size */
 157 #define NAND_CACHE_PAGES                32
 158 #elif defined(CONFIG_NAND_LP)
 159 #define CONFIG_SYS_NAND_OR_PRELIM       ( 0xFFFC0000    /* length 256K */ \
 160                                         | OR_FCM_PGS \
 161                                         | OR_FCM_CSCT \
 162                                         | OR_FCM_CST \
 163                                         | OR_FCM_CHT \
 164                                         | OR_FCM_SCY_1 \
 165                                         | OR_FCM_TRLX \
 166                                         | OR_FCM_EHTR )
 167 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000011      /* 256KB */
 168 #define CONFIG_SYS_NAND_PAGE_SIZE       (2048)          /* NAND chip page size */
 169 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)     /* NAND chip block size */
 170 #define NAND_CACHE_PAGES                64
 171 #else
 172 #error Page size of NAND not defined.
 173 #endif /* CONFIG_NAND_SP */
 174
 175 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SYS_NAND_BLOCK_SIZE
 176
 177 #define CONFIG_SYS_BR0_PRELIM           CONFIG_SYS_NAND_BR_PRELIM
 178 #define CONFIG_SYS_OR0_PRELIM           CONFIG_SYS_NAND_OR_PRELIM
 179
 180 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_NAND_BASE
 181
 182 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM
 183 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM  CONFIG_SYS_LBLAWAR0_PRELIM
 184
 185 /*
 186  * JFFS2 configuration
 187  */
 188 #define CONFIG_JFFS2_NAND
 189 #define CONFIG_JFFS2_DEV        "nand0"
 190
 191 /* mtdparts command line support */
 192 #define CONFIG_JFFS2_CMDLINE
 193 #define MTDIDS_DEFAULT          "nand0=nand0"
 194 #define MTDPARTS_DEFAULT        "mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)"
 195
 196 /* pass open firmware flat tree */
 197 #define CONFIG_OF_LIBFDT                1
 198 #define CONFIG_OF_BOARD_SETUP           1
 199 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 200
 201 /*
 202  * Serial Port
 203  */
 204 #define CONFIG_CONS_INDEX               1
 205 #define CONFIG_SYS_NS16550
 206 #define CONFIG_SYS_NS16550_SERIAL
 207 #define CONFIG_SYS_NS16550_REG_SIZE     1
 208
 209 #define CONFIG_SYS_BAUDRATE_TABLE       \
 210         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 211
 212 #define CONFIG_SYS_NS16550_COM1         (CONFIG_SYS_IMMR+0x4500)
 213 #define CONFIG_SYS_NS16550_COM2         (CONFIG_SYS_IMMR+0x4600)
 214
 215 /* Use the HUSH parser */
 216 #define CONFIG_SYS_HUSH_PARSER
 217 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 218
 219 /* I2C */
 220 #define CONFIG_HARD_I2C                 /* I2C with hardware support*/
 221 #define CONFIG_FSL_I2C
 222 #define CONFIG_I2C_MULTI_BUS
 223 #define CONFIG_I2C_CMD_TREE
 224 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 225 #define CONFIG_SYS_I2C_SLAVE            0x7F
 226 #define CONFIG_SYS_I2C_NOPROBES         {{0,0x69}} /* Don't probe these addrs */
 227 #define CONFIG_SYS_I2C_OFFSET           0x3000
 228 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 229
 230 /*
 231  * General PCI
 232  * Addresses are mapped 1-1.
 233  */
 234 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 235 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 236 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 237 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 238 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 239 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 240 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 241 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 242 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 243
 244 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 245 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1057  /* Motorola */
 246
 247 /*
 248  * TSEC
 249  */
 250 #define CONFIG_TSEC_ENET                /* TSEC ethernet support */
 251
 252 #define CONFIG_NET_MULTI
 253 #define CONFIG_GMII                     /* MII PHY management */
 254
 255 #ifdef CONFIG_TSEC1
 256 #define CONFIG_HAS_ETH0
 257 #define CONFIG_TSEC1_NAME               "TSEC0"
 258 #define CONFIG_SYS_TSEC1_OFFSET         0x24000
 259 #define TSEC1_PHY_ADDR                  0x0
 260 #define TSEC1_FLAGS                     TSEC_GIGABIT
 261 #define TSEC1_PHYIDX                    0
 262 #endif
 263
 264 #ifdef CONFIG_TSEC2
 265 #define CONFIG_HAS_ETH1
 266 #define CONFIG_TSEC2_NAME               "TSEC1"
 267 #define CONFIG_SYS_TSEC2_OFFSET         0x25000
 268 #define TSEC2_PHY_ADDR                  4
 269 #define TSEC2_FLAGS                     TSEC_GIGABIT
 270 #define TSEC2_PHYIDX                    0
 271 #endif
 272
 273
 274 /* Options are: TSEC[0-1] */
 275 #define CONFIG_ETHPRIME                 "TSEC1"
 276
 277 /*
 278  * Configure on-board RTC
 279  */
 280 #define CONFIG_RTC_DS1337
 281 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 282
 283 /*
 284  * Environment
 285  */
 286 #if defined(CONFIG_NAND_U_BOOT)
 287         #define CONFIG_ENV_IS_IN_NAND           1
 288         #define CONFIG_ENV_OFFSET               (768 * 1024)
 289         #define CONFIG_ENV_SECT_SIZE            CONFIG_SYS_NAND_BLOCK_SIZE
 290         #define CONFIG_ENV_SIZE                 CONFIG_ENV_SECT_SIZE
 291         #define CONFIG_ENV_SIZE_REDUND          CONFIG_ENV_SIZE
 292         #define CONFIG_ENV_RANGE                (CONFIG_ENV_SECT_SIZE * 4)
 293         #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
 294 #elif !defined(CONFIG_SYS_RAMBOOT)
 295         #define CONFIG_ENV_IS_IN_FLASH          1
 296         #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 297         #define CONFIG_ENV_SECT_SIZE            0x10000 /* 64K(one sector) for env */
 298         #define CONFIG_ENV_SIZE                 0x2000
 299
 300 /* Address and size of Redundant Environment Sector */
 301 #else
 302         #define CONFIG_ENV_IS_NOWHERE           1       /* Store ENV in memory only */
 303         #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE - 0x1000)
 304         #define CONFIG_ENV_SIZE                 0x2000
 305 #endif
 306
 307 #define CONFIG_LOADS_ECHO                       1       /* echo on for serial download */
 308 #define CONFIG_SYS_LOADS_BAUD_CHANGE            1       /* allow baudrate change */
 309
 310 /*
 311  * BOOTP options
 312  */
 313 #define CONFIG_BOOTP_BOOTFILESIZE
 314 #define CONFIG_BOOTP_BOOTPATH
 315 #define CONFIG_BOOTP_GATEWAY
 316 #define CONFIG_BOOTP_HOSTNAME
 317
 318
 319 /*
 320  * Command line configuration.
 321  */
 322 #include <config_cmd_default.h>
 323 #undef CONFIG_CMD_IMLS
 324 #undef CONFIG_CMD_FLASH
 325
 326 #define CONFIG_CMD_PING
 327 #define CONFIG_CMD_DHCP
 328 #define CONFIG_CMD_I2C
 329 #define CONFIG_CMD_MII
 330 #define CONFIG_CMD_DATE
 331 #define CONFIG_CMD_PCI
 332 #define CONFIG_CMD_JFFS2
 333
 334 #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
 335         #undef CONFIG_CMD_ENV
 336         #undef CONFIG_CMD_LOADS
 337 #endif
 338
 339 #define CONFIG_CMDLINE_EDITING          1
 340
 341
 342 /*
 343  * Miscellaneous configurable options
 344  */
 345 #define CONFIG_SYS_LONGHELP                             /* undef to save memory */
 346 #define CONFIG_SYS_LOAD_ADDR            0x2000000       /* default load address */
 347 #define CONFIG_SYS_PROMPT               "=> "           /* Monitor Command Prompt */
 348 #define CONFIG_SYS_CBSIZE               1024            /* Console I/O Buffer Size */
 349
 350 #define CONFIG_SYS_PBSIZE               ( CONFIG_SYS_CBSIZE             \
 351                                         + sizeof(CONFIG_SYS_PROMPT)     \
 352                                         + 16 )  /* Print Buffer Size */
 353 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 354 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 355 #define CONFIG_SYS_HZ                   1000            /* decrementer freq: 1ms ticks */
 356
 357 /*
 358  * For booting Linux, the board info and command line data
 359  * have to be in the first 8 MB of memory, since this is
 360  * the maximum mapped by the Linux kernel during initialization.
 361  */
 362 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux*/
 363
 364 #define CONFIG_SYS_RCWH_PCIHOST         0x80000000      /* PCIHOST */
 365
 366 #define CONFIG_SYS_HRCW_LOW             ( HRCWL_LCL_BUS_TO_SCB_CLK_1X1  \
 367                                         | 0x20000000 /* reserved */     \
 368                                         | HRCWL_DDR_TO_SCB_CLK_2X1      \
 369                                         | HRCWL_CSB_TO_CLKIN_4X1        \
 370                                         | HRCWL_CORE_TO_CSB_2_5X1 )
 371
 372 #define CONFIG_SYS_NS16550_CLK          (CONFIG_83XX_CLKIN * 4)
 373
 374 #define CONFIG_SYS_HRCW_HIGH_BASE       ( HRCWH_PCI_HOST                \
 375                                         | HRCWH_PCI1_ARBITER_ENABLE     \
 376                                         | HRCWH_CORE_ENABLE             \
 377                                         | HRCWH_BOOTSEQ_DISABLE         \
 378                                         | HRCWH_SW_WATCHDOG_DISABLE     \
 379                                         | HRCWH_TSEC1M_IN_RGMII         \
 380                                         | HRCWH_TSEC2M_IN_RGMII         \
 381                                         | HRCWH_BIG_ENDIAN              \
 382                                         | HRCWH_LALE_NORMAL )
 383
 384 #ifdef CONFIG_NAND_LP
 385 #define CONFIG_SYS_HRCW_HIGH    ( CONFIG_SYS_HRCW_HIGH_BASE             \
 386                                 | HRCWH_FROM_0XFFF00100                 \
 387                                 | HRCWH_ROM_LOC_NAND_LP_8BIT            \
 388                                 | HRCWH_RL_EXT_NAND)
 389 #else
 390 #define CONFIG_SYS_HRCW_HIGH    ( CONFIG_SYS_HRCW_HIGH_BASE             \
 391                                 | HRCWH_FROM_0XFFF00100                 \
 392                                 | HRCWH_ROM_LOC_NAND_SP_8BIT            \
 393                                 | HRCWH_RL_EXT_NAND )
 394 #endif
 395
 396 /* System IO Config */
 397 #define CONFIG_SYS_SICRH        ( SICRH_ETSEC2_B        \
 398                                 | SICRH_ETSEC2_C        \
 399                                 | SICRH_ETSEC2_D        \
 400                                 | SICRH_ETSEC2_E        \
 401                                 | SICRH_ETSEC2_F        \
 402                                 | SICRH_ETSEC2_G        \
 403                                 | SICRH_TSOBI1          \
 404                                 | SICRH_TSOBI2 )
 405 #define CONFIG_SYS_SICRL        (SICRL_USBDR            \
 406                                 | SICRL_ETSEC2_A )
 407
 408 #define CONFIG_SYS_HID0_INIT    0x000000000
 409 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK      \
 410                                 | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT )
 411
 412 #define CONFIG_SYS_HID2         HID2_HBE
 413
 414 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 415
 416 /* DDR @ 0x00000000 */
 417 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
 418 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 419 #define CONFIG_SYS_IBAT1L       ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATL_PP_10)
 420 #define CONFIG_SYS_IBAT1U       ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATU_BL_256M | BATU_VS | BATU_VP)
 421
 422 /* PCI @ 0x80000000 */
 423 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
 424 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 425 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 426 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 427
 428 /* PCI2 not supported on 8313 */
 429 #define CONFIG_SYS_IBAT4L       (0)
 430 #define CONFIG_SYS_IBAT4U       (0)
 431
 432 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
 433 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 434 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 435
 436 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 437 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_10)
 438 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 439
 440 #define CONFIG_SYS_IBAT7L       (0)
 441 #define CONFIG_SYS_IBAT7U       (0)
 442
 443 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 444 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 445 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 446 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 447 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 448 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 449 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 450 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 451 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 452 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 453 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 454 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 455 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 456 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 457 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 458 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 459
 460 /*
 461  * Internal Definitions
 462  *
 463  * Boot Flags
 464  */
 465 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH */
 466 #define BOOTFLAG_WARM   0x02    /* Software reboot */
 467
 468 /*
 469  * Environment Configuration
 470  */
 471 #define CONFIG_ENV_OVERWRITE
 472
 473 #define CONFIG_NETDEV           eth1
 474
 475 #define CONFIG_HOSTNAME         simpc8313
 476 #define CONFIG_ROOTPATH         /tftpboot/
 477 #define CONFIG_BOOTFILE         /tftpboot/uImage
 478 #define CONFIG_UBOOTPATH        u-boot-nand.bin /* U-Boot image on TFTP server */
 479 #define CONFIG_FDTFILE          simpc8313.dtb
 480
 481 #define CONFIG_LOADADDR         500000  /* default location for tftp and bootm */
 482 #define CONFIG_BOOTDELAY        5       /* 5 second delay */
 483 #define CONFIG_BAUDRATE         115200
 484
 485 #define CONFIG_BOOTCOMMAND      "nand read $loadaddr kernel 600000;bootm $loadaddr - $fdtaddr"
 486
 487 #define XMK_STR(x)      #x
 488 #define MK_STR(x)       XMK_STR(x)
 489
 490 #define CONFIG_EXTRA_ENV_SETTINGS \
 491         "netdev=" MK_STR(CONFIG_NETDEV) "\0"                            \
 492         "ethprime=TSEC1\0"                                              \
 493         "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                          \
 494         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 495                 "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
 496                 "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
 497                 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
 498                 "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
 499                 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
 500         "fdtaddr=ae0000\0"                                              \
 501         "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"                          \
 502         "console=ttyS0\0"                                               \
 503         "setbootargs=setenv bootargs "                                  \
 504                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 505         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "         \
 506                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 507                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"    \
 508         "load_uboot=tftp 100000 u-boot-nand.bin\0"                      \
 509         "burn_uboot=nand erase u-boot 80000; "                          \
 510                 "nand write 100000 u-boot $filesize\0"                  \
 511         "update_uboot=run load_uboot;run burn_uboot\0"                  \
 512         "mtdids=nand0=nand0\0"                                          \
 513         "mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0"      \
 514         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 515                 "nfsroot=${serverip}:${rootpath}\0"                     \
 516         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 517         "addip=setenv bootargs ${bootargs} "                            \
 518                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 519                 ":${hostname}:${netdev}:off panic=1\0"                  \
 520         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"        \
 521         "bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw "             \
 522                 "console=ttyS0,115200\0"                                \
 523         ""
 524
 525 #define CONFIG_NFSBOOTCOMMAND                                           \
 526         "setenv rootdev /dev/nfs;"                                      \
 527         "run setbootargs;"                                              \
 528         "run setipargs;"                                                \
 529         "tftp $loadaddr $bootfile;"                                     \
 530         "tftp $fdtaddr $fdtfile;"                                       \
 531         "bootm $loadaddr - $fdtaddr"
 532
 533 #define CONFIG_RAMBOOTCOMMAND                                           \
 534         "setenv rootdev /dev/ram;"                                      \
 535         "run setbootargs;"                                              \
 536         "tftp $ramdiskaddr $ramdiskfile;"                               \
 537         "tftp $loadaddr $bootfile;"                                     \
 538         "tftp $fdtaddr $fdtfile;"                                       \
 539         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 540
 541 #undef MK_STR
 542 #undef XMK_STR
 543
 544 #endif  /* __CONFIG_H */