include/configs/SL8245.h

   1 /*
   2  * (C) Copyright 2001 - 2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /* ------------------------------------------------------------------------- */
  25 /*
  26  * Configuration settings for the SL8245 board.
  27  */
  28
  29 /* ------------------------------------------------------------------------- */
  30
  31 /*
  32  * board/config.h - configuration options, board specific
  33  */
  34
  35 #ifndef __CONFIG_H
  36 #define __CONFIG_H
  37
  38 /*
  39  * High Level Configuration Options
  40  * (easy to change)
  41  */
  42
  43 #define CONFIG_MPC824X          1
  44 #define CONFIG_MPC8245          1
  45 #define CONFIG_SL8245           1
  46
  47
  48 #define CONFIG_CONS_INDEX       1
  49 #define CONFIG_BAUDRATE         115200
  50 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
  51
  52 #define CONFIG_BOOTDELAY        5
  53
  54 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  55
  56 #define CONFIG_COMMANDS         (CONFIG_CMD_DFL | CFG_CMD_PCI)
  57
  58 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any)       */
  59
  60 #include <cmd_confdefs.h>
  61
  62
  63 /*
  64  * Miscellaneous configurable options
  65  */
  66 #undef CFG_LONGHELP                     /* undef to save memory         */
  67 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
  68 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
  69
  70 /* Print Buffer Size
  71  */
  72 #define CFG_PBSIZE      (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
  73 #define CFG_MAXARGS     32              /* Max number of command args   */
  74 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
  75 #define CFG_LOAD_ADDR   0x00400000      /* Default load address         */
  76
  77 /*-----------------------------------------------------------------------
  78  * Start addresses for the final memory configuration
  79  * (Set up by the startup code)
  80  * Please note that CFG_SDRAM_BASE _must_ start at 0
  81  */
  82 #define CFG_SDRAM_BASE          0x00000000
  83
  84 #define CFG_FLASH_BASE0_PRELIM  0xFF800000      /* FLASH bank on RCS#0 */
  85 #define CFG_FLASH_BASE          CFG_FLASH_BASE0_PRELIM
  86 #define CFG_FLASH_BANKS         { CFG_FLASH_BASE0_PRELIM }
  87
  88 #define CFG_RESET_ADDRESS   0xFFF00100
  89
  90 #define CFG_EUMB_ADDR       0xFC000000
  91
  92 #define CFG_MONITOR_BASE    TEXT_BASE
  93 #define CFG_MONITOR_LEN     (256 << 10) /* Reserve 256 kB for Monitor   */
  94 #define CFG_MALLOC_LEN      (128 << 10) /* Reserve 128 kB for malloc()  */
  95
  96 #define CFG_MEMTEST_START   0x00004000  /* memtest works on             */
  97 #define CFG_MEMTEST_END     0x02000000  /* 0 ... 32 MB in DRAM          */
  98
  99         /* Maximum amount of RAM.
 100          */
 101 #define CFG_MAX_RAM_SIZE    0x10000000  /* 0 .. 256 MB of (S)DRAM */
 102
 103
 104 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
 105 #undef CFG_RAMBOOT
 106 #else
 107 #define CFG_RAMBOOT
 108 #endif
 109
 110 /*
 111  * NS16550 Configuration
 112  */
 113 #define CFG_NS16550
 114 #define CFG_NS16550_SERIAL
 115
 116 #define CFG_NS16550_REG_SIZE    1
 117
 118 #define CFG_NS16550_CLK         get_bus_freq(0)
 119
 120 #define CFG_NS16550_COM1        (CFG_EUMB_ADDR + 0x4500)
 121
 122 /*-----------------------------------------------------------------------
 123  * Definitions for initial stack pointer and data area
 124  */
 125
 126 #define CFG_GBL_DATA_SIZE      128
 127 #define CFG_INIT_RAM_ADDR     0x40000000
 128 #define CFG_INIT_RAM_END      0x1000
 129 #define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 130
 131 /*
 132  * Low Level Configuration Settings
 133  * (address mappings, register initial values, etc.)
 134  * You should know what you are doing if you make changes here.
 135  * For the detail description refer to the MPC8240 user's manual.
 136  */
 137
 138 #define CONFIG_SYS_CLK_FREQ  66666666   /* external frequency to pll */
 139 #define CFG_HZ               1000
 140
 141         /* Bit-field values for MCCR1.
 142          */
 143 #define CFG_ROMNAL          0
 144 #define CFG_ROMFAL          7
 145 #define CFG_BANK0_ROW       2
 146
 147         /* Bit-field values for MCCR2.
 148          */
 149 #define CFG_REFINT          0x400           /* Refresh interval FIXME: was 0t430                */
 150
 151         /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
 152          */
 153 #define CFG_BSTOPRE         192
 154
 155         /* Bit-field values for MCCR3.
 156          */
 157 #define CFG_REFREC          2       /* Refresh to activate interval */
 158
 159         /* Bit-field values for MCCR4.
 160          */
 161 #define CFG_PRETOACT        2       /* Precharge to activate interval */
 162 #define CFG_ACTTOPRE        5       /* Activate to Precharge interval */
 163 #define CFG_ACTORW          3       /* FIXME was 2 */
 164 #define CFG_SDMODE_CAS_LAT  3       /* SDMODE CAS latancy */
 165 #define CFG_SDMODE_WRAP     0       /* SDMODE wrap type */
 166 #define CFG_REGISTERD_TYPE_BUFFER 1
 167 #define CFG_EXTROM          1
 168 #define CFG_REGDIMM         0
 169
 170 #define CFG_ODCR                0xff    /* configures line driver impedances,   */
 171                                         /* see 8245 book for bit definitions    */
 172 #define CFG_PGMAX               0x32    /* how long the 8245 retains the        */
 173                                         /* currently accessed page in memory    */
 174                                         /* see 8245 book for details            */
 175
 176 /* Memory bank settings.
 177  * Only bits 20-29 are actually used from these vales to set the
 178  * start/end addresses. The upper two bits will always be 0, and the lower
 179  * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 180  * address. Refer to the MPC8240 book.
 181  */
 182
 183 #define CFG_BANK0_START     0x00000000
 184 #define CFG_BANK0_END       (CFG_MAX_RAM_SIZE - 1)
 185 #define CFG_BANK0_ENABLE    1
 186 #define CFG_BANK1_START     0x3ff00000
 187 #define CFG_BANK1_END       0x3fffffff
 188 #define CFG_BANK1_ENABLE    0
 189 #define CFG_BANK2_START     0x3ff00000
 190 #define CFG_BANK2_END       0x3fffffff
 191 #define CFG_BANK2_ENABLE    0
 192 #define CFG_BANK3_START     0x3ff00000
 193 #define CFG_BANK3_END       0x3fffffff
 194 #define CFG_BANK3_ENABLE    0
 195 #define CFG_BANK4_START     0x3ff00000
 196 #define CFG_BANK4_END       0x3fffffff
 197 #define CFG_BANK4_ENABLE    0
 198 #define CFG_BANK5_START     0x3ff00000
 199 #define CFG_BANK5_END       0x3fffffff
 200 #define CFG_BANK5_ENABLE    0
 201 #define CFG_BANK6_START     0x3ff00000
 202 #define CFG_BANK6_END       0x3fffffff
 203 #define CFG_BANK6_ENABLE    0
 204 #define CFG_BANK7_START     0x3ff00000
 205 #define CFG_BANK7_END       0x3fffffff
 206 #define CFG_BANK7_ENABLE    0
 207
 208 #define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 209 #define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 210
 211 #define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
 212 #define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 213
 214 #define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 215 #define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 216
 217 #define CFG_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 218 #define CFG_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 219
 220 #define CFG_DBAT0L  CFG_IBAT0L
 221 #define CFG_DBAT0U  CFG_IBAT0U
 222 #define CFG_DBAT1L  CFG_IBAT1L
 223 #define CFG_DBAT1U  CFG_IBAT1U
 224 #define CFG_DBAT2L  CFG_IBAT2L
 225 #define CFG_DBAT2U  CFG_IBAT2U
 226 #define CFG_DBAT3L  CFG_IBAT3L
 227 #define CFG_DBAT3U  CFG_IBAT3U
 228
 229 /*
 230  * For booting Linux, the board info and command line data
 231  * have to be in the first 8 MB of memory, since this is
 232  * the maximum mapped by the Linux kernel during initialization.
 233  */
 234 #define CFG_BOOTMAPSZ       (8 << 20)   /* Initial Memory map for Linux */
 235
 236 /*-----------------------------------------------------------------------
 237  * FLASH organization
 238  */
 239 #define CFG_MAX_FLASH_BANKS     1       /* Max number of flash banks            */
 240 #define CFG_MAX_FLASH_SECT      35      /* Max number of sectors per flash      */
 241
 242 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms) */
 243 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms) */
 244
 245
 246         /* Warining: environment is not EMBEDDED in the U-Boot code.
 247          * It's stored in flash separately.
 248          */
 249 #define CFG_ENV_IS_IN_FLASH         1
 250 #define CFG_ENV_ADDR            0xFFFF0000
 251 #define CFG_ENV_SIZE            0x00010000 /* Size of the Environment           */
 252 #define CFG_ENV_SECT_SIZE       0x00010000 /* Size of the Environment Sector    */
 253
 254 /*-----------------------------------------------------------------------
 255  * Cache Configuration
 256  */
 257 #define CFG_CACHELINE_SIZE      32
 258 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 259 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value        */
 260 #endif
 261
 262 /*
 263  * Internal Definitions
 264  *
 265  * Boot Flags
 266  */
 267 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH     */
 268 #define BOOTFLAG_WARM           0x02    /* Software reboot                      */
 269
 270 /*-----------------------------------------------------------------------
 271  * PCI stuff
 272  *-----------------------------------------------------------------------
 273  */
 274 #define CONFIG_PCI
 275 #define CONFIG_PCI_PNP
 276 #undef  CONFIG_PCI_SCAN_SHOW
 277
 278
 279 #define CONFIG_SK98
 280 #define CONFIG_NET_MULTI
 281
 282
 283 #endif  /* __CONFIG_H */