include/configs/SXNI855T.h

   1 /*
   2  * U-Boot configuration for SIXNET SXNI855T CPU board.
   3  * This board is based (loosely) on the Motorola FADS board, so this
   4  * file is based (loosely) on config_FADS860T.h, see it for additional
   5  * credits.
   6  *
   7  * Copyright (c) 2000-2002 Dave Ellis, SIXNET, dge@sixnetio.com
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  *
  27  */
  28
  29 /*
  30  * Memory map:
  31  *
  32  *   ff100000 -> ff13ffff : FPGA        CS1
  33  *   ff030000 -> ff03ffff : EXPANSION   CS7
  34  *   ff020000 -> ff02ffff : DATA FLASH  CS4
  35  *   ff018000 -> ff01ffff : UART B      CS6/UPMB
  36  *   ff010000 -> ff017fff : UART A      CS5/UPMB
  37  *   ff000000 -> ff00ffff : IMAP                   internal to the MPC855T
  38  *   f8000000 -> fbffffff : FLASH       CS0        up to 64MB
  39  *   f4000000 -> f7ffffff : NVSRAM      CS2        up to 64MB
  40  *   00000000 -> 0fffffff : SDRAM       CS3/UPMA   up to 256MB
  41  */
  42
  43 /* ------------------------------------------------------------------------- */
  44
  45 /*
  46  * board/config.h - configuration options, board specific
  47  */
  48
  49 #ifndef __CONFIG_H
  50 #define __CONFIG_H
  51
  52 /*
  53  * High Level Configuration Options
  54  * (easy to change)
  55  */
  56 #include <mpc8xx_irq.h>
  57
  58 #define CONFIG_SXNI855T         1       /* SIXNET IPm 855T CPU module */
  59
  60 /* The 855T is just a stripped 860T and needs code for 860, so for now
  61  * at least define 860, 860T and 855T
  62  */
  63 #define CONFIG_MPC860           1
  64 #define CONFIG_MPC860T          1
  65 #define CONFIG_MPC855T          1
  66
  67 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  68 #undef  CONFIG_8xx_CONS_SMC2
  69 #undef  CONFIG_8xx_CONS_SCC1
  70 #undef  CONFIG_8xx_CONS_NONE
  71 #define CONFIG_BAUDRATE         9600
  72 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  73
  74 #define MPC8XX_FACT             10      /* 50 MHz is 5 MHz in times 10  */
  75
  76 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  77
  78 #if 0
  79 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  80 #else
  81 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  82 #endif
  83
  84 #define CONFIG_HAS_ETH1
  85
  86 /*-----------------------------------------------------------------------
  87  * Definitions for status LED
  88  */
  89 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  90
  91 # define STATUS_LED_PAR         im_ioport.iop_papar
  92 # define STATUS_LED_DIR         im_ioport.iop_padir
  93 # define STATUS_LED_ODR         im_ioport.iop_paodr
  94 # define STATUS_LED_DAT         im_ioport.iop_padat
  95
  96 # define STATUS_LED_BIT         0x8000          /* LED 0 is on PA.0 */
  97 # define STATUS_LED_PERIOD      ((CFG_HZ / 2) / 5)      /* blink at 5 Hz */
  98 # define STATUS_LED_STATE       STATUS_LED_BLINKING
  99
 100 # define STATUS_LED_ACTIVE      0               /* LED on for bit == 0  */
 101
 102 # define STATUS_LED_BOOT        0               /* LED 0 used for boot status */
 103
 104 #ifdef DEV      /* development (debug) settings */
 105 #define CONFIG_BOOT_LED_STATE   STATUS_LED_OFF
 106 #else           /* production settings */
 107 #define CONFIG_BOOT_LED_STATE   STATUS_LED_ON
 108 #endif
 109
 110 #define CONFIG_SHOW_BOOT_PROGRESS 1
 111
 112 #define CONFIG_BOOTCOMMAND      "bootm f8040000 f8100000" /* autoboot command */
 113 #define CONFIG_BOOTARGS         "root=/dev/ram ip=off"
 114
 115 #define CONFIG_MISC_INIT_R              /* have misc_init_r() function */
 116 #define CONFIG_BOARD_POSTCLK_INIT       /* have board_postclk_init() function */
 117
 118 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 119
 120 #define CONFIG_RTC_DS1306               /* Dallas 1306 real time clock  */
 121
 122 #define CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 123 /*
 124  * Software (bit-bang) I2C driver configuration
 125  */
 126 #define PB_SCL          0x00000020      /* PB 26 */
 127 #define PB_SDA          0x00000010      /* PB 27 */
 128
 129 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 130 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 131 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 132 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 133 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 134                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 135 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 136                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 137 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 138
 139 # define CFG_I2C_SPEED          50000
 140 # define CFG_I2C_SLAVE          0xFE
 141 # define CFG_I2C_EEPROM_ADDR    0x50    /* Atmel 24C64                  */
 142 # define CFG_I2C_EEPROM_ADDR_LEN 2      /* two byte address             */
 143
 144 #define CONFIG_FEC_ENET         1       /* use FEC ethernet  */
 145
 146 #define CFG_DISCOVER_PHY
 147
 148 #define CONFIG_COMMANDS         (CONFIG_CMD_DFL         | \
 149                                  CFG_CMD_EEPROM         | \
 150                                  CFG_CMD_JFFS2          | \
 151                                  CFG_CMD_NAND           | \
 152                                  CFG_CMD_DATE)
 153
 154 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 155 #include <cmd_confdefs.h>
 156
 157 #define CFG_JFFS_CUSTOM_PART
 158 #define CFG_JFFS2_SORT_FRAGMENTS
 159 /* JFFS2 location when using NOR flash */
 160 #define CFG_JFFS2_BASE  (CFG_FLASH_BASE + 0x80000)
 161 #define CFG_JFFS2_SIZE  (0x780000)
 162 /* JFFS2 location (in RAM) when using NAND flash */
 163 #define CFG_JFFS2_RAMBASE 0x400000
 164 #define CFG_JFFS2_RAMSIZE 0x200000      /* NAND boot partition is 2MiB  */
 165
 166 /* NAND flash support */
 167 #define CONFIG_MTD_NAND_ECC_JFFS2
 168 #define CFG_MAX_NAND_DEVICE     1       /* Max number of NAND devices   */
 169 #define SECTORSIZE 512
 170
 171 #define ADDR_COLUMN 1
 172 #define ADDR_PAGE 2
 173 #define ADDR_COLUMN_PAGE 3
 174
 175 #define NAND_ChipID_UNKNOWN     0x00
 176 #define NAND_MAX_FLOORS 1
 177 #define NAND_MAX_CHIPS 1
 178
 179 /* DFBUSY is available on Port C, bit 12; 0 if busy */
 180 #define NAND_WAIT_READY(nand)   \
 181         while (!(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & 0x0008));
 182 #define WRITE_NAND_COMMAND(d, adr) WRITE_NAND((d), (adr))
 183 #define WRITE_NAND_ADDRESS(d, adr) WRITE_NAND((d), (adr))
 184 #define WRITE_NAND(d, adr)      \
 185          do { (*(volatile uint8_t *)(adr) = (uint8_t)(d)); } while (0)
 186 #define READ_NAND(adr) (*(volatile uint8_t *)(adr))
 187 #define CLE_LO  0x01    /* 0 selects CLE mode (CLE high) */
 188 #define ALE_LO  0x02    /* 0 selects ALE mode (ALE high) */
 189 #define CE_LO   0x04    /* 1 selects chip (CE low) */
 190 #define nand_setcr(cr, val) do {*(volatile uint8_t*)(cr) = (val);} while (0)
 191 #define NAND_DISABLE_CE(nand) \
 192         nand_setcr((nand)->IO_ADDR + 1, ALE_LO | CLE_LO)
 193 #define NAND_ENABLE_CE(nand) \
 194         nand_setcr((nand)->IO_ADDR + 1, CE_LO | ALE_LO | CLE_LO)
 195 #define NAND_CTL_CLRALE(nandptr) \
 196         nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO)
 197 #define NAND_CTL_SETALE(nandptr) \
 198         nand_setcr((nandptr) + 1, CE_LO | CLE_LO)
 199 #define NAND_CTL_CLRCLE(nandptr) \
 200         nand_setcr((nandptr) + 1, CE_LO | ALE_LO | CLE_LO)
 201 #define NAND_CTL_SETCLE(nandptr) \
 202         nand_setcr((nandptr) + 1, CE_LO | ALE_LO)
 203
 204 /*
 205  * Miscellaneous configurable options
 206  */
 207 #define CFG_LONGHELP                    /* undef to save a little memory */
 208 #define CFG_PROMPT              "=>"    /* Monitor Command Prompt       */
 209 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 210 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 211 #else
 212 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 213 #endif
 214 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 215 #define CFG_MAXARGS     16              /* max number of command args   */
 216 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 217
 218 #define CFG_MEMTEST_START       0x0100000       /* memtest works on     */
 219 #define CFG_MEMTEST_END         0x0400000       /* 1 ... 4 MB in DRAM   */
 220
 221 #define CFG_LOAD_ADDR           0x00100000
 222
 223 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 224
 225 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 226
 227 /*
 228  * Low Level Configuration Settings
 229  * (address mappings, register initial values, etc.)
 230  * You should know what you are doing if you make changes here.
 231  */
 232 /*-----------------------------------------------------------------------
 233  * Internal Memory Mapped Register
 234  */
 235 #define CFG_IMMR                0xFF000000
 236 #define CFG_IMMR_SIZE           ((uint)(64 * 1024))
 237
 238 /*-----------------------------------------------------------------------
 239  * Definitions for initial stack pointer and data area (in DPRAM)
 240  */
 241 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 242 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 243 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 244 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 245 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 246
 247 /*-----------------------------------------------------------------------
 248  * Start addresses for the final memory configuration
 249  * (Set up by the startup code)
 250  * Please note that CFG_SDRAM_BASE _must_ start at 0
 251  */
 252 #define CFG_SDRAM_BASE          0x00000000
 253 #define CFG_SRAM_BASE           0xF4000000
 254 #define CFG_SRAM_SIZE           0x04000000      /* autosize up to 64Mbyte */
 255
 256 #define CFG_FLASH_BASE          0xF8000000
 257 #define CFG_FLASH_SIZE          ((uint)(8 * 1024 * 1024))       /* max 8Mbyte */
 258
 259 #define CFG_DFLASH_BASE         0xff020000 /* DiskOnChip or NAND FLASH */
 260 #define CFG_DFLASH_SIZE         0x00010000
 261
 262 #define CFG_FPGA_BASE           0xFF100000      /* Xilinx FPGA */
 263 #define CFG_FPGA_PROG           0xFF130000      /* Programming address */
 264 #define CFG_FPGA_SIZE           0x00040000      /* 256KiB usable */
 265
 266 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 267 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 268 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 269
 270 /*
 271  * For booting Linux, the board info and command line data
 272  * have to be in the first 8 MB of memory, since this is
 273  * the maximum mapped by the Linux kernel during initialization.
 274  */
 275 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 276 /*-----------------------------------------------------------------------
 277  * FLASH organization
 278  */
 279 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 280 /* Intel 28F640 has 135, 127 64K sectors in 8MB, + 8 more for 8K boot blocks.
 281  * AMD 29LV641 has 128 64K sectors in 8MB
 282  */
 283 #define CFG_MAX_FLASH_SECT      135     /* max number of sectors on one chip    */
 284
 285 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 286 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 287
 288 /*-----------------------------------------------------------------------
 289  * Cache Configuration
 290  */
 291 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 292 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 293 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 294 #endif
 295
 296 /*-----------------------------------------------------------------------
 297  * SYPCR - System Protection Control                                    11-9
 298  * SYPCR can only be written once after reset!
 299  *-----------------------------------------------------------------------
 300  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 301  */
 302 #if defined(CONFIG_WATCHDOG)
 303 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 304                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 305 #else
 306 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 307 #endif
 308
 309 /*-----------------------------------------------------------------------
 310  * SIUMCR - SIU Module Configuration                                    11-6
 311  *-----------------------------------------------------------------------
 312  * PCMCIA config., multi-function pin tri-state
 313  */
 314 #define CFG_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 315
 316 /*-----------------------------------------------------------------------
 317  * TBSCR - Time Base Status and Control                                 11-26
 318  *-----------------------------------------------------------------------
 319  * Clear Reference Interrupt Status, Timebase freezing enabled
 320  */
 321 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 322
 323 /*-----------------------------------------------------------------------
 324  * PISCR - Periodic Interrupt Status and Control                11-31
 325  *-----------------------------------------------------------------------
 326  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 327  */
 328 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 329
 330 /*-----------------------------------------------------------------------
 331  * PLPRCR - PLL, Low-Power, and Reset Control Register  15-30
 332  *-----------------------------------------------------------------------
 333  * set the PLL, the low-power modes and the reset control (15-29)
 334  */
 335 #define CFG_PLPRCR      (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
 336                                 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 337
 338 /*-----------------------------------------------------------------------
 339  * SCCR - System Clock and reset Control Register               15-27
 340  *-----------------------------------------------------------------------
 341  * Set clock output, timebase and RTC source and divider,
 342  * power management and some other internal clocks
 343  */
 344 #define SCCR_MASK       SCCR_EBDF11
 345 #define CFG_SCCR        (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
 346
 347  /*-----------------------------------------------------------------------
 348  *
 349  *-----------------------------------------------------------------------
 350  *
 351  */
 352 #define CFG_DER         0
 353
 354 /* Because of the way the 860 starts up and assigns CS0 the
 355  * entire address space, we have to set the memory controller
 356  * differently.  Normally, you write the option register
 357  * first, and then enable the chip select by writing the
 358  * base register.  For CS0, you must write the base register
 359  * first, followed by the option register.
 360  */
 361
 362 /*
 363  * Init Memory Controller:
 364  *
 365  **********************************************************
 366  * BR0 and OR0 (FLASH)
 367  */
 368
 369 #define CFG_PRELIM_OR0_AM       0xFC000000      /* OR addr mask */
 370
 371 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0        */
 372 #define CFG_OR_TIMING_FLASH     (OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
 373
 374 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR0_AM | CFG_OR_TIMING_FLASH)
 375
 376 #define CONFIG_FLASH_16BIT
 377 #define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V )
 378 #define CFG_FLASH_PROTECTION    /* need to lock/unlock sectors in hardware */
 379
 380 /**********************************************************
 381  * BR1 and OR1 (FPGA)
 382  * These preliminary values are also the final values.
 383  */
 384 #define CFG_OR_TIMING_FPGA \
 385         (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_4_CLK | OR_EHTR | OR_TRLX)
 386 #define CFG_BR1_PRELIM  ((CFG_FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 387 #define CFG_OR1_PRELIM  (((-CFG_FPGA_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_FPGA)
 388
 389 /**********************************************************
 390  * BR4 and OR4 (data flash)
 391  * These preliminary values are also the final values.
 392  */
 393 #define CFG_OR_TIMING_DFLASH \
 394         (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK | OR_EHTR | OR_TRLX)
 395 #define CFG_BR4_PRELIM  ((CFG_DFLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 396 #define CFG_OR4_PRELIM  (((-CFG_DFLASH_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_DFLASH)
 397
 398 /**********************************************************
 399  * BR5/6 and OR5/6 (Dual UART)
 400  */
 401 #define CFG_DUART_SIZE  0x8000  /* 32K window, only uses 8 bytes */
 402 #define CFG_DUARTA_BASE 0xff010000
 403 #define CFG_DUARTB_BASE 0xff018000
 404
 405 #define DUART_MBMR      0
 406 #define DUART_OR_VALUE (ORMASK(CFG_DUART_SIZE) | OR_G5LS| OR_BI)
 407 #define DUART_BR_VALUE (BR_MS_UPMB | BR_PS_8 | BR_V)
 408 #define DUART_BR5_VALUE ((CFG_DUARTA_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
 409 #define DUART_BR6_VALUE ((CFG_DUARTB_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
 410
 411 /**********************************************************
 412  *
 413  * Boot Flags
 414  */
 415 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 416 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 417
 418 #define CONFIG_RESET_ON_PANIC           /* reset if system panic() */
 419
 420 #define CFG_ENV_IS_IN_FLASH
 421 #ifdef CFG_ENV_IS_IN_FLASH
 422   /* environment is in FLASH */
 423   #define CFG_ENV_ADDR          0xF8040000      /* AM29LV641 or AM29LV800BT */
 424   #define CFG_ENV_ADDR_REDUND   0xF8050000      /* AM29LV641 or AM29LV800BT */
 425   #define CFG_ENV_SECT_SIZE     0x00010000
 426   #define CFG_ENV_SIZE          0x00002000
 427 #else
 428   /* environment is in EEPROM */
 429   #define CFG_ENV_IS_IN_EEPROM          1
 430   #define CFG_ENV_OFFSET                0       /* at beginning of EEPROM */
 431   #define CFG_ENV_SIZE               1024       /* Use only a part of it*/
 432 #endif
 433
 434 #if 1
 435 #define CONFIG_AUTOBOOT_KEYED           /* use key strings to stop autoboot */
 436 #define CONFIG_AUTOBOOT_PROMPT          "autoboot in %d seconds\n"
 437 #define CONFIG_AUTOBOOT_DELAY_STR       "delayabit"
 438 #define CONFIG_AUTOBOOT_STOP_STR        " " /* easy to stop for now */
 439 #endif
 440
 441 #endif  /* __CONFIG_H */