include/configs/SXNI855T.h

   1 /*
   2  * U-Boot configuration for SIXNET SXNI855T CPU board.
   3  * This board is based (loosely) on the Motorola FADS board, so this
   4  * file is based (loosely) on config_FADS860T.h, see it for additional
   5  * credits.
   6  *
   7  * Copyright (c) 2000-2002 Dave Ellis, SIXNET, dge@sixnetio.com
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  *
  27  */
  28
  29 /*
  30  * Memory map:
  31  *
  32  *   ff100000 -> ff13ffff : FPGA        CS1
  33  *   ff030000 -> ff03ffff : EXPANSION   CS7
  34  *   ff020000 -> ff02ffff : DATA FLASH  CS4
  35  *   ff018000 -> ff01ffff : UART B      CS6/UPMB
  36  *   ff010000 -> ff017fff : UART A      CS5/UPMB
  37  *   ff000000 -> ff00ffff : IMAP                   internal to the MPC855T
  38  *   f8000000 -> fbffffff : FLASH       CS0        up to 64MB
  39  *   f4000000 -> f7ffffff : NVSRAM      CS2        up to 64MB
  40  *   00000000 -> 0fffffff : SDRAM       CS3/UPMA   up to 256MB
  41  */
  42
  43 /* ------------------------------------------------------------------------- */
  44
  45 /*
  46  * board/config.h - configuration options, board specific
  47  */
  48
  49 #ifndef __CONFIG_H
  50 #define __CONFIG_H
  51
  52 /*
  53  * High Level Configuration Options
  54  * (easy to change)
  55  */
  56 #include <mpc8xx_irq.h>
  57
  58 #define CONFIG_SXNI855T         1       /* SIXNET IPm 855T CPU module */
  59
  60 /* The 855T is just a stripped 860T and needs code for 860, so for now
  61  * at least define 860, 860T and 855T
  62  */
  63 #define CONFIG_MPC860           1
  64 #define CONFIG_MPC860T          1
  65 #define CONFIG_MPC855T          1
  66
  67 #define CONFIG_SYS_TEXT_BASE    0xF8000000
  68
  69 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  70 #undef  CONFIG_8xx_CONS_SMC2
  71 #undef  CONFIG_8xx_CONS_SCC1
  72 #undef  CONFIG_8xx_CONS_NONE
  73 #define CONFIG_BAUDRATE         9600
  74 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  75
  76 #define MPC8XX_FACT             10      /* 50 MHz is 5 MHz in times 10  */
  77
  78 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  79
  80 #if 0
  81 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  82 #else
  83 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  84 #endif
  85
  86 #define CONFIG_HAS_ETH1
  87
  88 /*-----------------------------------------------------------------------
  89  * Definitions for status LED
  90  */
  91 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  92
  93 # define STATUS_LED_PAR         im_ioport.iop_papar
  94 # define STATUS_LED_DIR         im_ioport.iop_padir
  95 # define STATUS_LED_ODR         im_ioport.iop_paodr
  96 # define STATUS_LED_DAT         im_ioport.iop_padat
  97
  98 # define STATUS_LED_BIT         0x8000          /* LED 0 is on PA.0 */
  99 # define STATUS_LED_PERIOD      ((CONFIG_SYS_HZ / 2) / 5)       /* blink at 5 Hz */
 100 # define STATUS_LED_STATE       STATUS_LED_BLINKING
 101
 102 # define STATUS_LED_ACTIVE      0               /* LED on for bit == 0  */
 103
 104 # define STATUS_LED_BOOT        0               /* LED 0 used for boot status */
 105
 106 #ifdef DEV      /* development (debug) settings */
 107 #define CONFIG_BOOT_LED_STATE   STATUS_LED_OFF
 108 #else           /* production settings */
 109 #define CONFIG_BOOT_LED_STATE   STATUS_LED_ON
 110 #endif
 111
 112 #define CONFIG_SHOW_BOOT_PROGRESS 1
 113
 114 #define CONFIG_BOOTCOMMAND      "bootm f8040000 f8100000" /* autoboot command */
 115 #define CONFIG_BOOTARGS         "root=/dev/ram ip=off"
 116
 117 #define CONFIG_MISC_INIT_R              /* have misc_init_r() function */
 118 #define CONFIG_BOARD_POSTCLK_INIT       /* have board_postclk_init() function */
 119
 120 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 121
 122 #define CONFIG_RTC_DS1306               /* Dallas 1306 real time clock  */
 123
 124 #define CONFIG_SYS_I2C
 125 #define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
 126 #define CONFIG_SYS_I2C_SOFT_SPEED       50000
 127 #define CONFIG_SYS_I2C_SOFT_SLAVE       0xFE
 128 /*
 129  * Software (bit-bang) I2C driver configuration
 130  */
 131 #define PB_SCL          0x00000020      /* PB 26 */
 132 #define PB_SDA          0x00000010      /* PB 27 */
 133
 134 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 135 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 136 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 137 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 138 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 139                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 140 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 141                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 142 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 143
 144 # define CONFIG_SYS_I2C_EEPROM_ADDR     0x50    /* Atmel 24C64                  */
 145 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2       /* two byte address             */
 146
 147 #define CONFIG_FEC_ENET         1       /* use FEC ethernet  */
 148 #define CONFIG_MII              1
 149
 150 #define CONFIG_SYS_DISCOVER_PHY
 151
 152
 153 /*
 154  * BOOTP options
 155  */
 156 #define CONFIG_BOOTP_BOOTFILESIZE
 157 #define CONFIG_BOOTP_BOOTPATH
 158 #define CONFIG_BOOTP_GATEWAY
 159 #define CONFIG_BOOTP_HOSTNAME
 160
 161
 162 /*
 163  * Command line configuration.
 164  */
 165 #include <config_cmd_default.h>
 166
 167 #define CONFIG_CMD_EEPROM
 168 #define CONFIG_CMD_JFFS2
 169 #define CONFIG_CMD_DATE
 170
 171 /*
 172  * Miscellaneous configurable options
 173  */
 174 #define CONFIG_SYS_LONGHELP                     /* undef to save a little memory */
 175 #define CONFIG_SYS_PROMPT               "=>"    /* Monitor Command Prompt       */
 176 #if defined(CONFIG_CMD_KGDB)
 177 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 178 #else
 179 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 180 #endif
 181 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 182 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 183 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 184
 185 #define CONFIG_SYS_MEMTEST_START        0x0100000       /* memtest works on     */
 186 #define CONFIG_SYS_MEMTEST_END          0x0400000       /* 1 ... 4 MB in DRAM   */
 187
 188 #define CONFIG_SYS_LOAD_ADDR            0x00100000
 189
 190 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 191
 192 /*
 193  * Low Level Configuration Settings
 194  * (address mappings, register initial values, etc.)
 195  * You should know what you are doing if you make changes here.
 196  */
 197 /*-----------------------------------------------------------------------
 198  * Internal Memory Mapped Register
 199  */
 200 #define CONFIG_SYS_IMMR         0xFF000000
 201 #define CONFIG_SYS_IMMR_SIZE            ((uint)(64 * 1024))
 202
 203 /*-----------------------------------------------------------------------
 204  * Definitions for initial stack pointer and data area (in DPRAM)
 205  */
 206 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 207 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 208 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 209 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 210
 211 /*-----------------------------------------------------------------------
 212  * Start addresses for the final memory configuration
 213  * (Set up by the startup code)
 214  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 215  */
 216 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 217 #define CONFIG_SYS_SRAM_BASE            0xF4000000
 218 #define CONFIG_SYS_SRAM_SIZE            0x04000000      /* autosize up to 64Mbyte */
 219
 220 #define CONFIG_SYS_FLASH_BASE           0xF8000000
 221 #define CONFIG_SYS_FLASH_SIZE           ((uint)(8 * 1024 * 1024))       /* max 8Mbyte */
 222
 223 #define CONFIG_SYS_DFLASH_BASE          0xff020000 /* DiskOnChip or NAND FLASH */
 224 #define CONFIG_SYS_DFLASH_SIZE          0x00010000
 225
 226 #define CONFIG_SYS_FPGA_BASE            0xFF100000      /* Xilinx FPGA */
 227 #define CONFIG_SYS_FPGA_PROG            0xFF130000      /* Programming address */
 228 #define CONFIG_SYS_FPGA_SIZE            0x00040000      /* 256KiB usable */
 229
 230 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 231 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 232 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 233
 234 /*
 235  * For booting Linux, the board info and command line data
 236  * have to be in the first 8 MB of memory, since this is
 237  * the maximum mapped by the Linux kernel during initialization.
 238  */
 239 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 240 /*-----------------------------------------------------------------------
 241  * FLASH organization
 242  */
 243 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 244 /* Intel 28F640 has 135, 127 64K sectors in 8MB, + 8 more for 8K boot blocks.
 245  * AMD 29LV641 has 128 64K sectors in 8MB
 246  */
 247 #define CONFIG_SYS_MAX_FLASH_SECT       135     /* max number of sectors on one chip    */
 248
 249 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 250 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 251
 252 /*-----------------------------------------------------------------------
 253  * Cache Configuration
 254  */
 255 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 256 #if defined(CONFIG_CMD_KGDB)
 257 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 258 #endif
 259
 260 /*-----------------------------------------------------------------------
 261  * SYPCR - System Protection Control                                    11-9
 262  * SYPCR can only be written once after reset!
 263  *-----------------------------------------------------------------------
 264  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 265  */
 266 #if defined(CONFIG_WATCHDOG)
 267 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 268                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 269 #else
 270 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 271 #endif
 272
 273 /*-----------------------------------------------------------------------
 274  * SIUMCR - SIU Module Configuration                                    11-6
 275  *-----------------------------------------------------------------------
 276  * PCMCIA config., multi-function pin tri-state
 277  */
 278 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 279
 280 /*-----------------------------------------------------------------------
 281  * TBSCR - Time Base Status and Control                                 11-26
 282  *-----------------------------------------------------------------------
 283  * Clear Reference Interrupt Status, Timebase freezing enabled
 284  */
 285 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 286
 287 /*-----------------------------------------------------------------------
 288  * PISCR - Periodic Interrupt Status and Control                11-31
 289  *-----------------------------------------------------------------------
 290  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 291  */
 292 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 293
 294 /*-----------------------------------------------------------------------
 295  * PLPRCR - PLL, Low-Power, and Reset Control Register  15-30
 296  *-----------------------------------------------------------------------
 297  * set the PLL, the low-power modes and the reset control (15-29)
 298  */
 299 #define CONFIG_SYS_PLPRCR       (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
 300                                 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 301
 302 /*-----------------------------------------------------------------------
 303  * SCCR - System Clock and reset Control Register               15-27
 304  *-----------------------------------------------------------------------
 305  * Set clock output, timebase and RTC source and divider,
 306  * power management and some other internal clocks
 307  */
 308 #define SCCR_MASK       SCCR_EBDF11
 309 #define CONFIG_SYS_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
 310
 311  /*-----------------------------------------------------------------------
 312  *
 313  *-----------------------------------------------------------------------
 314  *
 315  */
 316 #define CONFIG_SYS_DER          0
 317
 318 /* Because of the way the 860 starts up and assigns CS0 the
 319  * entire address space, we have to set the memory controller
 320  * differently.  Normally, you write the option register
 321  * first, and then enable the chip select by writing the
 322  * base register.  For CS0, you must write the base register
 323  * first, followed by the option register.
 324  */
 325
 326 /*
 327  * Init Memory Controller:
 328  *
 329  **********************************************************
 330  * BR0 and OR0 (FLASH)
 331  */
 332
 333 #define CONFIG_SYS_PRELIM_OR0_AM        0xFC000000      /* OR addr mask */
 334
 335 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0        */
 336 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
 337
 338 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR0_AM | CONFIG_SYS_OR_TIMING_FLASH)
 339
 340 #define CONFIG_FLASH_16BIT
 341 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V )
 342 #define CONFIG_SYS_FLASH_PROTECTION     /* need to lock/unlock sectors in hardware */
 343
 344 /**********************************************************
 345  * BR1 and OR1 (FPGA)
 346  * These preliminary values are also the final values.
 347  */
 348 #define CONFIG_SYS_OR_TIMING_FPGA \
 349         (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_4_CLK | OR_EHTR | OR_TRLX)
 350 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 351 #define CONFIG_SYS_OR1_PRELIM   (((-CONFIG_SYS_FPGA_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_FPGA)
 352
 353 /**********************************************************
 354  * BR4 and OR4 (data flash)
 355  * These preliminary values are also the final values.
 356  */
 357 #define CONFIG_SYS_OR_TIMING_DFLASH \
 358         (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK | OR_EHTR | OR_TRLX)
 359 #define CONFIG_SYS_BR4_PRELIM   ((CONFIG_SYS_DFLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
 360 #define CONFIG_SYS_OR4_PRELIM   (((-CONFIG_SYS_DFLASH_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_DFLASH)
 361
 362 /**********************************************************
 363  * BR5/6 and OR5/6 (Dual UART)
 364  */
 365 #define CONFIG_SYS_DUART_SIZE   0x8000  /* 32K window, only uses 8 bytes */
 366 #define CONFIG_SYS_DUARTA_BASE  0xff010000
 367 #define CONFIG_SYS_DUARTB_BASE  0xff018000
 368
 369 #define DUART_MBMR      0
 370 #define DUART_OR_VALUE (ORMASK(CONFIG_SYS_DUART_SIZE) | OR_G5LS| OR_BI)
 371 #define DUART_BR_VALUE (BR_MS_UPMB | BR_PS_8 | BR_V)
 372 #define DUART_BR5_VALUE ((CONFIG_SYS_DUARTA_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
 373 #define DUART_BR6_VALUE ((CONFIG_SYS_DUARTB_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
 374
 375 #define CONFIG_RESET_ON_PANIC           /* reset if system panic() */
 376
 377 #define CONFIG_ENV_IS_IN_FLASH
 378 #ifdef CONFIG_ENV_IS_IN_FLASH
 379   /* environment is in FLASH */
 380   #define CONFIG_ENV_ADDR               0xF8040000      /* AM29LV641 or AM29LV800BT */
 381   #define CONFIG_ENV_ADDR_REDUND        0xF8050000      /* AM29LV641 or AM29LV800BT */
 382   #define CONFIG_ENV_SECT_SIZE  0x00010000
 383   #define CONFIG_ENV_SIZE               0x00002000
 384 #else
 385   /* environment is in EEPROM */
 386   #define CONFIG_ENV_IS_IN_EEPROM               1
 387   #define CONFIG_ENV_OFFSET             0       /* at beginning of EEPROM */
 388   #define CONFIG_ENV_SIZE                    1024       /* Use only a part of it*/
 389 #endif
 390
 391 #if 1
 392 #define CONFIG_AUTOBOOT_KEYED           /* use key strings to stop autoboot */
 393 #define CONFIG_AUTOBOOT_PROMPT          "autoboot in %d seconds\n", bootdelay
 394 #define CONFIG_AUTOBOOT_DELAY_STR       "delayabit"
 395 #define CONFIG_AUTOBOOT_STOP_STR        " " /* easy to stop for now */
 396 #endif
 397
 398 #endif  /* __CONFIG_H */