include/configs/Sandpoint8245.h

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /* ------------------------------------------------------------------------- */
  25
  26 /*
  27  * board/config.h - configuration options, board specific
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37
  38 #define CONFIG_MPC824X          1
  39 #define CONFIG_MPC8245          1
  40 #define CONFIG_SANDPOINT        1
  41
  42 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  43
  44 #if 0
  45 #define USE_DINK32              1
  46 #else
  47 #undef USE_DINK32
  48 #endif
  49
  50 #define CONFIG_CONS_INDEX     3               /* set to '3' for on-chip DUART */
  51 #define CONFIG_BAUDRATE         9600
  52 #define CONFIG_DRAM_SPEED       100             /* MHz                          */
  53
  54 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  55
  56
  57 /*
  58  * BOOTP options
  59  */
  60 #define CONFIG_BOOTP_BOOTFILESIZE
  61 #define CONFIG_BOOTP_BOOTPATH
  62 #define CONFIG_BOOTP_GATEWAY
  63 #define CONFIG_BOOTP_HOSTNAME
  64
  65
  66 /*
  67  * Command line configuration.
  68  */
  69 #include <config_cmd_default.h>
  70
  71 #define CONFIG_CMD_DHCP
  72 #define CONFIG_CMD_ELF
  73 #define CONFIG_CMD_I2C
  74 #define CONFIG_CMD_EEPROM
  75 #define CONFIG_CMD_NFS
  76 #define CONFIG_CMD_PCI
  77 #define CONFIG_CMD_SNTP
  78
  79
  80 /*
  81  * Miscellaneous configurable options
  82  */
  83 #define CONFIG_SYS_LONGHELP             1               /* undef to save memory         */
  84 #define CONFIG_SYS_PROMPT               "=> "           /* Monitor Command Prompt       */
  85 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
  86 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size    */
  87 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
  88 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  89 #define CONFIG_SYS_LOAD_ADDR            0x00100000      /* default load address         */
  90 #define CONFIG_SYS_HZ                   1000            /* decrementer freq: 1 ms ticks */
  91
  92 /*-----------------------------------------------------------------------
  93  * PCI stuff
  94  *-----------------------------------------------------------------------
  95  */
  96 #define CONFIG_PCI                              /* include pci support          */
  97 #undef CONFIG_PCI_PNP
  98
  99 #define CONFIG_NET_MULTI                        /* Multi ethernet cards support */
 100
 101 #define CONFIG_EEPRO100
 102 #define CONFIG_SYS_RX_ETH_BUFFER        8               /* use 8 rx buffer on eepro100  */
 103 #define CONFIG_NATSEMI
 104 #define CONFIG_NS8382X
 105
 106 #define PCI_ENET0_IOADDR        0x80000000
 107 #define PCI_ENET0_MEMADDR       0x80000000
 108 #define PCI_ENET1_IOADDR        0x81000000
 109 #define PCI_ENET1_MEMADDR       0x81000000
 110
 111
 112 /*-----------------------------------------------------------------------
 113  * Start addresses for the final memory configuration
 114  * (Set up by the startup code)
 115  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 116  */
 117 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 118 #define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
 119
 120 #define CONFIG_SYS_RESET_ADDRESS        0xFFF00100
 121
 122 #if defined (USE_DINK32)
 123 #define CONFIG_SYS_MONITOR_LEN          0x00030000
 124 #define CONFIG_SYS_MONITOR_BASE 0x00090000
 125 #define CONFIG_SYS_RAMBOOT              1
 126 #define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 127 #define CONFIG_SYS_INIT_RAM_END 0x10000
 128 #define CONFIG_SYS_GBL_DATA_SIZE        256  /* size in bytes reserved for initial data */
 129 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 130 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 131 #else
 132 #undef  CONFIG_SYS_RAMBOOT
 133 #define CONFIG_SYS_MONITOR_LEN          0x00030000
 134 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 135
 136 /*#define CONFIG_SYS_GBL_DATA_SIZE    256*/
 137 #define CONFIG_SYS_GBL_DATA_SIZE        128
 138
 139 #define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
 140 #define CONFIG_SYS_INIT_RAM_END      0x1000
 141 #define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 142
 143 #endif
 144
 145 #define CONFIG_SYS_FLASH_BASE           0xFFF00000
 146 #if 0
 147 #define CONFIG_SYS_FLASH_SIZE           (512 * 1024)    /* sandpoint has tiny eeprom    */
 148 #else
 149 #define CONFIG_SYS_FLASH_SIZE           (1024 * 1024)   /* Unity has onboard 1MByte flash */
 150 #endif
 151 #define CONFIG_ENV_IS_IN_FLASH  1
 152 #define CONFIG_ENV_OFFSET               0x00004000      /* Offset of Environment Sector */
 153 #define CONFIG_ENV_SIZE         0x00002000      /* Total Size of Environment Sector */
 154
 155 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)     /* Reserve 512 kB for malloc()  */
 156
 157 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest works on             */
 158 #define CONFIG_SYS_MEMTEST_END          0x04000000      /* 0 ... 32 MB in DRAM          */
 159
 160 #define CONFIG_SYS_EUMB_ADDR            0xFC000000
 161
 162 #define CONFIG_SYS_ISA_MEM              0xFD000000
 163 #define CONFIG_SYS_ISA_IO               0xFE000000
 164
 165 #define CONFIG_SYS_FLASH_RANGE_BASE     0xFF000000      /* flash memory address range   */
 166 #define CONFIG_SYS_FLASH_RANGE_SIZE     0x01000000
 167 #define FLASH_BASE0_PRELIM      0xFFF00000      /* sandpoint flash              */
 168 #define FLASH_BASE1_PRELIM      0xFF000000      /* PMC onboard flash            */
 169
 170 /*
 171  * select i2c support configuration
 172  *
 173  * Supported configurations are {none, software, hardware} drivers.
 174  * If the software driver is chosen, there are some additional
 175  * configuration items that the driver uses to drive the port pins.
 176  */
 177 #define CONFIG_HARD_I2C         1               /* To enable I2C support        */
 178 #undef  CONFIG_SOFT_I2C                         /* I2C bit-banged               */
 179 #define CONFIG_SYS_I2C_SPEED            400000          /* I2C speed and slave address  */
 180 #define CONFIG_SYS_I2C_SLAVE            0x7F
 181
 182 #ifdef CONFIG_SOFT_I2C
 183 #error "Soft I2C is not configured properly.  Please review!"
 184 #define I2C_PORT                3               /* Port A=0, B=1, C=2, D=3 */
 185 #define I2C_ACTIVE              (iop->pdir |=  0x00010000)
 186 #define I2C_TRISTATE            (iop->pdir &= ~0x00010000)
 187 #define I2C_READ                ((iop->pdat & 0x00010000) != 0)
 188 #define I2C_SDA(bit)            if(bit) iop->pdat |=  0x00010000; \
 189                                 else    iop->pdat &= ~0x00010000
 190 #define I2C_SCL(bit)            if(bit) iop->pdat |=  0x00020000; \
 191                                 else    iop->pdat &= ~0x00020000
 192 #define I2C_DELAY               udelay(5)       /* 1/4 I2C clock duration */
 193 #endif /* CONFIG_SOFT_I2C */
 194
 195 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57            /* EEPROM IS24C02               */
 196 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1               /* Bytes of address             */
 197 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 198 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 199
 200 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 201 #define CONFIG_SYS_FLASH_BANKS          { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
 202
 203 /*-----------------------------------------------------------------------
 204  * Definitions for initial stack pointer and data area (in DPRAM)
 205  */
 206
 207
 208 #define CONFIG_WINBOND_83C553   1       /*has a winbond bridge                  */
 209 #define CONFIG_SYS_USE_WINBOND_IDE      0       /*use winbond 83c553 internal IDE ctrlr */
 210 #define CONFIG_SYS_WINBOND_ISA_CFG_ADDR    0x80005800   /*pci-isa bridge config addr    */
 211 #define CONFIG_SYS_WINBOND_IDE_CFG_ADDR    0x80005900   /*ide config addr               */
 212
 213 #define CONFIG_SYS_IDE_MAXBUS           2   /* max. 2 IDE busses        */
 214 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 215
 216 /*
 217  * NS87308 Configuration
 218  */
 219 #define CONFIG_NS87308                  /* Nat Semi super-io controller on ISA bus */
 220
 221 #define CONFIG_SYS_NS87308_BADDR_10     1
 222
 223 #define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1   | \
 224                                   CONFIG_SYS_NS87308_UART2   | \
 225                                   CONFIG_SYS_NS87308_POWRMAN | \
 226                                   CONFIG_SYS_NS87308_RTC_APC )
 227
 228 #undef  CONFIG_SYS_NS87308_PS2MOD
 229
 230 #define CONFIG_SYS_NS87308_CS0_BASE     0x0076
 231 #define CONFIG_SYS_NS87308_CS0_CONF     0x30
 232 #define CONFIG_SYS_NS87308_CS1_BASE     0x0075
 233 #define CONFIG_SYS_NS87308_CS1_CONF     0x30
 234 #define CONFIG_SYS_NS87308_CS2_BASE     0x0074
 235 #define CONFIG_SYS_NS87308_CS2_CONF     0x30
 236
 237 /*
 238  * NS16550 Configuration
 239  */
 240 #define CONFIG_SYS_NS16550
 241 #define CONFIG_SYS_NS16550_SERIAL
 242
 243 #define CONFIG_SYS_NS16550_REG_SIZE     1
 244
 245 #if (CONFIG_CONS_INDEX > 2)
 246 #define CONFIG_SYS_NS16550_CLK         CONFIG_DRAM_SPEED*1000000
 247 #else
 248 #define CONFIG_SYS_NS16550_CLK         1843200
 249 #endif
 250
 251 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
 252 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
 253 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4500)
 254 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_EUMB_ADDR + 0x4600)
 255
 256 /*
 257  * Low Level Configuration Settings
 258  * (address mappings, register initial values, etc.)
 259  * You should know what you are doing if you make changes here.
 260  */
 261
 262 #define CONFIG_SYS_CLK_FREQ  33333333   /* external frequency to pll */
 263
 264 #define CONFIG_SYS_ROMNAL               7       /*rom/flash next access time            */
 265 #define CONFIG_SYS_ROMFAL               11      /*rom/flash access time                 */
 266
 267 #define CONFIG_SYS_REFINT       430     /* no of clock cycles between CBR refresh cycles */
 268
 269 /* the following are for SDRAM only*/
 270 #define CONFIG_SYS_BSTOPRE      121     /* Burst To Precharge, sets open page interval */
 271 #define CONFIG_SYS_REFREC               8       /* Refresh to activate interval         */
 272 #define CONFIG_SYS_RDLAT                4       /* data latency from read command       */
 273 #define CONFIG_SYS_PRETOACT             3       /* Precharge to activate interval       */
 274 #define CONFIG_SYS_ACTTOPRE             5       /* Activate to Precharge interval       */
 275 #define CONFIG_SYS_ACTORW               3       /* Activate to R/W                      */
 276 #define CONFIG_SYS_SDMODE_CAS_LAT       3       /* SDMODE CAS latency                   */
 277 #define CONFIG_SYS_SDMODE_WRAP          0       /* SDMODE wrap type                     */
 278 #if 0
 279 #define CONFIG_SYS_SDMODE_BURSTLEN      2       /* OBSOLETE!  SDMODE Burst length 2=4, 3=8              */
 280 #endif
 281
 282 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
 283 #define CONFIG_SYS_EXTROM 1
 284 #define CONFIG_SYS_REGDIMM 0
 285
 286
 287 /* memory bank settings*/
 288 /*
 289  * only bits 20-29 are actually used from these vales to set the
 290  * start/end address the upper two bits will be 0, and the lower 20
 291  * bits will be set to 0x00000 for a start address, or 0xfffff for an
 292  * end address
 293  */
 294 #define CONFIG_SYS_BANK0_START          0x00000000
 295 #define CONFIG_SYS_BANK0_END            (CONFIG_SYS_MAX_RAM_SIZE - 1)
 296 #define CONFIG_SYS_BANK0_ENABLE 1
 297 #define CONFIG_SYS_BANK1_START          0x3ff00000
 298 #define CONFIG_SYS_BANK1_END            0x3fffffff
 299 #define CONFIG_SYS_BANK1_ENABLE 0
 300 #define CONFIG_SYS_BANK2_START          0x3ff00000
 301 #define CONFIG_SYS_BANK2_END            0x3fffffff
 302 #define CONFIG_SYS_BANK2_ENABLE 0
 303 #define CONFIG_SYS_BANK3_START          0x3ff00000
 304 #define CONFIG_SYS_BANK3_END            0x3fffffff
 305 #define CONFIG_SYS_BANK3_ENABLE 0
 306 #define CONFIG_SYS_BANK4_START          0x00000000
 307 #define CONFIG_SYS_BANK4_END            0x00000000
 308 #define CONFIG_SYS_BANK4_ENABLE 0
 309 #define CONFIG_SYS_BANK5_START          0x00000000
 310 #define CONFIG_SYS_BANK5_END            0x00000000
 311 #define CONFIG_SYS_BANK5_ENABLE 0
 312 #define CONFIG_SYS_BANK6_START          0x00000000
 313 #define CONFIG_SYS_BANK6_END            0x00000000
 314 #define CONFIG_SYS_BANK6_ENABLE 0
 315 #define CONFIG_SYS_BANK7_START          0x00000000
 316 #define CONFIG_SYS_BANK7_END            0x00000000
 317 #define CONFIG_SYS_BANK7_ENABLE 0
 318 /*
 319  * Memory bank enable bitmask, specifying which of the banks defined above
 320  are actually present. MSB is for bank #7, LSB is for bank #0.
 321  */
 322 #define CONFIG_SYS_BANK_ENABLE          0x01
 323
 324 #define CONFIG_SYS_ODCR         0xff    /* configures line driver impedances,   */
 325                                         /* see 8240 book for bit definitions    */
 326 #define CONFIG_SYS_PGMAX                0x32    /* how long the 8240 retains the        */
 327                                         /* currently accessed page in memory    */
 328                                         /* see 8240 book for details            */
 329
 330 /* SDRAM 0 - 256MB */
 331 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 332 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 333
 334 /* stack in DCACHE @ 1GB (no backing mem) */
 335 #if defined(USE_DINK32)
 336 #define CONFIG_SYS_IBAT1L       (0x40000000 | BATL_PP_00 )
 337 #define CONFIG_SYS_IBAT1U       (0x40000000 | BATU_BL_128K )
 338 #else
 339 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
 340 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 341 #endif
 342
 343 /* PCI memory */
 344 #define CONFIG_SYS_IBAT2L       (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 345 #define CONFIG_SYS_IBAT2U       (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 346
 347 /* Flash, config addrs, etc */
 348 #define CONFIG_SYS_IBAT3L       (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 349 #define CONFIG_SYS_IBAT3U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 350
 351 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 352 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 353 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 354 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 355 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 356 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 357 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 358 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 359
 360 /*
 361  * For booting Linux, the board info and command line data
 362  * have to be in the first 8 MB of memory, since this is
 363  * the maximum mapped by the Linux kernel during initialization.
 364  */
 365 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 366 /*-----------------------------------------------------------------------
 367  * FLASH organization
 368  */
 369 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks           */
 370 #define CONFIG_SYS_MAX_FLASH_SECT       20      /* max number of sectors on one chip    */
 371
 372 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 373 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 374
 375 /*-----------------------------------------------------------------------
 376  * Cache Configuration
 377  */
 378 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8240 CPU                      */
 379 #if defined(CONFIG_CMD_KGDB)
 380 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 381 #endif
 382
 383 /* values according to the manual */
 384
 385 #define CONFIG_DRAM_50MHZ       1
 386 #define CONFIG_SDRAM_50MHZ
 387
 388 #undef  NR_8259_INTS
 389 #define NR_8259_INTS            1
 390
 391
 392 #define CONFIG_DISK_SPINUP_TIME 1000000
 393
 394
 395 #endif  /* __CONFIG_H */