include/configs/T4240EMU.h

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * T4240 EMU board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #define CONFIG_T4240EMU
  14 #define CONFIG_PHYS_64BIT
  15
  16 #define CONFIG_SYS_NO_FLASH             1
  17 #define CONFIG_SYS_FSL_DDR_EMU          1
  18 #define CONFIG_SYS_FSL_NO_QIXIS         1
  19 #define CONFIG_SYS_FSL_NO_SERDES        1
  20
  21 #include "t4qds.h"
  22
  23 #define CONFIG_CMD_CACHE
  24 #define CONFIG_CMD_CACHE_FLUSH
  25
  26 #define CONFIG_ENV_IS_NOWHERE
  27 #define CONFIG_ENV_SIZE         0x2000
  28
  29 #define CONFIG_SYS_CLK_FREQ     100000000
  30 #define CONFIG_DDR_CLK_FREQ     133333333
  31 #define CONFIG_FSL_TBCLK_EXTRA_DIV 100
  32
  33 /*
  34  * DDR Setup
  35  */
  36 #define CONFIG_SYS_SPD_BUS_NUM  1
  37 #define SPD_EEPROM_ADDRESS1     0x51
  38 #define SPD_EEPROM_ADDRESS2     0x52
  39 #define SPD_EEPROM_ADDRESS3     0x53
  40 #define SPD_EEPROM_ADDRESS4     0x54
  41 #define SPD_EEPROM_ADDRESS5     0x55
  42 #define SPD_EEPROM_ADDRESS6     0x56
  43 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
  44 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
  45
  46 /*
  47  * IFC Definitions
  48  */
  49 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
  50 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
  51 /* NOR Flash Timing Params */
  52 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  53                                 + 0x8000000) | \
  54                                 CSPR_PORT_SIZE_32 | \
  55                                 CSPR_MSEL_NOR | \
  56                                 CSPR_V)
  57 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(0)
  58 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x1) | \
  59                                 FTIM0_NOR_TEADC(0x1) | \
  60                                 FTIM0_NOR_TEAHC(0x1))
  61 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x1) | \
  62                                 FTIM1_NOR_TRAD_NOR(0x1))
  63 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x0) | \
  64                                 FTIM2_NOR_TCH(0x0) | \
  65                                 FTIM2_NOR_TWP(0x1))
  66 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  67 #define CONFIG_SYS_IFC_CCR      0x01000000
  68
  69 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
  70 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
  71 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
  72 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
  73 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
  74 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
  75 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
  76 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
  77
  78 /* I2C */
  79 #define CONFIG_SYS_FSL_I2C_SPEED        4000000 /* faster speed for emulator */
  80 #define CONFIG_SYS_FSL_I2C2_SPEED       4000000
  81
  82 /* Qman/Bman */
  83 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
  84 #define CONFIG_SYS_BMAN_NUM_PORTALS     50
  85 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
  86 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
  87 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
  88 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
  89 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
  90 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
  91 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  92 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
  93                                         CONFIG_SYS_BMAN_CENA_SIZE)
  94 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  95 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
  96 #define CONFIG_SYS_QMAN_NUM_PORTALS     50
  97 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
  98 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
  99 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 100 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 101 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 102 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 103 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 104 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 105                                         CONFIG_SYS_QMAN_CENA_SIZE)
 106 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 107 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 108
 109 #define CONFIG_SYS_DPAA_FMAN
 110 #define CONFIG_SYS_DPAA_PME
 111 #define CONFIG_SYS_PMAN
 112 #define CONFIG_SYS_DPAA_DCE
 113 #define CONFIG_SYS_DPAA_RMAN
 114 #define CONFIG_SYS_INTERLAKEN
 115
 116 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 117 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 118 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 119 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 120
 121 #define CONFIG_BOOTDELAY        0
 122
 123 /*
 124  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 125  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 126  * interleaving. It can be cacheline, page, bank, superbank.
 127  * See doc/README.fsl-ddr for details.
 128  */
 129 #ifdef CONFIG_PPC_T4240
 130 #define CTRL_INTLV_PREFERED 3way_4KB
 131 #else
 132 #define CTRL_INTLV_PREFERED cacheline
 133 #endif
 134
 135 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 136         "hwconfig=fsl_ddr:"                                     \
 137         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 138         "bank_intlv=auto;"                                      \
 139         "netdev=eth0\0"                                         \
 140         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 141 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
 142         "consoledev=ttyS0\0"                                    \
 143         "ramdiskaddr=2000000\0"                                 \
 144         "ramdiskfile=t4240emu/ramdisk.uboot\0"                  \
 145         "fdtaddr=c00000\0"                                      \
 146         "fdtfile=t4240emu/t4240emu.dtb\0"                               \
 147         "bdev=sda3\0"
 148
 149 /*
 150  * For emulation this causes u-boot to jump to the start of the proof point
 151  * app code automatically
 152  */
 153 #define CONFIG_PROOF_POINTS                     \
 154         "setenv bootargs root=/dev/$bdev rw "           \
 155         "console=$consoledev,$baudrate $othbootargs;"   \
 156         "cpu 1 release 0x29000000 - - -;"               \
 157         "cpu 2 release 0x29000000 - - -;"               \
 158         "cpu 3 release 0x29000000 - - -;"               \
 159         "cpu 4 release 0x29000000 - - -;"               \
 160         "cpu 5 release 0x29000000 - - -;"               \
 161         "cpu 6 release 0x29000000 - - -;"               \
 162         "cpu 7 release 0x29000000 - - -;"               \
 163         "go 0x29000000"
 164
 165 #define CONFIG_HVBOOT                           \
 166         "setenv bootargs config-addr=0x60000000; "      \
 167         "bootm 0x01000000 - 0x00f00000"
 168
 169 #define CONFIG_LINUX                                    \
 170         "errata;"                                       \
 171         "setenv othbootargs ignore_loglevel;"           \
 172         "setenv bootargs root=/dev/ram rw "             \
 173         "console=$consoledev,$baudrate $othbootargs;"   \
 174         "setenv ramdiskaddr 0x02000000;"                \
 175         "setenv fdtaddr 0x00c00000;"                    \
 176         "setenv loadaddr 0x1000000;"                    \
 177         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 178
 179 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 180
 181 #endif  /* __CONFIG_H */