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1 /*
2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 /*
8 * T4240 QDS board configuration file
9 */
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12
13 #define CONFIG_T4240QDS
14 #define CONFIG_PHYS_64BIT
15
16 #define CONFIG_FSL_SATA_V2
17 #define CONFIG_PCIE4
18
19 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
20
21 #ifdef CONFIG_RAMBOOT_PBL
22 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
23 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_rcw.cfg
24 #if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD)
25 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
27 #else
28 #define CONFIG_SPL
29 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
30 #define CONFIG_SPL_ENV_SUPPORT
31 #define CONFIG_SPL_SERIAL_SUPPORT
32 #define CONFIG_SPL_FLUSH_IMAGE
33 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
34 #define CONFIG_SPL_LIBGENERIC_SUPPORT
35 #define CONFIG_SPL_LIBCOMMON_SUPPORT
36 #define CONFIG_SPL_I2C_SUPPORT
37 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
38 #define CONFIG_FSL_LAW /* Use common FSL init code */
39 #define CONFIG_SYS_TEXT_BASE 0x00201000
40 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
41 #define CONFIG_SPL_PAD_TO 0x40000
42 #define CONFIG_SPL_MAX_SIZE 0x28000
43 #define RESET_VECTOR_OFFSET 0x27FFC
44 #define BOOT_PAGE_OFFSET 0x27000
45
46 #ifdef CONFIG_NAND
47 #define CONFIG_SPL_NAND_SUPPORT
48 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
49 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
50 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
51 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
52 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
53 #define CONFIG_SPL_NAND_BOOT
54 #endif
55
56 #ifdef CONFIG_SDCARD
57 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
58 #define CONFIG_SPL_MMC_SUPPORT
59 #define CONFIG_SPL_MMC_MINIMAL
60 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
61 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
62 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
63 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
64 #ifndef CONFIG_SPL_BUILD
65 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
66 #endif
67 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
68 #define CONFIG_SPL_MMC_BOOT
69 #endif
70
71 #ifdef CONFIG_SPL_BUILD
72 #define CONFIG_SPL_SKIP_RELOCATE
73 #define CONFIG_SPL_COMMON_INIT_DDR
74 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
75 #define CONFIG_SYS_NO_FLASH
76 #endif
77
78 #endif
79 #endif /* CONFIG_RAMBOOT_PBL */
80
81 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
82 /* Set 1M boot space */
83 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
84 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
85 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
86 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
87 #define CONFIG_SYS_NO_FLASH
88 #endif
89
90 #define CONFIG_SRIO_PCIE_BOOT_MASTER
91 #define CONFIG_DDR_ECC
92
93 #include "t4qds.h"
94
95 #ifdef CONFIG_SYS_NO_FLASH
96 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
97 #define CONFIG_ENV_IS_NOWHERE
98 #endif
99 #else
100 #define CONFIG_FLASH_CFI_DRIVER
101 #define CONFIG_SYS_FLASH_CFI
102 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
103 #endif
104
105 #if defined(CONFIG_SPIFLASH)
106 #define CONFIG_SYS_EXTRA_ENV_RELOC
107 #define CONFIG_ENV_IS_IN_SPI_FLASH
108 #define CONFIG_ENV_SPI_BUS 0
109 #define CONFIG_ENV_SPI_CS 0
110 #define CONFIG_ENV_SPI_MAX_HZ 10000000
111 #define CONFIG_ENV_SPI_MODE 0
112 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
113 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
114 #define CONFIG_ENV_SECT_SIZE 0x10000
115 #elif defined(CONFIG_SDCARD)
116 #define CONFIG_SYS_EXTRA_ENV_RELOC
117 #define CONFIG_ENV_IS_IN_MMC
118 #define CONFIG_SYS_MMC_ENV_DEV 0
119 #define CONFIG_ENV_SIZE 0x2000
120 #define CONFIG_ENV_OFFSET (512 * 0x800)
121 #elif defined(CONFIG_NAND)
122 #define CONFIG_SYS_EXTRA_ENV_RELOC
123 #define CONFIG_ENV_IS_IN_NAND
124 #define CONFIG_ENV_SIZE 0x2000
125 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
126 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
127 #define CONFIG_ENV_IS_IN_REMOTE
128 #define CONFIG_ENV_ADDR 0xffe20000
129 #define CONFIG_ENV_SIZE 0x2000
130 #elif defined(CONFIG_ENV_IS_NOWHERE)
131 #define CONFIG_ENV_SIZE 0x2000
132 #else
133 #define CONFIG_ENV_IS_IN_FLASH
134 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
135 #define CONFIG_ENV_SIZE 0x2000
136 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
137 #endif
138
139 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
140 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
141
142 #ifndef __ASSEMBLY__
143 unsigned long get_board_sys_clk(void);
144 unsigned long get_board_ddr_clk(void);
145 #endif
146
147 /* EEPROM */
148 #define CONFIG_ID_EEPROM
149 #define CONFIG_SYS_I2C_EEPROM_NXID
150 #define CONFIG_SYS_EEPROM_BUS_NUM 0
151 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
152 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
153
154 /*
155 * DDR Setup
156 */
157 #define CONFIG_SYS_SPD_BUS_NUM 0
158 #define SPD_EEPROM_ADDRESS1 0x51
159 #define SPD_EEPROM_ADDRESS2 0x52
160 #define SPD_EEPROM_ADDRESS3 0x53
161 #define SPD_EEPROM_ADDRESS4 0x54
162 #define SPD_EEPROM_ADDRESS5 0x55
163 #define SPD_EEPROM_ADDRESS6 0x56
164 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
165 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
166
167 /*
168 * IFC Definitions
169 */
170 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
171 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
172 + 0x8000000) | \
173 CSPR_PORT_SIZE_16 | \
174 CSPR_MSEL_NOR | \
175 CSPR_V)
176 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
177 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
178 CSPR_PORT_SIZE_16 | \
179 CSPR_MSEL_NOR | \
180 CSPR_V)
181 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
182 /* NOR Flash Timing Params */
183 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
184
185 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
186 FTIM0_NOR_TEADC(0x5) | \
187 FTIM0_NOR_TEAHC(0x5))
188 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
189 FTIM1_NOR_TRAD_NOR(0x1A) |\
190 FTIM1_NOR_TSEQRAD_NOR(0x13))
191 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
192 FTIM2_NOR_TCH(0x4) | \
193 FTIM2_NOR_TWPH(0x0E) | \
194 FTIM2_NOR_TWP(0x1c))
195 #define CONFIG_SYS_NOR_FTIM3 0x0
196
197 #define CONFIG_SYS_FLASH_QUIET_TEST
198 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
199
200 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
201 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
202 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
203 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
204
205 #define CONFIG_SYS_FLASH_EMPTY_INFO
206 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
207 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
208
209 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
210 #define QIXIS_BASE 0xffdf0000
211 #define QIXIS_LBMAP_SWITCH 6
212 #define QIXIS_LBMAP_MASK 0x0f
213 #define QIXIS_LBMAP_SHIFT 0
214 #define QIXIS_LBMAP_DFLTBANK 0x00
215 #define QIXIS_LBMAP_ALTBANK 0x04
216 #define QIXIS_RST_CTL_RESET 0x83
217 #define QIXIS_RST_FORCE_MEM 0x1
218 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
219 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
220 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
221 #define QIXIS_BRDCFG5 0x55
222 #define QIXIS_MUX_SDHC 2
223 #define QIXIS_MUX_SDHC_WIDTH8 1
224 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
225
226 #define CONFIG_SYS_CSPR3_EXT (0xf)
227 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
228 | CSPR_PORT_SIZE_8 \
229 | CSPR_MSEL_GPCM \
230 | CSPR_V)
231 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
232 #define CONFIG_SYS_CSOR3 0x0
233 /* QIXIS Timing parameters for IFC CS3 */
234 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
235 FTIM0_GPCM_TEADC(0x0e) | \
236 FTIM0_GPCM_TEAHC(0x0e))
237 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
238 FTIM1_GPCM_TRAD(0x3f))
239 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
240 FTIM2_GPCM_TCH(0x0) | \
241 FTIM2_GPCM_TWP(0x1f))
242 #define CONFIG_SYS_CS3_FTIM3 0x0
243
244 /* NAND Flash on IFC */
245 #define CONFIG_NAND_FSL_IFC
246 #define CONFIG_SYS_NAND_BASE 0xff800000
247 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
248
249 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
250 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
251 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
252 | CSPR_MSEL_NAND /* MSEL = NAND */ \
253 | CSPR_V)
254 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
255
256 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
257 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
258 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
259 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
260 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
261 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
262 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
263
264 #define CONFIG_SYS_NAND_ONFI_DETECTION
265
266 /* ONFI NAND Flash mode0 Timing Params */
267 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
268 FTIM0_NAND_TWP(0x18) | \
269 FTIM0_NAND_TWCHT(0x07) | \
270 FTIM0_NAND_TWH(0x0a))
271 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
272 FTIM1_NAND_TWBE(0x39) | \
273 FTIM1_NAND_TRR(0x0e) | \
274 FTIM1_NAND_TRP(0x18))
275 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
276 FTIM2_NAND_TREH(0x0a) | \
277 FTIM2_NAND_TWHRE(0x1e))
278 #define CONFIG_SYS_NAND_FTIM3 0x0
279
280 #define CONFIG_SYS_NAND_DDR_LAW 11
281
282 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
283 #define CONFIG_SYS_MAX_NAND_DEVICE 1
284 #define CONFIG_MTD_NAND_VERIFY_WRITE
285 #define CONFIG_CMD_NAND
286
287 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
288 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
289 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
290
291 #if defined(CONFIG_NAND)
292 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
293 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
294 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
295 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
296 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
297 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
298 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
299 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
300 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
301 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
302 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
303 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
304 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
305 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
306 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
307 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
308 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
309 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
310 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
311 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
312 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
313 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
314 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
315 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
316 #else
317 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
318 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
319 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
320 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
321 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
322 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
323 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
324 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
325 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
326 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
327 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
328 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
329 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
330 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
331 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
332 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
333 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
334 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
335 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
336 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
337 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
338 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
339 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
340 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
341 #endif
342
343 #if defined(CONFIG_RAMBOOT_PBL)
344 #define CONFIG_SYS_RAMBOOT
345 #endif
346
347
348 /* I2C */
349 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
350 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
351 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
352 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
353
354 #define I2C_MUX_CH_DEFAULT 0x8
355 #define I2C_MUX_CH_VOL_MONITOR 0xa
356 #define I2C_MUX_CH_VSC3316_FS 0xc
357 #define I2C_MUX_CH_VSC3316_BS 0xd
358
359 /* Voltage monitor on channel 2*/
360 #define I2C_VOL_MONITOR_ADDR 0x40
361 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
362 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
363 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
364
365 /* VSC Crossbar switches */
366 #define CONFIG_VSC_CROSSBAR
367 #define VSC3316_FSM_TX_ADDR 0x70
368 #define VSC3316_FSM_RX_ADDR 0x71
369
370 /*
371 * RapidIO
372 */
373
374 /*
375 * for slave u-boot IMAGE instored in master memory space,
376 * PHYS must be aligned based on the SIZE
377 */
378 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
379 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
380 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
381 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
382 /*
383 * for slave UCODE and ENV instored in master memory space,
384 * PHYS must be aligned based on the SIZE
385 */
386 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
387 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
388 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
389
390 /* slave core release by master*/
391 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
392 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
393
394 /*
395 * SRIO_PCIE_BOOT - SLAVE
396 */
397 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
398 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
399 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
400 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
401 #endif
402 /*
403 * eSPI - Enhanced SPI
404 */
405 #define CONFIG_FSL_ESPI
406 #define CONFIG_SPI_FLASH
407 #define CONFIG_SPI_FLASH_SST
408 #define CONFIG_CMD_SF
409 #define CONFIG_SF_DEFAULT_SPEED 10000000
410 #define CONFIG_SF_DEFAULT_MODE 0
411
412
413 /* Qman/Bman */
414 #ifndef CONFIG_NOBQFMAN
415 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
416 #define CONFIG_SYS_BMAN_NUM_PORTALS 50
417 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
418 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
419 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
420 #define CONFIG_SYS_QMAN_NUM_PORTALS 50
421 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
422 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
423 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
424
425 #define CONFIG_SYS_DPAA_FMAN
426 #define CONFIG_SYS_DPAA_PME
427 #define CONFIG_SYS_PMAN
428 #define CONFIG_SYS_DPAA_DCE
429 #define CONFIG_SYS_DPAA_RMAN
430 #define CONFIG_SYS_INTERLAKEN
431
432 /* Default address of microcode for the Linux Fman driver */
433 #if defined(CONFIG_SPIFLASH)
434 /*
435 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
436 * env, so we got 0x110000.
437 */
438 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
439 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
440 #elif defined(CONFIG_SDCARD)
441 /*
442 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
443 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
444 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
445 */
446 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
447 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
448 #elif defined(CONFIG_NAND)
449 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
450 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
451 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
452 /*
453 * Slave has no ucode locally, it can fetch this from remote. When implementing
454 * in two corenet boards, slave's ucode could be stored in master's memory
455 * space, the address can be mapped from slave TLB->slave LAW->
456 * slave SRIO or PCIE outbound window->master inbound window->
457 * master LAW->the ucode address in master's memory space.
458 */
459 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
460 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
461 #else
462 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
463 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
464 #endif
465 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
466 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
467 #endif /* CONFIG_NOBQFMAN */
468
469 #ifdef CONFIG_SYS_DPAA_FMAN
470 #define CONFIG_FMAN_ENET
471 #define CONFIG_PHYLIB_10G
472 #define CONFIG_PHY_VITESSE
473 #define CONFIG_PHY_TERANETICS
474 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
475 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
476 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
477 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
478 #define FM1_10GEC1_PHY_ADDR 0x0
479 #define FM1_10GEC2_PHY_ADDR 0x1
480 #define FM2_10GEC1_PHY_ADDR 0x2
481 #define FM2_10GEC2_PHY_ADDR 0x3
482 #endif
483
484
485 /* SATA */
486 #ifdef CONFIG_FSL_SATA_V2
487 #define CONFIG_LIBATA
488 #define CONFIG_FSL_SATA
489
490 #define CONFIG_SYS_SATA_MAX_DEVICE 2
491 #define CONFIG_SATA1
492 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
493 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
494 #define CONFIG_SATA2
495 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
496 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
497
498 #define CONFIG_LBA48
499 #define CONFIG_CMD_SATA
500 #define CONFIG_DOS_PARTITION
501 #define CONFIG_CMD_EXT2
502 #endif
503
504 #ifdef CONFIG_FMAN_ENET
505 #define CONFIG_MII /* MII PHY management */
506 #define CONFIG_ETHPRIME "FM1@DTSEC1"
507 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
508 #endif
509
510 /*
511 * USB
512 */
513 #define CONFIG_CMD_USB
514 #define CONFIG_USB_STORAGE
515 #define CONFIG_USB_EHCI
516 #define CONFIG_USB_EHCI_FSL
517 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
518 #define CONFIG_CMD_EXT2
519 #define CONFIG_HAS_FSL_DR_USB
520
521 #define CONFIG_MMC
522
523 #ifdef CONFIG_MMC
524 #define CONFIG_FSL_ESDHC
525 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
526 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
527 #define CONFIG_CMD_MMC
528 #define CONFIG_GENERIC_MMC
529 #define CONFIG_CMD_EXT2
530 #define CONFIG_CMD_FAT
531 #define CONFIG_DOS_PARTITION
532 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
533 #define CONFIG_ESDHC_DETECT_QUIRK \
534 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
535 IS_SVR_REV(get_svr(), 1, 0))
536 #define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
537 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
538 #endif
539
540 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
541
542 #define __USB_PHY_TYPE utmi
543
544 /*
545 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
546 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
547 * interleaving. It can be cacheline, page, bank, superbank.
548 * See doc/README.fsl-ddr for details.
549 */
550 #ifdef CONFIG_PPC_T4240
551 #define CTRL_INTLV_PREFERED 3way_4KB
552 #else
553 #define CTRL_INTLV_PREFERED cacheline
554 #endif
555
556 #define CONFIG_EXTRA_ENV_SETTINGS \
557 "hwconfig=fsl_ddr:" \
558 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
559 "bank_intlv=auto;" \
560 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
561 "netdev=eth0\0" \
562 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
563 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
564 "tftpflash=tftpboot $loadaddr $uboot && " \
565 "protect off $ubootaddr +$filesize && " \
566 "erase $ubootaddr +$filesize && " \
567 "cp.b $loadaddr $ubootaddr $filesize && " \
568 "protect on $ubootaddr +$filesize && " \
569 "cmp.b $loadaddr $ubootaddr $filesize\0" \
570 "consoledev=ttyS0\0" \
571 "ramdiskaddr=2000000\0" \
572 "ramdiskfile=t4240qds/ramdisk.uboot\0" \
573 "fdtaddr=c00000\0" \
574 "fdtfile=t4240qds/t4240qds.dtb\0" \
575 "bdev=sda3\0"
576
577 #define CONFIG_HVBOOT \
578 "setenv bootargs config-addr=0x60000000; " \
579 "bootm 0x01000000 - 0x00f00000"
580
581 #define CONFIG_ALU \
582 "setenv bootargs root=/dev/$bdev rw " \
583 "console=$consoledev,$baudrate $othbootargs;" \
584 "cpu 1 release 0x01000000 - - -;" \
585 "cpu 2 release 0x01000000 - - -;" \
586 "cpu 3 release 0x01000000 - - -;" \
587 "cpu 4 release 0x01000000 - - -;" \
588 "cpu 5 release 0x01000000 - - -;" \
589 "cpu 6 release 0x01000000 - - -;" \
590 "cpu 7 release 0x01000000 - - -;" \
591 "go 0x01000000"
592
593 #define CONFIG_LINUX \
594 "setenv bootargs root=/dev/ram rw " \
595 "console=$consoledev,$baudrate $othbootargs;" \
596 "setenv ramdiskaddr 0x02000000;" \
597 "setenv fdtaddr 0x00c00000;" \
598 "setenv loadaddr 0x1000000;" \
599 "bootm $loadaddr $ramdiskaddr $fdtaddr"
600
601 #define CONFIG_HDBOOT \
602 "setenv bootargs root=/dev/$bdev rw " \
603 "console=$consoledev,$baudrate $othbootargs;" \
604 "tftp $loadaddr $bootfile;" \
605 "tftp $fdtaddr $fdtfile;" \
606 "bootm $loadaddr - $fdtaddr"
607
608 #define CONFIG_NFSBOOTCOMMAND \
609 "setenv bootargs root=/dev/nfs rw " \
610 "nfsroot=$serverip:$rootpath " \
611 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
612 "console=$consoledev,$baudrate $othbootargs;" \
613 "tftp $loadaddr $bootfile;" \
614 "tftp $fdtaddr $fdtfile;" \
615 "bootm $loadaddr - $fdtaddr"
616
617 #define CONFIG_RAMBOOTCOMMAND \
618 "setenv bootargs root=/dev/ram rw " \
619 "console=$consoledev,$baudrate $othbootargs;" \
620 "tftp $ramdiskaddr $ramdiskfile;" \
621 "tftp $loadaddr $bootfile;" \
622 "tftp $fdtaddr $fdtfile;" \
623 "bootm $loadaddr $ramdiskaddr $fdtaddr"
624
625 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
626
627 #include <asm/fsl_secure_boot.h>
628
629 #endif /* __CONFIG_H */