include/configs/T4240QDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * T4240 QDS board configuration file
   8  */
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #define CONFIG_FSL_SATA_V2
  13 #define CONFIG_PCIE4
  14
  15 #define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
  16
  17 #ifdef CONFIG_RAMBOOT_PBL
  18 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
  19 #if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD)
  20 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  21 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  22 #else
  23 #define CONFIG_SPL_FLUSH_IMAGE
  24 #define CONFIG_SPL_PAD_TO               0x40000
  25 #define CONFIG_SPL_MAX_SIZE             0x28000
  26 #define RESET_VECTOR_OFFSET             0x27FFC
  27 #define BOOT_PAGE_OFFSET                0x27000
  28
  29 #ifdef  CONFIG_NAND
  30 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  31 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  32 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  33 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  34 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  35 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg
  36 #define CONFIG_SPL_NAND_BOOT
  37 #endif
  38
  39 #ifdef  CONFIG_SDCARD
  40 #define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
  41 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  42 #define CONFIG_SYS_MMC_U_BOOT_DST       0x00200000
  43 #define CONFIG_SYS_MMC_U_BOOT_START     0x00200000
  44 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  45 #ifndef CONFIG_SPL_BUILD
  46 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  47 #endif
  48 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  49 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg
  50 #define CONFIG_SPL_MMC_BOOT
  51 #endif
  52
  53 #ifdef CONFIG_SPL_BUILD
  54 #define CONFIG_SPL_SKIP_RELOCATE
  55 #define CONFIG_SPL_COMMON_INIT_DDR
  56 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  57 #endif
  58
  59 #endif
  60 #endif /* CONFIG_RAMBOOT_PBL */
  61
  62 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  63 /* Set 1M boot space */
  64 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  65 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  66                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  67 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  68 #endif
  69
  70 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  71 #define CONFIG_DDR_ECC
  72
  73 #include "t4qds.h"
  74
  75 #if defined(CONFIG_SPIFLASH)
  76 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  77 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
  78 #define CONFIG_ENV_SECT_SIZE            0x10000
  79 #elif defined(CONFIG_SDCARD)
  80 #define CONFIG_SYS_MMC_ENV_DEV          0
  81 #define CONFIG_ENV_SIZE                 0x2000
  82 #define CONFIG_ENV_OFFSET               (512 * 0x800)
  83 #elif defined(CONFIG_NAND)
  84 #define CONFIG_ENV_SIZE                 0x2000
  85 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
  86 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  87 #define CONFIG_ENV_ADDR         0xffe20000
  88 #define CONFIG_ENV_SIZE         0x2000
  89 #elif defined(CONFIG_ENV_IS_NOWHERE)
  90 #define CONFIG_ENV_SIZE         0x2000
  91 #else
  92 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  93 #define CONFIG_ENV_SIZE         0x2000
  94 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
  95 #endif
  96
  97 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
  98 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
  99
 100 #ifndef __ASSEMBLY__
 101 unsigned long get_board_sys_clk(void);
 102 unsigned long get_board_ddr_clk(void);
 103 #endif
 104
 105 /* EEPROM */
 106 #define CONFIG_ID_EEPROM
 107 #define CONFIG_SYS_I2C_EEPROM_NXID
 108 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 109 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 110 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 111
 112 /*
 113  * DDR Setup
 114  */
 115 #define CONFIG_SYS_SPD_BUS_NUM  0
 116 #define SPD_EEPROM_ADDRESS1     0x51
 117 #define SPD_EEPROM_ADDRESS2     0x52
 118 #define SPD_EEPROM_ADDRESS3     0x53
 119 #define SPD_EEPROM_ADDRESS4     0x54
 120 #define SPD_EEPROM_ADDRESS5     0x55
 121 #define SPD_EEPROM_ADDRESS6     0x56
 122 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 123 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 124
 125 /*
 126  * IFC Definitions
 127  */
 128 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 129 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 130                                 + 0x8000000) | \
 131                                 CSPR_PORT_SIZE_16 | \
 132                                 CSPR_MSEL_NOR | \
 133                                 CSPR_V)
 134 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 135 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 136                                 CSPR_PORT_SIZE_16 | \
 137                                 CSPR_MSEL_NOR | \
 138                                 CSPR_V)
 139 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 140 /* NOR Flash Timing Params */
 141 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 142
 143 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 144                                 FTIM0_NOR_TEADC(0x5) | \
 145                                 FTIM0_NOR_TEAHC(0x5))
 146 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 147                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 148                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 149 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 150                                 FTIM2_NOR_TCH(0x4) | \
 151                                 FTIM2_NOR_TWPH(0x0E) | \
 152                                 FTIM2_NOR_TWP(0x1c))
 153 #define CONFIG_SYS_NOR_FTIM3    0x0
 154
 155 #define CONFIG_SYS_FLASH_QUIET_TEST
 156 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 157
 158 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 159 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 160 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 161 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 162
 163 #define CONFIG_SYS_FLASH_EMPTY_INFO
 164 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 165                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 166
 167 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 168 #define QIXIS_BASE                      0xffdf0000
 169 #define QIXIS_LBMAP_SWITCH              6
 170 #define QIXIS_LBMAP_MASK                0x0f
 171 #define QIXIS_LBMAP_SHIFT               0
 172 #define QIXIS_LBMAP_DFLTBANK            0x00
 173 #define QIXIS_LBMAP_ALTBANK             0x04
 174 #define QIXIS_RST_CTL_RESET             0x83
 175 #define QIXIS_RST_FORCE_MEM             0x1
 176 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 177 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 178 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 179 #define QIXIS_BRDCFG5                   0x55
 180 #define QIXIS_MUX_SDHC                  2
 181 #define QIXIS_MUX_SDHC_WIDTH8           1
 182 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 183
 184 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 185 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 186                                 | CSPR_PORT_SIZE_8 \
 187                                 | CSPR_MSEL_GPCM \
 188                                 | CSPR_V)
 189 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 190 #define CONFIG_SYS_CSOR3        0x0
 191 /* QIXIS Timing parameters for IFC CS3 */
 192 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 193                                         FTIM0_GPCM_TEADC(0x0e) | \
 194                                         FTIM0_GPCM_TEAHC(0x0e))
 195 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 196                                         FTIM1_GPCM_TRAD(0x3f))
 197 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 198                                         FTIM2_GPCM_TCH(0x8) | \
 199                                         FTIM2_GPCM_TWP(0x1f))
 200 #define CONFIG_SYS_CS3_FTIM3            0x0
 201
 202 /* NAND Flash on IFC */
 203 #define CONFIG_NAND_FSL_IFC
 204 #define CONFIG_SYS_NAND_BASE            0xff800000
 205 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 206
 207 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 208 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 209                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 210                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 211                                 | CSPR_V)
 212 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 213
 214 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 215                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 216                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 217                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 218                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 219                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 220                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 221
 222 #define CONFIG_SYS_NAND_ONFI_DETECTION
 223
 224 /* ONFI NAND Flash mode0 Timing Params */
 225 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 226                                         FTIM0_NAND_TWP(0x18)   | \
 227                                         FTIM0_NAND_TWCHT(0x07) | \
 228                                         FTIM0_NAND_TWH(0x0a))
 229 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 230                                         FTIM1_NAND_TWBE(0x39)  | \
 231                                         FTIM1_NAND_TRR(0x0e)   | \
 232                                         FTIM1_NAND_TRP(0x18))
 233 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 234                                         FTIM2_NAND_TREH(0x0a) | \
 235                                         FTIM2_NAND_TWHRE(0x1e))
 236 #define CONFIG_SYS_NAND_FTIM3           0x0
 237
 238 #define CONFIG_SYS_NAND_DDR_LAW         11
 239
 240 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 241 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 242
 243 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 244 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 245 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 246
 247 #if defined(CONFIG_NAND)
 248 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 249 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 250 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 251 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 252 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 253 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 254 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 255 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 256 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 257 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 258 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 259 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 260 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 261 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 262 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 263 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 264 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 265 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 266 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 267 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 268 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 269 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 270 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 271 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 272 #else
 273 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 274 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 275 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 276 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 277 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 278 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 279 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 280 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 281 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 282 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 283 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 284 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 285 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 286 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 287 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 288 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 289 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 290 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 291 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 292 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 293 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 294 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 295 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 296 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 297 #endif
 298
 299 #if defined(CONFIG_RAMBOOT_PBL)
 300 #define CONFIG_SYS_RAMBOOT
 301 #endif
 302
 303 /* I2C */
 304 #define CONFIG_SYS_FSL_I2C_SPEED        100000  /* I2C speed */
 305 #define CONFIG_SYS_FSL_I2C2_SPEED       100000  /* I2C2 speed */
 306 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
 307 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
 308
 309 #define I2C_MUX_CH_DEFAULT      0x8
 310 #define I2C_MUX_CH_VOL_MONITOR  0xa
 311 #define I2C_MUX_CH_VSC3316_FS   0xc
 312 #define I2C_MUX_CH_VSC3316_BS   0xd
 313
 314 /* Voltage monitor on channel 2*/
 315 #define I2C_VOL_MONITOR_ADDR            0x40
 316 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 317 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 318 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 319
 320 /* VSC Crossbar switches */
 321 #define CONFIG_VSC_CROSSBAR
 322 #define VSC3316_FSM_TX_ADDR     0x70
 323 #define VSC3316_FSM_RX_ADDR     0x71
 324
 325 /*
 326  * RapidIO
 327  */
 328
 329 /*
 330  * for slave u-boot IMAGE instored in master memory space,
 331  * PHYS must be aligned based on the SIZE
 332  */
 333 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 334 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 335 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 336 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 337 /*
 338  * for slave UCODE and ENV instored in master memory space,
 339  * PHYS must be aligned based on the SIZE
 340  */
 341 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 342 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 343 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 344
 345 /* slave core release by master*/
 346 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 347 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 348
 349 /*
 350  * SRIO_PCIE_BOOT - SLAVE
 351  */
 352 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 353 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 354 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 355                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 356 #endif
 357 /*
 358  * eSPI - Enhanced SPI
 359  */
 360
 361 /* Qman/Bman */
 362 #ifndef CONFIG_NOBQFMAN
 363 #define CONFIG_SYS_BMAN_NUM_PORTALS     50
 364 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 365 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 366 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 367 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 368 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 369 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 370 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 371 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 372                                         CONFIG_SYS_BMAN_CENA_SIZE)
 373 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 374 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 375 #define CONFIG_SYS_QMAN_NUM_PORTALS     50
 376 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 377 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 378 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 379 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 380 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 381 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 382 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 383 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 384                                         CONFIG_SYS_QMAN_CENA_SIZE)
 385 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 386 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 387
 388 #define CONFIG_SYS_DPAA_FMAN
 389 #define CONFIG_SYS_DPAA_PME
 390 #define CONFIG_SYS_PMAN
 391 #define CONFIG_SYS_DPAA_DCE
 392 #define CONFIG_SYS_DPAA_RMAN
 393 #define CONFIG_SYS_INTERLAKEN
 394
 395 /* Default address of microcode for the Linux Fman driver */
 396 #if defined(CONFIG_SPIFLASH)
 397 /*
 398  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 399  * env, so we got 0x110000.
 400  */
 401 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 402 #elif defined(CONFIG_SDCARD)
 403 /*
 404  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 405  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 406  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 407  */
 408 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 409 #elif defined(CONFIG_NAND)
 410 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 411 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 412 /*
 413  * Slave has no ucode locally, it can fetch this from remote. When implementing
 414  * in two corenet boards, slave's ucode could be stored in master's memory
 415  * space, the address can be mapped from slave TLB->slave LAW->
 416  * slave SRIO or PCIE outbound window->master inbound window->
 417  * master LAW->the ucode address in master's memory space.
 418  */
 419 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 420 #else
 421 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 422 #endif
 423 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 424 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 425 #endif /* CONFIG_NOBQFMAN */
 426
 427 #ifdef CONFIG_SYS_DPAA_FMAN
 428 #define CONFIG_PHYLIB_10G
 429 #define CONFIG_PHY_VITESSE
 430 #define CONFIG_PHY_TERANETICS
 431 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 432 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 433 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 434 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 435 #define FM1_10GEC1_PHY_ADDR     0x0
 436 #define FM1_10GEC2_PHY_ADDR     0x1
 437 #define FM2_10GEC1_PHY_ADDR     0x2
 438 #define FM2_10GEC2_PHY_ADDR     0x3
 439 #endif
 440
 441 /* SATA */
 442 #ifdef CONFIG_FSL_SATA_V2
 443 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 444 #define CONFIG_SATA1
 445 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 446 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 447 #define CONFIG_SATA2
 448 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 449 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 450
 451 #define CONFIG_LBA48
 452 #endif
 453
 454 #ifdef CONFIG_FMAN_ENET
 455 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 456 #endif
 457
 458 /*
 459 * USB
 460 */
 461 #define CONFIG_USB_EHCI_FSL
 462 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 463 #define CONFIG_HAS_FSL_DR_USB
 464
 465 #ifdef CONFIG_MMC
 466 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 467 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 468 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 469 #define CONFIG_ESDHC_DETECT_QUIRK \
 470         (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
 471         IS_SVR_REV(get_svr(), 1, 0))
 472 #define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
 473         (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
 474 #endif
 475
 476
 477 #define __USB_PHY_TYPE  utmi
 478
 479 /*
 480  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 481  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 482  * interleaving. It can be cacheline, page, bank, superbank.
 483  * See doc/README.fsl-ddr for details.
 484  */
 485 #ifdef CONFIG_ARCH_T4240
 486 #define CTRL_INTLV_PREFERED 3way_4KB
 487 #else
 488 #define CTRL_INTLV_PREFERED cacheline
 489 #endif
 490
 491 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 492         "hwconfig=fsl_ddr:"                                     \
 493         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 494         "bank_intlv=auto;"                                      \
 495         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 496         "netdev=eth0\0"                                         \
 497         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 498         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
 499         "tftpflash=tftpboot $loadaddr $uboot && "               \
 500         "protect off $ubootaddr +$filesize && "                 \
 501         "erase $ubootaddr +$filesize && "                       \
 502         "cp.b $loadaddr $ubootaddr $filesize && "               \
 503         "protect on $ubootaddr +$filesize && "                  \
 504         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 505         "consoledev=ttyS0\0"                                    \
 506         "ramdiskaddr=2000000\0"                                 \
 507         "ramdiskfile=t4240qds/ramdisk.uboot\0"                  \
 508         "fdtaddr=1e00000\0"                                     \
 509         "fdtfile=t4240qds/t4240qds.dtb\0"                               \
 510         "bdev=sda3\0"
 511
 512 #define CONFIG_HVBOOT                           \
 513         "setenv bootargs config-addr=0x60000000; "      \
 514         "bootm 0x01000000 - 0x00f00000"
 515
 516 #define CONFIG_ALU                              \
 517         "setenv bootargs root=/dev/$bdev rw "           \
 518         "console=$consoledev,$baudrate $othbootargs;"   \
 519         "cpu 1 release 0x01000000 - - -;"               \
 520         "cpu 2 release 0x01000000 - - -;"               \
 521         "cpu 3 release 0x01000000 - - -;"               \
 522         "cpu 4 release 0x01000000 - - -;"               \
 523         "cpu 5 release 0x01000000 - - -;"               \
 524         "cpu 6 release 0x01000000 - - -;"               \
 525         "cpu 7 release 0x01000000 - - -;"               \
 526         "go 0x01000000"
 527
 528 #define CONFIG_LINUX                            \
 529         "setenv bootargs root=/dev/ram rw "             \
 530         "console=$consoledev,$baudrate $othbootargs;"   \
 531         "setenv ramdiskaddr 0x02000000;"                \
 532         "setenv fdtaddr 0x00c00000;"                    \
 533         "setenv loadaddr 0x1000000;"                    \
 534         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 535
 536 #define CONFIG_HDBOOT                                   \
 537         "setenv bootargs root=/dev/$bdev rw "           \
 538         "console=$consoledev,$baudrate $othbootargs;"   \
 539         "tftp $loadaddr $bootfile;"                     \
 540         "tftp $fdtaddr $fdtfile;"                       \
 541         "bootm $loadaddr - $fdtaddr"
 542
 543 #define CONFIG_NFSBOOTCOMMAND                   \
 544         "setenv bootargs root=/dev/nfs rw "     \
 545         "nfsroot=$serverip:$rootpath "          \
 546         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 547         "console=$consoledev,$baudrate $othbootargs;"   \
 548         "tftp $loadaddr $bootfile;"             \
 549         "tftp $fdtaddr $fdtfile;"               \
 550         "bootm $loadaddr - $fdtaddr"
 551
 552 #define CONFIG_RAMBOOTCOMMAND                           \
 553         "setenv bootargs root=/dev/ram rw "             \
 554         "console=$consoledev,$baudrate $othbootargs;"   \
 555         "tftp $ramdiskaddr $ramdiskfile;"               \
 556         "tftp $loadaddr $bootfile;"                     \
 557         "tftp $fdtaddr $fdtfile;"                       \
 558         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 559
 560 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 561
 562 #include <asm/fsl_secure_boot.h>
 563
 564 #endif  /* __CONFIG_H */