include/configs/T4240RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 /*
   8  * T4240 RDB board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #define CONFIG_FSL_SATA_V2
  14 #define CONFIG_PCIE4
  15
  16 #define CONFIG_ICS307_REFCLK_HZ         25000000  /* ICS307 ref clk freq */
  17
  18 #ifdef CONFIG_RAMBOOT_PBL
  19 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
  20 #ifndef CONFIG_SDCARD
  21 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  22 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  23 #else
  24 #define CONFIG_SPL_FLUSH_IMAGE
  25 #define CONFIG_SPL_PAD_TO               0x40000
  26 #define CONFIG_SPL_MAX_SIZE             0x28000
  27 #define RESET_VECTOR_OFFSET             0x27FFC
  28 #define BOOT_PAGE_OFFSET                0x27000
  29
  30 #ifdef  CONFIG_SDCARD
  31 #define CONFIG_RESET_VECTOR_ADDRESS     0x200FFC
  32 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  33 #define CONFIG_SYS_MMC_U_BOOT_DST       0x00200000
  34 #define CONFIG_SYS_MMC_U_BOOT_START     0x00200000
  35 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  36 #ifndef CONFIG_SPL_BUILD
  37 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  38 #endif
  39 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
  40 #endif
  41
  42 #ifdef CONFIG_SPL_BUILD
  43 #define CONFIG_SPL_SKIP_RELOCATE
  44 #define CONFIG_SPL_COMMON_INIT_DDR
  45 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  46 #endif
  47
  48 #endif
  49 #endif /* CONFIG_RAMBOOT_PBL */
  50
  51 #define CONFIG_DDR_ECC
  52
  53 /* High Level Configuration Options */
  54 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  55
  56 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  57 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  58 #endif
  59
  60 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  61 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  62 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  63 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  64 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  65 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  66
  67 #define CONFIG_ENV_OVERWRITE
  68
  69 /*
  70  * These can be toggled for performance analysis, otherwise use default.
  71  */
  72 #define CONFIG_SYS_CACHE_STASHING
  73 #define CONFIG_BTB                      /* toggle branch predition */
  74 #ifdef CONFIG_DDR_ECC
  75 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  76 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  77 #endif
  78
  79 #define CONFIG_ENABLE_36BIT_PHYS
  80
  81 #define CONFIG_ADDR_MAP
  82 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
  83
  84 /*
  85  *  Config the L3 Cache as L3 SRAM
  86  */
  87 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  88 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  89 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  90 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  91 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
  92 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
  93 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
  94
  95 #define CONFIG_SYS_DCSRBAR              0xf0000000
  96 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  97
  98 /*
  99  * DDR Setup
 100  */
 101 #define CONFIG_VERY_BIG_RAM
 102 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 103 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 104
 105 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 106 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
 107
 108 #define CONFIG_DDR_SPD
 109
 110 /*
 111  * IFC Definitions
 112  */
 113 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 114 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 115
 116 #ifdef CONFIG_SPL_BUILD
 117 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
 118 #else
 119 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 120 #endif
 121
 122 #define CONFIG_HWCONFIG
 123
 124 /* define to use L1 as initial stack */
 125 #define CONFIG_L1_INIT_RAM
 126 #define CONFIG_SYS_INIT_RAM_LOCK
 127 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 128 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 129 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 130 /* The assembler doesn't like typecast */
 131 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 132         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 133           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 134 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 135
 136 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 137                                         GENERATED_GBL_DATA_SIZE)
 138 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 139
 140 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 141 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 142
 143 /* Serial Port - controlled on board with jumper J8
 144  * open - index 2
 145  * shorted - index 1
 146  */
 147 #define CONFIG_SYS_NS16550_SERIAL
 148 #define CONFIG_SYS_NS16550_REG_SIZE     1
 149 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 150
 151 #define CONFIG_SYS_BAUDRATE_TABLE       \
 152         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 153
 154 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 155 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 156 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 157 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 158
 159 /* I2C */
 160 #ifndef CONFIG_DM_I2C
 161 #define CONFIG_SYS_I2C
 162 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 163 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 164 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 165 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 166 #else
 167 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM
 168 #define CONFIG_I2C_DEFAULT_BUS_NUMBER   0
 169 #endif
 170
 171 #define CONFIG_SYS_I2C_FSL
 172
 173 /*
 174  * General PCI
 175  * Memory space is mapped 1-1, but I/O space must start from 0.
 176  */
 177
 178 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 179 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 180 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 181 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 182 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 183
 184 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 185 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 186 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 187 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 188 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 189
 190 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 191 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 192 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 193 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 194 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 195
 196 /* controller 4, Base address 203000 */
 197 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 198 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 199 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 200
 201 #ifdef CONFIG_PCI
 202 #if !defined(CONFIG_DM_PCI)
 203 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 204 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 205 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 206 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 207 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 208 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 209 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 210 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 211 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 212 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 213 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 214 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 215 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 216 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 217 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
 218 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 219 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 220 #define CONFIG_PCI_INDIRECT_BRIDGE
 221 #endif
 222
 223 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 224 #endif  /* CONFIG_PCI */
 225
 226 /* SATA */
 227 #ifdef CONFIG_FSL_SATA_V2
 228 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 229 #define CONFIG_SATA1
 230 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 231 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 232 #define CONFIG_SATA2
 233 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 234 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 235
 236 #define CONFIG_LBA48
 237 #endif
 238
 239 #ifdef CONFIG_FMAN_ENET
 240 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 241 #endif
 242
 243 /*
 244  * Environment
 245  */
 246 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 247 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 248
 249 /*
 250  * Command line configuration.
 251  */
 252
 253 /*
 254  * Miscellaneous configurable options
 255  */
 256 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 257
 258 /*
 259  * For booting Linux, the board info and command line data
 260  * have to be in the first 64 MB of memory, since this is
 261  * the maximum mapped by the Linux kernel during initialization.
 262  */
 263 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 264 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 265
 266 #ifdef CONFIG_CMD_KGDB
 267 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 268 #endif
 269
 270 /*
 271  * Environment Configuration
 272  */
 273 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 274 #define CONFIG_BOOTFILE         "uImage"
 275 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 276
 277 /* default location for tftp and bootm */
 278 #define CONFIG_LOADADDR         1000000
 279
 280 #define CONFIG_HVBOOT                                   \
 281         "setenv bootargs config-addr=0x60000000; "      \
 282         "bootm 0x01000000 - 0x00f00000"
 283
 284 #if defined(CONFIG_SPIFLASH)
 285 #elif defined(CONFIG_SDCARD)
 286 #define CONFIG_SYS_MMC_ENV_DEV          0
 287 #endif
 288
 289 #define CONFIG_SYS_CLK_FREQ     66666666
 290 #define CONFIG_DDR_CLK_FREQ     133333333
 291
 292 #ifndef __ASSEMBLY__
 293 unsigned long get_board_sys_clk(void);
 294 unsigned long get_board_ddr_clk(void);
 295 #endif
 296
 297 /*
 298  * DDR Setup
 299  */
 300 #define CONFIG_SYS_SPD_BUS_NUM  0
 301 #define SPD_EEPROM_ADDRESS1     0x52
 302 #define SPD_EEPROM_ADDRESS2     0x54
 303 #define SPD_EEPROM_ADDRESS3     0x56
 304 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 305 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 306
 307 /*
 308  * IFC Definitions
 309  */
 310 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 311 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 312                                 + 0x8000000) | \
 313                                 CSPR_PORT_SIZE_16 | \
 314                                 CSPR_MSEL_NOR | \
 315                                 CSPR_V)
 316 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 317 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 318                                 CSPR_PORT_SIZE_16 | \
 319                                 CSPR_MSEL_NOR | \
 320                                 CSPR_V)
 321 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 322 /* NOR Flash Timing Params */
 323 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 324
 325 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 326                                 FTIM0_NOR_TEADC(0x5) | \
 327                                 FTIM0_NOR_TEAHC(0x5))
 328 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 329                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 330                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 331 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 332                                 FTIM2_NOR_TCH(0x4) | \
 333                                 FTIM2_NOR_TWPH(0x0E) | \
 334                                 FTIM2_NOR_TWP(0x1c))
 335 #define CONFIG_SYS_NOR_FTIM3    0x0
 336
 337 #define CONFIG_SYS_FLASH_QUIET_TEST
 338 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 339
 340 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 341 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 342 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 343 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 344
 345 #define CONFIG_SYS_FLASH_EMPTY_INFO
 346 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 347                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 348
 349 /* NAND Flash on IFC */
 350 #define CONFIG_NAND_FSL_IFC
 351 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 352 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 353 #define CONFIG_SYS_NAND_BASE            0xff800000
 354 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 355
 356 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 357 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 358                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 359                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 360                                 | CSPR_V)
 361 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 362
 363 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 364                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 365                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 366                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 367                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 368                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 369                                 | CSOR_NAND_PB(128))    /*Page Per Block = 128*/
 370
 371 #define CONFIG_SYS_NAND_ONFI_DETECTION
 372
 373 /* ONFI NAND Flash mode0 Timing Params */
 374 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 375                                         FTIM0_NAND_TWP(0x18)   | \
 376                                         FTIM0_NAND_TWCHT(0x07) | \
 377                                         FTIM0_NAND_TWH(0x0a))
 378 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 379                                         FTIM1_NAND_TWBE(0x39)  | \
 380                                         FTIM1_NAND_TRR(0x0e)   | \
 381                                         FTIM1_NAND_TRP(0x18))
 382 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 383                                         FTIM2_NAND_TREH(0x0a) | \
 384                                         FTIM2_NAND_TWHRE(0x1e))
 385 #define CONFIG_SYS_NAND_FTIM3           0x0
 386
 387 #define CONFIG_SYS_NAND_DDR_LAW         11
 388 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 389 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 390
 391 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 392
 393 #if defined(CONFIG_MTD_RAW_NAND)
 394 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 395 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 396 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 397 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 398 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 399 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 400 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 401 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 402 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 403 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 404 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 405 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 406 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 407 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 408 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 409 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 410 #else
 411 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 412 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 413 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 414 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 415 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 416 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 417 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 418 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 419 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 420 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 421 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 422 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 423 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 424 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 425 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 426 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 427 #endif
 428 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 429 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 430 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 431 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 432 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 433 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 434 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 435 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 436
 437 /* CPLD on IFC */
 438 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 439 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 440 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 441 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
 442                                 | CSPR_PORT_SIZE_8 \
 443                                 | CSPR_MSEL_GPCM \
 444                                 | CSPR_V)
 445
 446 #define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 447 #define CONFIG_SYS_CSOR3        0x0
 448
 449 /* CPLD Timing parameters for IFC CS3 */
 450 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 451                                         FTIM0_GPCM_TEADC(0x0e) | \
 452                                         FTIM0_GPCM_TEAHC(0x0e))
 453 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 454                                         FTIM1_GPCM_TRAD(0x1f))
 455 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 456                                         FTIM2_GPCM_TCH(0x8) | \
 457                                         FTIM2_GPCM_TWP(0x1f))
 458 #define CONFIG_SYS_CS3_FTIM3            0x0
 459
 460 #if defined(CONFIG_RAMBOOT_PBL)
 461 #define CONFIG_SYS_RAMBOOT
 462 #endif
 463
 464 /* I2C */
 465 #define CONFIG_SYS_FSL_I2C_SPEED        100000  /* I2C speed */
 466 #define CONFIG_SYS_FSL_I2C2_SPEED       100000  /* I2C2 speed */
 467 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
 468 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
 469
 470 #define I2C_MUX_CH_DEFAULT      0x8
 471 #define I2C_MUX_CH_VOL_MONITOR  0xa
 472 #define I2C_MUX_CH_VSC3316_FS   0xc
 473 #define I2C_MUX_CH_VSC3316_BS   0xd
 474
 475 /* Voltage monitor on channel 2*/
 476 #define I2C_VOL_MONITOR_ADDR            0x40
 477 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 478 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 479 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 480
 481 #define CONFIG_VID_FLS_ENV              "t4240rdb_vdd_mv"
 482 #ifndef CONFIG_SPL_BUILD
 483 #define CONFIG_VID
 484 #endif
 485 #define CONFIG_VOL_MONITOR_IR36021_SET
 486 #define CONFIG_VOL_MONITOR_IR36021_READ
 487 /* The lowest and highest voltage allowed for T4240RDB */
 488 #define VDD_MV_MIN                      819
 489 #define VDD_MV_MAX                      1212
 490
 491 /*
 492  * eSPI - Enhanced SPI
 493  */
 494
 495 /* Qman/Bman */
 496 #ifndef CONFIG_NOBQFMAN
 497 #define CONFIG_SYS_BMAN_NUM_PORTALS     50
 498 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 499 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 500 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 501 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 502 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 503 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 504 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 505 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 506                                         CONFIG_SYS_BMAN_CENA_SIZE)
 507 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 508 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 509 #define CONFIG_SYS_QMAN_NUM_PORTALS     50
 510 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 511 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 512 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 513 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 514 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 515 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 516 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 517 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 518                                         CONFIG_SYS_QMAN_CENA_SIZE)
 519 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 520 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 521
 522 #define CONFIG_SYS_DPAA_FMAN
 523 #define CONFIG_SYS_DPAA_PME
 524 #define CONFIG_SYS_PMAN
 525 #define CONFIG_SYS_DPAA_DCE
 526 #define CONFIG_SYS_DPAA_RMAN
 527 #define CONFIG_SYS_INTERLAKEN
 528
 529 /* Default address of microcode for the Linux Fman driver */
 530 #if defined(CONFIG_SPIFLASH)
 531 /*
 532  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 533  * env, so we got 0x110000.
 534  */
 535 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 536 #elif defined(CONFIG_SDCARD)
 537 /*
 538  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 539  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 540  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 541  */
 542 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 543 #elif defined(CONFIG_MTD_RAW_NAND)
 544 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
 545 #else
 546 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 547 #endif
 548 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 549 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 550 #endif /* CONFIG_NOBQFMAN */
 551
 552 #ifdef CONFIG_SYS_DPAA_FMAN
 553 #define CONFIG_CORTINA_FW_ADDR          0xefe00000
 554 #define CONFIG_CORTINA_FW_LENGTH        0x40000
 555 #define SGMII_PHY_ADDR1 0x0
 556 #define SGMII_PHY_ADDR2 0x1
 557 #define SGMII_PHY_ADDR3 0x2
 558 #define SGMII_PHY_ADDR4 0x3
 559 #define SGMII_PHY_ADDR5 0x4
 560 #define SGMII_PHY_ADDR6 0x5
 561 #define SGMII_PHY_ADDR7 0x6
 562 #define SGMII_PHY_ADDR8 0x7
 563 #define FM1_10GEC1_PHY_ADDR     0x10
 564 #define FM1_10GEC2_PHY_ADDR     0x11
 565 #define FM2_10GEC1_PHY_ADDR     0x12
 566 #define FM2_10GEC2_PHY_ADDR     0x13
 567 #define CORTINA_PHY_ADDR1       FM1_10GEC1_PHY_ADDR
 568 #define CORTINA_PHY_ADDR2       FM1_10GEC2_PHY_ADDR
 569 #define CORTINA_PHY_ADDR3       FM2_10GEC1_PHY_ADDR
 570 #define CORTINA_PHY_ADDR4       FM2_10GEC2_PHY_ADDR
 571 #endif
 572
 573 /* SATA */
 574 #ifdef CONFIG_FSL_SATA_V2
 575 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 576 #define CONFIG_SATA1
 577 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 578 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 579 #define CONFIG_SATA2
 580 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 581 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 582
 583 #define CONFIG_LBA48
 584 #endif
 585
 586 #ifdef CONFIG_FMAN_ENET
 587 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 588 #endif
 589
 590 /*
 591 * USB
 592 */
 593 #define CONFIG_USB_EHCI_FSL
 594 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 595 #define CONFIG_HAS_FSL_DR_USB
 596
 597 #ifdef CONFIG_MMC
 598 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 599 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 600 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 601 #endif
 602
 603
 604 #define __USB_PHY_TYPE  utmi
 605
 606 /*
 607  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 608  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 609  * interleaving. It can be cacheline, page, bank, superbank.
 610  * See doc/README.fsl-ddr for details.
 611  */
 612 #ifdef CONFIG_ARCH_T4240
 613 #define CTRL_INTLV_PREFERED 3way_4KB
 614 #else
 615 #define CTRL_INTLV_PREFERED cacheline
 616 #endif
 617
 618 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 619         "hwconfig=fsl_ddr:"                                     \
 620         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 621         "bank_intlv=auto;"                                      \
 622         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 623         "netdev=eth0\0"                                         \
 624         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 625         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 626         "tftpflash=tftpboot $loadaddr $uboot && "               \
 627         "protect off $ubootaddr +$filesize && "                 \
 628         "erase $ubootaddr +$filesize && "                       \
 629         "cp.b $loadaddr $ubootaddr $filesize && "               \
 630         "protect on $ubootaddr +$filesize && "                  \
 631         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 632         "consoledev=ttyS0\0"                                    \
 633         "ramdiskaddr=2000000\0"                                 \
 634         "ramdiskfile=t4240rdb/ramdisk.uboot\0"                  \
 635         "fdtaddr=1e00000\0"                                     \
 636         "fdtfile=t4240rdb/t4240rdb.dtb\0"                       \
 637         "bdev=sda3\0"
 638
 639 #define CONFIG_HVBOOT                                   \
 640         "setenv bootargs config-addr=0x60000000; "      \
 641         "bootm 0x01000000 - 0x00f00000"
 642
 643 #define CONFIG_LINUX                                    \
 644         "setenv bootargs root=/dev/ram rw "             \
 645         "console=$consoledev,$baudrate $othbootargs;"   \
 646         "setenv ramdiskaddr 0x02000000;"                \
 647         "setenv fdtaddr 0x00c00000;"                    \
 648         "setenv loadaddr 0x1000000;"                    \
 649         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 650
 651 #define CONFIG_HDBOOT                                   \
 652         "setenv bootargs root=/dev/$bdev rw "           \
 653         "console=$consoledev,$baudrate $othbootargs;"   \
 654         "tftp $loadaddr $bootfile;"                     \
 655         "tftp $fdtaddr $fdtfile;"                       \
 656         "bootm $loadaddr - $fdtaddr"
 657
 658 #define CONFIG_NFSBOOTCOMMAND                   \
 659         "setenv bootargs root=/dev/nfs rw "     \
 660         "nfsroot=$serverip:$rootpath "          \
 661         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 662         "console=$consoledev,$baudrate $othbootargs;"   \
 663         "tftp $loadaddr $bootfile;"             \
 664         "tftp $fdtaddr $fdtfile;"               \
 665         "bootm $loadaddr - $fdtaddr"
 666
 667 #define CONFIG_RAMBOOTCOMMAND                           \
 668         "setenv bootargs root=/dev/ram rw "             \
 669         "console=$consoledev,$baudrate $othbootargs;"   \
 670         "tftp $ramdiskaddr $ramdiskfile;"               \
 671         "tftp $loadaddr $bootfile;"                     \
 672         "tftp $fdtaddr $fdtfile;"                       \
 673         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 674
 675 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 676
 677 #include <asm/fsl_secure_boot.h>
 678
 679 #endif  /* __CONFIG_H */