include/configs/TASREG.h

   1 /*
   2  * Configuation settings for the esd TASREG board.
   3  *
   4  * (C) Copyright 2004
   5  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 /*
  27  * board/config.h - configuration options, board specific
  28  */
  29
  30 #ifndef _TASREG_H
  31 #define _TASREG_H
  32
  33 #ifndef __ASSEMBLY__
  34 #include <asm/m5249.h>
  35 #endif
  36
  37 /*
  38  * High Level Configuration Options
  39  * (easy to change)
  40  */
  41 #define CONFIG_MCF52x2                  /* define processor family */
  42 #define CONFIG_M5249                    /* define processor type */
  43
  44 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  45
  46 #define CONFIG_MCFTMR
  47
  48 #define CONFIG_MCFUART
  49 #define CFG_UART_PORT           (0)
  50 #define CONFIG_BAUDRATE         19200
  51 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
  52
  53 #undef  CONFIG_WATCHDOG
  54
  55 #undef CONFIG_MONITOR_IS_IN_RAM               /* no pre-loader required!!! ;-) */
  56
  57
  58 /*
  59  * BOOTP options
  60  */
  61 #define CONFIG_BOOTP_BOOTFILESIZE
  62 #define CONFIG_BOOTP_BOOTPATH
  63 #define CONFIG_BOOTP_GATEWAY
  64 #define CONFIG_BOOTP_HOSTNAME
  65
  66
  67 /*
  68  * Command line configuration.
  69  */
  70 #include <config_cmd_default.h>
  71
  72 #define CONFIG_CMD_BSP
  73 #define CONFIG_CMD_EEPROM
  74 #define CONFIG_CMD_I2C
  75
  76 #undef CONFIG_CMD_NET
  77
  78
  79 #define CONFIG_BOOTDELAY        3
  80
  81 #define CFG_PROMPT              "=> "
  82 #define CFG_LONGHELP                            /* undef to save memory         */
  83
  84 #if defined(CONFIG_CMD_KGDB)
  85 #define CFG_CBSIZE              1024            /* Console I/O Buffer Size      */
  86 #else
  87 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
  88 #endif
  89 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  90 #define CFG_MAXARGS             16              /* max number of command args   */
  91 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
  92
  93 #define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
  94 #define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
  95 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
  96 #define CONFIG_LOOPW            1       /* enable loopw command         */
  97 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
  98
  99 #define CFG_LOAD_ADDR           0x200000        /* default load address */
 100
 101 #define CFG_MEMTEST_START       0x400
 102 #define CFG_MEMTEST_END         0x380000
 103
 104 #define CFG_HZ                  1000
 105
 106 /*
 107  * Clock configuration: enable only one of the following options
 108  */
 109
 110 #if 0 /* this setting will run the cpu at 11MHz */
 111 #define CFG_PLL_BYPASS          1                /* bypass PLL for test purpose */
 112 #undef  CFG_FAST_CLK                             /* MCF5249 can run at 140MHz   */
 113 #define CFG_CLK                 11289600         /* PLL bypass                  */
 114 #endif
 115
 116 #if 0 /* this setting will run the cpu at 70MHz */
 117 #undef  CFG_PLL_BYPASS                           /* bypass PLL for test purpose */
 118 #undef  CFG_FAST_CLK                             /* MCF5249 can run at 140MHz   */
 119 #define CFG_CLK                 72185018         /* The next lower speed        */
 120 #endif
 121
 122 #if 1 /* this setting will run the cpu at 140MHz */
 123 #undef  CFG_PLL_BYPASS                           /* bypass PLL for test purpose */
 124 #define CFG_FAST_CLK            1                /* MCF5249 can run at 140MHz   */
 125 #define CFG_CLK                 132025600        /* MCF5249 can run at 140MHz   */
 126 #endif
 127
 128 /*
 129  * Low Level Configuration Settings
 130  * (address mappings, register initial values, etc.)
 131  * You should know what you are doing if you make changes here.
 132  */
 133
 134 #define CFG_MBAR                0x10000000      /* Register Base Addrs */
 135 #define CFG_MBAR2               0x80000000
 136
 137 /*-----------------------------------------------------------------------
 138  * I2C
 139  */
 140 #define CONFIG_SOFT_I2C
 141 #define CFG_I2C_SPEED           100000  /* I2C speed and slave address */
 142 #define CFG_I2C_SLAVE           0x7F
 143 #define CFG_I2C_EEPROM_ADDR     0x50    /* EEPROM CAT28WC32             */
 144 #define CFG_I2C_EEPROM_ADDR_LEN 2       /* Bytes of address             */
 145 /* mask of address bits that overflow into the "EEPROM chip address"    */
 146 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x01
 147 #define CFG_EEPROM_PAGE_WRITE_BITS 5    /* The Catalyst CAT24WC32 has   */
 148                                         /* 32 byte page write mode using*/
 149                                         /* last 5 bits of the address   */
 150 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10   /* and takes up to 10 msec */
 151 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 152
 153 #if defined (CONFIG_SOFT_I2C)
 154 #if 0 /* push-pull */
 155 #define SDA             0x00800000
 156 #define SCL             0x00000008
 157 #define DIR0            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_EN))
 158 #define DIR1            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_EN))
 159 #define OUT0            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_OUT))
 160 #define OUT1            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_OUT))
 161 #define IN0             *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_READ))
 162 #define IN1             *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_READ))
 163 #define I2C_INIT        {OUT1|=SDA;OUT0|=SCL;}
 164 #define I2C_READ        ((IN1&SDA)?1:0)
 165 #define I2C_SDA(x)      {if(x)OUT1|=SDA;else OUT1&=~SDA;}
 166 #define I2C_SCL(x)      {if(x)OUT0|=SCL;else OUT0&=~SCL;}
 167 #define I2C_DELAY       {udelay(5);}
 168 #define I2C_ACTIVE      {DIR1|=SDA;}
 169 #define I2C_TRISTATE    {DIR1&=~SDA;}
 170 #else /* open-collector */
 171 #define SDA             0x00800000
 172 #define SCL             0x00000008
 173 #define DIR0            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_EN))
 174 #define DIR1            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_EN))
 175 #define OUT0            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_OUT))
 176 #define OUT1            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_OUT))
 177 #define IN0             *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_READ))
 178 #define IN1             *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_READ))
 179 #define I2C_INIT        {DIR1&=~SDA;DIR0&=~SCL;OUT1&=~SDA;OUT0&=~SCL;}
 180 #define I2C_READ        ((IN1&SDA)?1:0)
 181 #define I2C_SDA(x)      {if(x)DIR1&=~SDA;else DIR1|=SDA;}
 182 #define I2C_SCL(x)      {if(x)DIR0&=~SCL;else DIR0|=SCL;}
 183 #define I2C_DELAY       {udelay(5);}
 184 #define I2C_ACTIVE      {DIR1|=SDA;}
 185 #define I2C_TRISTATE    {DIR1&=~SDA;}
 186 #endif
 187 #endif
 188
 189 /*-----------------------------------------------------------------------
 190  * Definitions for initial stack pointer and data area (in DPRAM)
 191  */
 192 #define CFG_INIT_RAM_ADDR       0x20000000
 193 #define CFG_INIT_RAM_END        0x1000  /* End of used area in internal SRAM    */
 194 #define CFG_GBL_DATA_SIZE       64      /* size in bytes reserved for initial data */
 195 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 196 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 197
 198 #define CONFIG_ENV_IS_IN_FLASH  1
 199 #define CONFIG_ENV_ADDR         0xFFC40000      /* Address of Environment Sector*/
 200 #define CONFIG_ENV_SIZE         0x10000 /* Total Size of Environment Sector     */
 201 #define CONFIG_ENV_SECT_SIZE    0x10000 /* see README - env sector total size   */
 202
 203 /*-----------------------------------------------------------------------
 204  * Start addresses for the final memory configuration
 205  * (Set up by the startup code)
 206  * Please note that CFG_SDRAM_BASE _must_ start at 0
 207  */
 208 #define CFG_SDRAM_BASE          0x00000000
 209 #define CFG_SDRAM_SIZE          16              /* SDRAM size in MB */
 210 #define CFG_FLASH_BASE          0xffc00000
 211
 212 #if 0 /* test-only */
 213 #define CONFIG_PRAM             512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
 214 #endif
 215
 216 #define CFG_MONITOR_BASE        (CFG_FLASH_BASE + 0x400)
 217
 218 #define CFG_MONITOR_LEN         0x20000
 219 #define CFG_MALLOC_LEN          (1 * 1024*1024) /* Reserve 1 MB for malloc()    */
 220 #define CFG_BOOTPARAMS_LEN      64*1024
 221
 222 /*
 223  * For booting Linux, the board info and command line data
 224  * have to be in the first 8 MB of memory, since this is
 225  * the maximum mapped by the Linux kernel during initialization ??
 226  */
 227 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 228
 229 /*-----------------------------------------------------------------------
 230  * FLASH organization
 231  */
 232 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 233 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
 234
 235 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 236 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 237
 238 #define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
 239 #define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
 240 #define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
 241 /*
 242  * The following defines are added for buggy IOP480 byte interface.
 243  * All other boards should use the standard values (CPCI405 etc.)
 244  */
 245 #define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
 246 #define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
 247 #define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
 248
 249 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 250
 251 /*-----------------------------------------------------------------------
 252  * Cache Configuration
 253  */
 254 #define CFG_CACHELINE_SIZE      16
 255
 256 /*-----------------------------------------------------------------------
 257  * Memory bank definitions
 258  */
 259
 260 /* CS0 - AMD Flash, address 0xffc00000 */
 261 #define CFG_CSAR0               0xffc0
 262 #define CFG_CSCR0               0x1980          /* WS=0110, AA=1, PS=10         */
 263 /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
 264 #define CFG_CSMR0               0x003f0021      /* 4MB, AA=0, WP=0, C/I=1, V=1  */
 265
 266 /* CS1 - FPGA, address 0xe0000000 */
 267 #define CFG_CSAR1               0xe000
 268 #define CFG_CSCR1               0x0d80          /* WS=0011, AA=1, PS=10         */
 269 #define CFG_CSMR1               0x00010001      /* 128kB, AA=0, WP=0, C/I=0, V=1*/
 270
 271 /*-----------------------------------------------------------------------
 272  * Port configuration
 273  */
 274 #define CFG_GPIO_FUNC           0x00000008      /* Set gpio pins: none          */
 275 #define CFG_GPIO1_FUNC          0x00df00f0      /* 36-39(SWITCH),48-52(FPGAs),54*/
 276 #define CFG_GPIO_EN             0x00000008      /* Set gpio output enable       */
 277 #define CFG_GPIO1_EN            0x00c70000      /* Set gpio output enable       */
 278 #define CFG_GPIO_OUT            0x00000008      /* Set outputs to default state */
 279 #define CFG_GPIO1_OUT           0x00c70000      /* Set outputs to default state */
 280
 281 #define CFG_GPIO1_LED           0x00400000      /* user led                     */
 282
 283 /*-----------------------------------------------------------------------
 284  * FPGA stuff
 285  */
 286 #define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
 287 #define CFG_FPGA_MAX_SIZE       512*1024    /* 512kByte is enough for XC2S200*/
 288
 289 /* FPGA program pin configuration */
 290 #define CFG_FPGA_PRG            0x00010000  /* FPGA program pin (ppc output) */
 291 #define CFG_FPGA_CLK            0x00040000  /* FPGA clk pin (ppc output)     */
 292 #define CFG_FPGA_DATA           0x00020000  /* FPGA data pin (ppc output)    */
 293 #define CFG_FPGA_INIT           0x00080000  /* FPGA init pin (ppc input)     */
 294 #define CFG_FPGA_DONE           0x00100000  /* FPGA done pin (ppc input)     */
 295
 296 #endif  /* _TASREG_H */