include/configs/TASREG.h

   1 /*
   2  * Configuation settings for the esd TASREG board.
   3  *
   4  * (C) Copyright 2004
   5  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 /*
  27  * board/config.h - configuration options, board specific
  28  */
  29
  30 #ifndef _TASREG_H
  31 #define _TASREG_H
  32
  33 #ifndef __ASSEMBLY__
  34 #include <asm/m5249.h>
  35 #endif
  36
  37 /*
  38  * High Level Configuration Options
  39  * (easy to change)
  40  */
  41 #define CONFIG_MCF52x2                  /* define processor family */
  42 #define CONFIG_M5249                    /* define processor type */
  43
  44 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  45
  46 #define CONFIG_BAUDRATE         19200
  47 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
  48
  49 #undef  CONFIG_WATCHDOG
  50
  51 #undef CONFIG_MONITOR_IS_IN_RAM               /* no pre-loader required!!! ;-) */
  52
  53
  54 /*
  55  * Command line configuration.
  56  */
  57 #include <config_cmd_default.h>
  58
  59 #define CONFIG_CMD_BSP
  60 #define CONFIG_CMD_EEPROM
  61 #define CONFIG_CMD_I2C
  62
  63 #undef CONFIG_CMD_NET
  64
  65
  66 #define CONFIG_BOOTDELAY        3
  67
  68 #define CFG_PROMPT              "=> "
  69 #define CFG_LONGHELP                            /* undef to save memory         */
  70
  71 #if defined(CONFIG_CMD_KGDB)
  72 #define CFG_CBSIZE              1024            /* Console I/O Buffer Size      */
  73 #else
  74 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
  75 #endif
  76 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  77 #define CFG_MAXARGS             16              /* max number of command args   */
  78 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
  79
  80 #define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
  81 #define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
  82 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
  83 #define CONFIG_LOOPW            1       /* enable loopw command         */
  84 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
  85
  86 #define CFG_LOAD_ADDR           0x200000        /* default load address */
  87
  88 #define CFG_MEMTEST_START       0x400
  89 #define CFG_MEMTEST_END         0x380000
  90
  91 #define CFG_HZ                  1000
  92
  93 /*
  94  * Clock configuration: enable only one of the following options
  95  */
  96
  97 #if 0 /* this setting will run the cpu at 11MHz */
  98 #define CFG_PLL_BYPASS          1                /* bypass PLL for test purpose */
  99 #undef  CFG_FAST_CLK                             /* MCF5249 can run at 140MHz   */
 100 #define CFG_CLK                 11289600         /* PLL bypass                  */
 101 #endif
 102
 103 #if 0 /* this setting will run the cpu at 70MHz */
 104 #undef  CFG_PLL_BYPASS                           /* bypass PLL for test purpose */
 105 #undef  CFG_FAST_CLK                             /* MCF5249 can run at 140MHz   */
 106 #define CFG_CLK                 72185018         /* The next lower speed        */
 107 #endif
 108
 109 #if 1 /* this setting will run the cpu at 140MHz */
 110 #undef  CFG_PLL_BYPASS                           /* bypass PLL for test purpose */
 111 #define CFG_FAST_CLK            1                /* MCF5249 can run at 140MHz   */
 112 #define CFG_CLK                 132025600        /* MCF5249 can run at 140MHz   */
 113 #endif
 114
 115 /*
 116  * Low Level Configuration Settings
 117  * (address mappings, register initial values, etc.)
 118  * You should know what you are doing if you make changes here.
 119  */
 120
 121 #define CFG_MBAR                0x10000000      /* Register Base Addrs */
 122 #define CFG_MBAR2               0x80000000
 123
 124 /*-----------------------------------------------------------------------
 125  * I2C
 126  */
 127 #define CONFIG_SOFT_I2C
 128 #define CFG_I2C_SPEED           100000  /* I2C speed and slave address */
 129 #define CFG_I2C_SLAVE           0x7F
 130 #define CFG_I2C_EEPROM_ADDR     0x50    /* EEPROM CAT28WC32             */
 131 #define CFG_I2C_EEPROM_ADDR_LEN 2       /* Bytes of address             */
 132 /* mask of address bits that overflow into the "EEPROM chip address"    */
 133 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x01
 134 #define CFG_EEPROM_PAGE_WRITE_BITS 5    /* The Catalyst CAT24WC32 has   */
 135                                         /* 32 byte page write mode using*/
 136                                         /* last 5 bits of the address   */
 137 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10   /* and takes up to 10 msec */
 138 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 139
 140 #if defined (CONFIG_SOFT_I2C)
 141 #if 0 /* push-pull */
 142 #define SDA             0x00800000
 143 #define SCL             0x00000008
 144 #define DIR0            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_EN))
 145 #define DIR1            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_EN))
 146 #define OUT0            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_OUT))
 147 #define OUT1            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_OUT))
 148 #define IN0             *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_READ))
 149 #define IN1             *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_READ))
 150 #define I2C_INIT        {OUT1|=SDA;OUT0|=SCL;}
 151 #define I2C_READ        ((IN1&SDA)?1:0)
 152 #define I2C_SDA(x)      {if(x)OUT1|=SDA;else OUT1&=~SDA;}
 153 #define I2C_SCL(x)      {if(x)OUT0|=SCL;else OUT0&=~SCL;}
 154 #define I2C_DELAY       {udelay(5);}
 155 #define I2C_ACTIVE      {DIR1|=SDA;}
 156 #define I2C_TRISTATE    {DIR1&=~SDA;}
 157 #else /* open-collector */
 158 #define SDA             0x00800000
 159 #define SCL             0x00000008
 160 #define DIR0            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_EN))
 161 #define DIR1            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_EN))
 162 #define OUT0            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_OUT))
 163 #define OUT1            *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_OUT))
 164 #define IN0             *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_READ))
 165 #define IN1             *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_READ))
 166 #define I2C_INIT        {DIR1&=~SDA;DIR0&=~SCL;OUT1&=~SDA;OUT0&=~SCL;}
 167 #define I2C_READ        ((IN1&SDA)?1:0)
 168 #define I2C_SDA(x)      {if(x)DIR1&=~SDA;else DIR1|=SDA;}
 169 #define I2C_SCL(x)      {if(x)DIR0&=~SCL;else DIR0|=SCL;}
 170 #define I2C_DELAY       {udelay(5);}
 171 #define I2C_ACTIVE      {DIR1|=SDA;}
 172 #define I2C_TRISTATE    {DIR1&=~SDA;}
 173 #endif
 174 #endif
 175
 176 /*-----------------------------------------------------------------------
 177  * Definitions for initial stack pointer and data area (in DPRAM)
 178  */
 179 #define CFG_INIT_RAM_ADDR       0x20000000
 180 #define CFG_INIT_RAM_END        0x1000  /* End of used area in internal SRAM    */
 181 #define CFG_GBL_DATA_SIZE       64      /* size in bytes reserved for initial data */
 182 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 183 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 184
 185 #define CFG_ENV_IS_IN_FLASH     1
 186 #define CFG_ENV_ADDR            0xFFC40000      /* Address of Environment Sector*/
 187 #define CFG_ENV_SIZE            0x10000 /* Total Size of Environment Sector     */
 188 #define CFG_ENV_SECT_SIZE       0x10000 /* see README - env sector total size   */
 189
 190 /*-----------------------------------------------------------------------
 191  * Start addresses for the final memory configuration
 192  * (Set up by the startup code)
 193  * Please note that CFG_SDRAM_BASE _must_ start at 0
 194  */
 195 #define CFG_SDRAM_BASE          0x00000000
 196 #define CFG_SDRAM_SIZE          16              /* SDRAM size in MB */
 197 #define CFG_FLASH_BASE          0xffc00000
 198
 199 #if 0 /* test-only */
 200 #define CONFIG_PRAM             512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
 201 #endif
 202
 203 #define CFG_MONITOR_BASE        (CFG_FLASH_BASE + 0x400)
 204
 205 #define CFG_MONITOR_LEN         0x20000
 206 #define CFG_MALLOC_LEN          (1 * 1024*1024) /* Reserve 1 MB for malloc()    */
 207 #define CFG_BOOTPARAMS_LEN      64*1024
 208
 209 /*
 210  * For booting Linux, the board info and command line data
 211  * have to be in the first 8 MB of memory, since this is
 212  * the maximum mapped by the Linux kernel during initialization ??
 213  */
 214 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 215
 216 /*-----------------------------------------------------------------------
 217  * FLASH organization
 218  */
 219 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 220 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
 221
 222 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 223 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 224
 225 #define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
 226 #define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
 227 #define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
 228 /*
 229  * The following defines are added for buggy IOP480 byte interface.
 230  * All other boards should use the standard values (CPCI405 etc.)
 231  */
 232 #define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
 233 #define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
 234 #define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
 235
 236 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 237
 238 /*-----------------------------------------------------------------------
 239  * Cache Configuration
 240  */
 241 #define CFG_CACHELINE_SIZE      16
 242
 243 /*-----------------------------------------------------------------------
 244  * Memory bank definitions
 245  */
 246
 247 /* CS0 - AMD Flash, address 0xffc00000 */
 248 #define CFG_CSAR0               0xffc0
 249 #define CFG_CSCR0               0x1980          /* WS=0110, AA=1, PS=10         */
 250 /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
 251 #define CFG_CSMR0               0x003f0021      /* 4MB, AA=0, WP=0, C/I=1, V=1  */
 252
 253 /* CS1 - FPGA, address 0xe0000000 */
 254 #define CFG_CSAR1               0xe000
 255 #define CFG_CSCR1               0x0d80          /* WS=0011, AA=1, PS=10         */
 256 #define CFG_CSMR1               0x00010001      /* 128kB, AA=0, WP=0, C/I=0, V=1*/
 257
 258 /*-----------------------------------------------------------------------
 259  * Port configuration
 260  */
 261 #define CFG_GPIO_FUNC           0x00000008      /* Set gpio pins: none          */
 262 #define CFG_GPIO1_FUNC          0x00df00f0      /* 36-39(SWITCH),48-52(FPGAs),54*/
 263 #define CFG_GPIO_EN             0x00000008      /* Set gpio output enable       */
 264 #define CFG_GPIO1_EN            0x00c70000      /* Set gpio output enable       */
 265 #define CFG_GPIO_OUT            0x00000008      /* Set outputs to default state */
 266 #define CFG_GPIO1_OUT           0x00c70000      /* Set outputs to default state */
 267
 268 #define CFG_GPIO1_LED           0x00400000      /* user led                     */
 269
 270 /*-----------------------------------------------------------------------
 271  * FPGA stuff
 272  */
 273 #define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
 274 #define CFG_FPGA_MAX_SIZE       512*1024    /* 512kByte is enough for XC2S200*/
 275
 276 /* FPGA program pin configuration */
 277 #define CFG_FPGA_PRG            0x00010000  /* FPGA program pin (ppc output) */
 278 #define CFG_FPGA_CLK            0x00040000  /* FPGA clk pin (ppc output)     */
 279 #define CFG_FPGA_DATA           0x00020000  /* FPGA data pin (ppc output)    */
 280 #define CFG_FPGA_INIT           0x00080000  /* FPGA init pin (ppc input)     */
 281 #define CFG_FPGA_DONE           0x00100000  /* FPGA done pin (ppc input)     */
 282
 283 #endif  /* _TASREG_H */