include/configs/TB5200.h

   1 /*
   2  * (C) Copyright 2003-2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004-2006
   6  * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * High Level Configuration Options
  16  * (easy to change)
  17  */
  18
  19 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU */
  20 #define CONFIG_MPC5200          1       /* (more precisely an MPC5200 CPU) */
  21 #define CONFIG_TQM5200          1       /* ... on TQM5200 module */
  22 #define CONFIG_TB5200           1       /* ... on a TB5200 base board */
  23
  24 /*
  25  * Valid values for CONFIG_SYS_TEXT_BASE are:
  26  * 0xFC000000   boot low (standard configuration with room for
  27  *              max 64 MByte Flash ROM)
  28  * 0xFFF00000   boot high (for a backup copy of U-Boot)
  29  * 0x00100000   boot from RAM (for testing only)
  30  */
  31 #ifndef CONFIG_SYS_TEXT_BASE
  32 #define CONFIG_SYS_TEXT_BASE    0xFC000000
  33 #endif
  34
  35 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33.000000MHz */
  36
  37 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
  38
  39 /*
  40  * Serial console configuration
  41  */
  42 #define CONFIG_PSC_CONSOLE      1       /* default console is on PSC1 */
  43 #define CONFIG_PSC_CONSOLE2     6       /* second console is on PSC6 */
  44 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
  45 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  46
  47 /*
  48  * Video console
  49  */
  50 #if 1
  51 #define CONFIG_VIDEO
  52 #define CONFIG_VIDEO_SM501
  53 #define CONFIG_VIDEO_SM501_32BPP
  54 #define CONFIG_CFB_CONSOLE
  55 #define CONFIG_VIDEO_LOGO
  56 #define CONFIG_VGA_AS_SINGLE_DEVICE
  57 #define CONFIG_CONSOLE_EXTRA_INFO
  58 #define CONFIG_VIDEO_SW_CURSOR
  59 #define CONFIG_SPLASH_SCREEN
  60 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
  61 #endif
  62
  63 /* Partitions */
  64 #define CONFIG_MAC_PARTITION
  65 #define CONFIG_DOS_PARTITION
  66 #define CONFIG_ISO_PARTITION
  67
  68 /* USB */
  69 #define CONFIG_USB_OHCI
  70 #define CONFIG_USB_STORAGE
  71
  72 /* POST support */
  73 #define CONFIG_POST             (CONFIG_SYS_POST_MEMORY   | \
  74                                  CONFIG_SYS_POST_CPU       | \
  75                                  CONFIG_SYS_POST_I2C)
  76
  77 #ifdef CONFIG_POST
  78 /* preserve space for the post_word at end of on-chip SRAM */
  79 #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
  80 #endif
  81
  82
  83 /*
  84  * BOOTP options
  85  */
  86 #define CONFIG_BOOTP_BOOTFILESIZE
  87 #define CONFIG_BOOTP_BOOTPATH
  88 #define CONFIG_BOOTP_GATEWAY
  89 #define CONFIG_BOOTP_HOSTNAME
  90
  91
  92 /*
  93  * Command line configuration.
  94  */
  95 #include <config_cmd_default.h>
  96
  97 #define CONFIG_CMD_ASKENV
  98 #define CONFIG_CMD_DATE
  99 #define CONFIG_CMD_DHCP
 100 #define CONFIG_CMD_ECHO
 101 #define CONFIG_CMD_EEPROM
 102 #define CONFIG_CMD_EXT2
 103 #define CONFIG_CMD_FAT
 104 #define CONFIG_CMD_I2C
 105 #define CONFIG_CMD_IDE
 106 #define CONFIG_CMD_JFFS2
 107 #define CONFIG_CMD_MII
 108 #define CONFIG_CMD_NFS
 109 #define CONFIG_CMD_PING
 110 #define CONFIG_CMD_REGINFO
 111 #define CONFIG_CMD_SNTP
 112 #define CONFIG_CMD_BSP
 113 #define CONFIG_CMD_USB
 114
 115 #ifdef CONFIG_VIDEO
 116 #define CONFIG_CMD_BMP
 117 #endif
 118
 119 #ifdef CONFIG_POST
 120 #define CONFIG_CMD_DIAG
 121 #endif
 122
 123
 124 #define CONFIG_TIMESTAMP                /* display image timestamps */
 125
 126 #if (CONFIG_SYS_TEXT_BASE == 0xFC000000)                /* Boot low */
 127 #   define CONFIG_SYS_LOWBOOT           1
 128 #endif
 129
 130 /*
 131  * Autobooting
 132  */
 133 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 134
 135 #define CONFIG_PREBOOT  "echo;" \
 136         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 137         "echo"
 138
 139 #undef  CONFIG_BOOTARGS
 140
 141 #if defined(CONFIG_TQM5200_B)
 142 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 143         "netdev=eth0\0"                                                 \
 144         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 145         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 146         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 147                 "nfsroot=${serverip}:${rootpath}\0"                     \
 148         "addip=setenv bootargs ${bootargs} "                            \
 149                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 150                 ":${hostname}:${netdev}:off panic=1\0"                  \
 151         "flash_self=run ramargs addip;"                                 \
 152                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 153         "flash_nfs=run nfsargs addip;"                                  \
 154                 "bootm ${kernel_addr}\0"                                \
 155         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
 156         "bootfile=/tftpboot/tqm5200/uImage\0"                           \
 157         "load=tftp 200000 ${u-boot}\0"                                  \
 158         "u-boot=/tftpboot/tqm5200/u-boot.bin\0"                         \
 159         "update=protect off FC000000 FC07FFFF;"                         \
 160                 "erase FC000000 FC07FFFF;"                              \
 161                 "cp.b 200000 FC000000 ${filesize};"                     \
 162                 "protect on FC000000 FC07FFFF\0"                        \
 163         ""
 164 #else
 165 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 166         "netdev=eth0\0"                                                 \
 167         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 168         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 169         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 170                 "nfsroot=${serverip}:${rootpath}\0"                     \
 171         "addip=setenv bootargs ${bootargs} "                            \
 172                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 173                 ":${hostname}:${netdev}:off panic=1\0"                  \
 174         "flash_self=run ramargs addip;"                                 \
 175                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 176         "flash_nfs=run nfsargs addip;"                                  \
 177                 "bootm ${kernel_addr}\0"                                \
 178         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
 179         "bootfile=/tftpboot/tqm5200/uImage\0"                           \
 180         "load=tftp 200000 $(u-boot)\0"                                  \
 181         "u-boot=/tftpboot/tqm5200/u-boot.bin\0"                         \
 182         "update=protect off FC000000 FC05FFFF;"                         \
 183                 "erase FC000000 FC05FFFF;"                              \
 184                 "cp.b 200000 FC000000 ${filesize};"                     \
 185                 "protect on FC000000 FC05FFFF\0"                        \
 186         ""
 187 #endif /* CONFIG_TQM5200_B */
 188
 189 #define CONFIG_BOOTCOMMAND      "run net_nfs"
 190
 191 /*
 192  * IPB Bus clocking configuration.
 193  */
 194 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
 195
 196 #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
 197 /*
 198  * PCI Bus clocking configuration
 199  *
 200  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 201  * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
 202  * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
 203  */
 204 #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2            /* define for 66MHz speed */
 205 #endif
 206
 207 /*
 208  * I2C configuration
 209  */
 210 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 211 #define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #2 */
 212
 213 /*
 214  * I2C clock frequency
 215  *
 216  * Please notice, that the resulting clock frequency could differ from the
 217  * configured value. This is because the I2C clock is derived from system
 218  * clock over a frequency divider with only a few divider values. U-boot
 219  * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
 220  * approximation allways lies below the configured value, never above.
 221  */
 222 #define CONFIG_SYS_I2C_SPEED            100000 /* 100 kHz */
 223 #define CONFIG_SYS_I2C_SLAVE            0x7F
 224
 225 /*
 226  * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
 227  * also). For other EEPROMs configuration should be verified. On Mini-FAP the
 228  * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
 229  * same configuration could be used.
 230  */
 231 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x */
 232 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 233 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* =32 Bytes per write */
 234 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   20
 235
 236 /* List of I2C addresses to be verified by POST */
 237 #undef CONFIG_SYS_POST_I2C_ADDRS
 238 #define CONFIG_SYS_POST_I2C_ADDRS       {CONFIG_SYS_I2C_EEPROM_ADDR,    \
 239                                          CONFIG_SYS_I2C_RTC_ADDR,       \
 240                                          CONFIG_SYS_I2C_SLAVE}
 241
 242 /*
 243  * Flash configuration
 244  */
 245 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
 246
 247 /* use CFI flash driver */
 248 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 249 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 250 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_BOOTCS_START }
 251 #define CONFIG_SYS_FLASH_EMPTY_INFO
 252 #define CONFIG_SYS_FLASH_SIZE           0x04000000 /* 64 MByte */
 253 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sects on one chip */
 254 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 255
 256 #if !defined(CONFIG_SYS_LOWBOOT)
 257 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
 258 #else   /* CONFIG_SYS_LOWBOOT */
 259 #if defined(CONFIG_TQM5200_B)
 260 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00080000)
 261 #else
 262 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00060000)
 263 #endif /* CONFIG_TQM5200_B */
 264 #endif  /* CONFIG_SYS_LOWBOOT */
 265 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks
 266                                            (= chip selects) */
 267
 268 /* Dynamic MTD partition support */
 269 #define CONFIG_CMD_MTDPARTS
 270 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 271 #define CONFIG_FLASH_CFI_MTD
 272 #define MTDIDS_DEFAULT          "nor0=TQM5200-0"
 273 #if defined(CONFIG_TQM5200_B)
 274 #define MTDPARTS_DEFAULT        "mtdparts=TQM5200-0:768k(firmware),"    \
 275                                                 "1280k(kernel),"        \
 276                                                 "2m(initrd),"           \
 277                                                 "4m(small-fs),"         \
 278                                                 "16m(big-fs),"          \
 279                                                 "8m(misc)"
 280 #else
 281 #define MTDPARTS_DEFAULT        "mtdparts=TQM5200-0:640k(firmware),"    \
 282                                                 "1408k(kernel),"        \
 283                                                 "2m(initrd),"           \
 284                                                 "4m(small-fs),"         \
 285                                                 "16m(big-fs),"          \
 286                                                 "8m(misc)"
 287 #endif /* CONFIG_TQM5200_B */
 288
 289 /*
 290  * Environment settings
 291  */
 292 #define CONFIG_ENV_IS_IN_FLASH  1
 293 #define CONFIG_ENV_SIZE         0x10000
 294 #if defined(CONFIG_TQM5200_B)
 295 #define CONFIG_ENV_SECT_SIZE    0x40000
 296 #else
 297 #define CONFIG_ENV_SECT_SIZE    0x20000
 298 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 299 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 300 #endif /* CONFIG_TQM5200_B */
 301
 302 /*
 303  * Memory map
 304  */
 305 #define CONFIG_SYS_MBAR         0xF0000000
 306 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 307 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 308
 309 /* Use ON-Chip SRAM until RAM will be available */
 310 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 311 #ifdef CONFIG_POST
 312 /* preserve space for the post_word at end of on-chip SRAM */
 313 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_POST_SIZE
 314 #else
 315 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE
 316 #endif
 317
 318
 319 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 320 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 321
 322 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 323 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 324 #   define CONFIG_SYS_RAMBOOT           1
 325 #endif
 326
 327 #if defined(CONFIG_TQM5200_B)
 328 #define CONFIG_SYS_MONITOR_LEN          (512 << 10)     /* Reserve 512 kB for Monitor   */
 329 #else
 330 #define CONFIG_SYS_MONITOR_LEN          (384 << 10)     /* Reserve 384 kB for Monitor   */
 331 #endif /* CONFIG_TQM5200_B */
 332 #define CONFIG_SYS_MALLOC_LEN           (1024 << 10)    /* Reserve 1024 kB for malloc() */
 333 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 334
 335 /*
 336  * Ethernet configuration
 337  */
 338 #define CONFIG_MPC5xxx_FEC      1
 339 #define CONFIG_MPC5xxx_FEC_MII100
 340 /*
 341  * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 342  */
 343 /* #define CONFIG_MPC5xxx_FEC_MII10 */
 344 #define CONFIG_PHY_ADDR         0x00
 345
 346 /*
 347  * GPIO configuration
 348  *
 349  * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
 350  *      Bit 0 (mask: 0x80000000): 1
 351  * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 352  *      00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
 353  *      01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
 354  *            Use for REV200 STK52XX boards. Do not use with REV100 modules
 355  *            (because, there I2C1 is used as I2C bus)
 356  * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 357  * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
 358  *      000 -> All PSC2 pins are GIOPs
 359  *      001 -> CAN1/2 on PSC2 pins
 360  *             Use for REV100 STK52xx boards
 361  * use PSC3: Bits 20:23 (mask: 0x00000300):
 362  *      0001 -> USB2
 363  *      0000 -> GPIO
 364  * use PSC6:
 365  *   on STK52xx:
 366  *      use as UART. Pins PSC6_0 to PSC6_3 are used.
 367  *      Bits 9:11 (mask: 0x00700000):
 368  *         101 -> PSC6 : Extended POST test is not available
 369  *   on MINI-FAP and TQM5200_IB:
 370  *      use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
 371  *         000 -> PSC6 could not be used as UART, CODEC or IrDA
 372  *   GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
 373  *   tests.
 374  */
 375 #define CONFIG_SYS_GPS_PORT_CONFIG      0x81500114
 376
 377 /*
 378  * RTC configuration
 379  */
 380 #define CONFIG_RTC_M41T11       1
 381 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 382 #define CONFIG_SYS_M41T11_BASE_YEAR     1900    /* because Linux uses the same base
 383                                            year */
 384
 385 /*
 386  * Miscellaneous configurable options
 387  */
 388 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 389 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt   */
 390 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 391 #if defined(CONFIG_CMD_KGDB)
 392 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 393 #else
 394 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 395 #endif
 396 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 397 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 398 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 399
 400 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs */
 401 #if defined(CONFIG_CMD_KGDB)
 402 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 403 #endif
 404
 405 /* Enable an alternate, more extensive memory test */
 406 #define CONFIG_SYS_ALT_MEMTEST
 407
 408 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 409 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 410
 411 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 412
 413 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 414
 415 /*
 416  * Enable loopw command.
 417  */
 418 #define CONFIG_LOOPW
 419
 420 /*
 421  * Various low-level settings
 422  */
 423 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 424 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 425
 426 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 427 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 428 #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
 429 #define CONFIG_SYS_BOOTCS_CFG           0x0008DF30 /* for pci_clk  = 66 MHz */
 430 #else
 431 #define CONFIG_SYS_BOOTCS_CFG           0x0004DF30 /* for pci_clk = 33 MHz */
 432 #endif
 433 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 434 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 435
 436 #define CONFIG_LAST_STAGE_INIT
 437
 438 /*
 439  * SRAM - Do not map below 2 GB in address space, because this area is used
 440  * for SDRAM autosizing.
 441  */
 442 #define CONFIG_SYS_CS2_START            0xE5000000
 443 #define CONFIG_SYS_CS2_SIZE             0x100000        /* 1 MByte */
 444 #define CONFIG_SYS_CS2_CFG              0x0004D930
 445
 446 /*
 447  * Grafic controller - Do not map below 2 GB in address space, because this
 448  * area is used for SDRAM autosizing.
 449  */
 450 #define SM501_FB_BASE           0xE0000000
 451 #define CONFIG_SYS_CS1_START            (SM501_FB_BASE)
 452 #define CONFIG_SYS_CS1_SIZE             0x4000000       /* 64 MByte */
 453 #define CONFIG_SYS_CS1_CFG              0x8F48FF70
 454 #define SM501_MMIO_BASE         CONFIG_SYS_CS1_START + 0x03E00000
 455
 456 #define CONFIG_SYS_CS_BURST             0x00000000
 457 #define CONFIG_SYS_CS_DEADCYCLE 0x33333311      /* 1 dead cycle for flash and SM501 */
 458
 459 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
 460
 461 /*-----------------------------------------------------------------------
 462  * USB stuff
 463  *-----------------------------------------------------------------------
 464  */
 465 #define CONFIG_USB_CLOCK        0x0001BBBB
 466 #define CONFIG_USB_CONFIG       0x00001000
 467
 468 /*-----------------------------------------------------------------------
 469  * IDE/ATA stuff Supports IDE harddisk
 470  *-----------------------------------------------------------------------
 471  */
 472
 473 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 474
 475 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 476 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 477
 478 #define CONFIG_IDE_RESET                /* reset for ide supported      */
 479 #define CONFIG_IDE_PREINIT
 480
 481 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 482 #define CONFIG_SYS_IDE_MAXDEVICE        2       /* max. 2 drives per IDE bus    */
 483
 484 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 485
 486 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 487
 488 /* Offset for data I/O                  */
 489 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 490
 491 /* Offset for normal register accesses  */
 492 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 493
 494 /* Offset for alternate registers       */
 495 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 496
 497 /* Interval between registers                                                */
 498 #define CONFIG_SYS_ATA_STRIDE           4
 499
 500 #endif /* __CONFIG_H */