include/configs/TB5200.h

   1 /*
   2  * (C) Copyright 2003-2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004-2006
   6  * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * High Level Configuration Options
  16  * (easy to change)
  17  */
  18
  19 #define CONFIG_MPC5200          1       /* This is an MPC5200 CPU */
  20 #define CONFIG_TQM5200          1       /* ... on TQM5200 module */
  21 #define CONFIG_TB5200           1       /* ... on a TB5200 base board */
  22
  23 /*
  24  * Valid values for CONFIG_SYS_TEXT_BASE are:
  25  * 0xFC000000   boot low (standard configuration with room for
  26  *              max 64 MByte Flash ROM)
  27  * 0xFFF00000   boot high (for a backup copy of U-Boot)
  28  * 0x00100000   boot from RAM (for testing only)
  29  */
  30 #ifndef CONFIG_SYS_TEXT_BASE
  31 #define CONFIG_SYS_TEXT_BASE    0xFC000000
  32 #endif
  33
  34 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33.000000MHz */
  35
  36 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
  37
  38 /*
  39  * Serial console configuration
  40  */
  41 #define CONFIG_PSC_CONSOLE      1       /* default console is on PSC1 */
  42 #define CONFIG_PSC_CONSOLE2     6       /* second console is on PSC6 */
  43 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
  44 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  45
  46 /*
  47  * Video console
  48  */
  49 #if 1
  50 #define CONFIG_VIDEO
  51 #define CONFIG_VIDEO_SM501
  52 #define CONFIG_VIDEO_SM501_32BPP
  53 #define CONFIG_CFB_CONSOLE
  54 #define CONFIG_VIDEO_LOGO
  55 #define CONFIG_VGA_AS_SINGLE_DEVICE
  56 #define CONFIG_CONSOLE_EXTRA_INFO
  57 #define CONFIG_VIDEO_SW_CURSOR
  58 #define CONFIG_SPLASH_SCREEN
  59 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
  60 #endif
  61
  62 /* Partitions */
  63 #define CONFIG_MAC_PARTITION
  64 #define CONFIG_DOS_PARTITION
  65 #define CONFIG_ISO_PARTITION
  66
  67 /* USB */
  68 #define CONFIG_USB_OHCI
  69 #define CONFIG_USB_STORAGE
  70
  71 /* POST support */
  72 #define CONFIG_POST             (CONFIG_SYS_POST_MEMORY   | \
  73                                  CONFIG_SYS_POST_CPU       | \
  74                                  CONFIG_SYS_POST_I2C)
  75
  76 #ifdef CONFIG_POST
  77 /* preserve space for the post_word at end of on-chip SRAM */
  78 #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
  79 #endif
  80
  81
  82 /*
  83  * BOOTP options
  84  */
  85 #define CONFIG_BOOTP_BOOTFILESIZE
  86 #define CONFIG_BOOTP_BOOTPATH
  87 #define CONFIG_BOOTP_GATEWAY
  88 #define CONFIG_BOOTP_HOSTNAME
  89
  90
  91 /*
  92  * Command line configuration.
  93  */
  94 #include <config_cmd_default.h>
  95
  96 #define CONFIG_CMD_ASKENV
  97 #define CONFIG_CMD_DATE
  98 #define CONFIG_CMD_DHCP
  99 #define CONFIG_CMD_ECHO
 100 #define CONFIG_CMD_EEPROM
 101 #define CONFIG_CMD_EXT2
 102 #define CONFIG_CMD_FAT
 103 #define CONFIG_CMD_I2C
 104 #define CONFIG_CMD_IDE
 105 #define CONFIG_CMD_JFFS2
 106 #define CONFIG_CMD_MII
 107 #define CONFIG_CMD_NFS
 108 #define CONFIG_CMD_PING
 109 #define CONFIG_CMD_REGINFO
 110 #define CONFIG_CMD_SNTP
 111 #define CONFIG_CMD_BSP
 112 #define CONFIG_CMD_USB
 113
 114 #ifdef CONFIG_VIDEO
 115 #define CONFIG_CMD_BMP
 116 #endif
 117
 118 #ifdef CONFIG_POST
 119 #define CONFIG_CMD_DIAG
 120 #endif
 121
 122
 123 #define CONFIG_TIMESTAMP                /* display image timestamps */
 124
 125 #if (CONFIG_SYS_TEXT_BASE == 0xFC000000)                /* Boot low */
 126 #   define CONFIG_SYS_LOWBOOT           1
 127 #endif
 128
 129 /*
 130  * Autobooting
 131  */
 132 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 133
 134 #define CONFIG_PREBOOT  "echo;" \
 135         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 136         "echo"
 137
 138 #undef  CONFIG_BOOTARGS
 139
 140 #if defined(CONFIG_TQM5200_B)
 141 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 142         "netdev=eth0\0"                                                 \
 143         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 144         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 145         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 146                 "nfsroot=${serverip}:${rootpath}\0"                     \
 147         "addip=setenv bootargs ${bootargs} "                            \
 148                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 149                 ":${hostname}:${netdev}:off panic=1\0"                  \
 150         "flash_self=run ramargs addip;"                                 \
 151                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 152         "flash_nfs=run nfsargs addip;"                                  \
 153                 "bootm ${kernel_addr}\0"                                \
 154         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
 155         "bootfile=/tftpboot/tqm5200/uImage\0"                           \
 156         "load=tftp 200000 ${u-boot}\0"                                  \
 157         "u-boot=/tftpboot/tqm5200/u-boot.bin\0"                         \
 158         "update=protect off FC000000 FC07FFFF;"                         \
 159                 "erase FC000000 FC07FFFF;"                              \
 160                 "cp.b 200000 FC000000 ${filesize};"                     \
 161                 "protect on FC000000 FC07FFFF\0"                        \
 162         ""
 163 #else
 164 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 165         "netdev=eth0\0"                                                 \
 166         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 167         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 168         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 169                 "nfsroot=${serverip}:${rootpath}\0"                     \
 170         "addip=setenv bootargs ${bootargs} "                            \
 171                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 172                 ":${hostname}:${netdev}:off panic=1\0"                  \
 173         "flash_self=run ramargs addip;"                                 \
 174                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 175         "flash_nfs=run nfsargs addip;"                                  \
 176                 "bootm ${kernel_addr}\0"                                \
 177         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
 178         "bootfile=/tftpboot/tqm5200/uImage\0"                           \
 179         "load=tftp 200000 $(u-boot)\0"                                  \
 180         "u-boot=/tftpboot/tqm5200/u-boot.bin\0"                         \
 181         "update=protect off FC000000 FC05FFFF;"                         \
 182                 "erase FC000000 FC05FFFF;"                              \
 183                 "cp.b 200000 FC000000 ${filesize};"                     \
 184                 "protect on FC000000 FC05FFFF\0"                        \
 185         ""
 186 #endif /* CONFIG_TQM5200_B */
 187
 188 #define CONFIG_BOOTCOMMAND      "run net_nfs"
 189
 190 /*
 191  * IPB Bus clocking configuration.
 192  */
 193 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
 194
 195 #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
 196 /*
 197  * PCI Bus clocking configuration
 198  *
 199  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 200  * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
 201  * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
 202  */
 203 #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2            /* define for 66MHz speed */
 204 #endif
 205
 206 /*
 207  * I2C configuration
 208  */
 209 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 210 #define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #2 */
 211
 212 /*
 213  * I2C clock frequency
 214  *
 215  * Please notice, that the resulting clock frequency could differ from the
 216  * configured value. This is because the I2C clock is derived from system
 217  * clock over a frequency divider with only a few divider values. U-boot
 218  * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
 219  * approximation allways lies below the configured value, never above.
 220  */
 221 #define CONFIG_SYS_I2C_SPEED            100000 /* 100 kHz */
 222 #define CONFIG_SYS_I2C_SLAVE            0x7F
 223
 224 /*
 225  * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
 226  * also). For other EEPROMs configuration should be verified. On Mini-FAP the
 227  * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
 228  * same configuration could be used.
 229  */
 230 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x */
 231 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 232 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* =32 Bytes per write */
 233 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   20
 234
 235 /* List of I2C addresses to be verified by POST */
 236 #undef CONFIG_SYS_POST_I2C_ADDRS
 237 #define CONFIG_SYS_POST_I2C_ADDRS       {CONFIG_SYS_I2C_EEPROM_ADDR,    \
 238                                          CONFIG_SYS_I2C_RTC_ADDR,       \
 239                                          CONFIG_SYS_I2C_SLAVE}
 240
 241 /*
 242  * Flash configuration
 243  */
 244 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
 245
 246 /* use CFI flash driver */
 247 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 248 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 249 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_BOOTCS_START }
 250 #define CONFIG_SYS_FLASH_EMPTY_INFO
 251 #define CONFIG_SYS_FLASH_SIZE           0x04000000 /* 64 MByte */
 252 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sects on one chip */
 253 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 254
 255 #if !defined(CONFIG_SYS_LOWBOOT)
 256 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
 257 #else   /* CONFIG_SYS_LOWBOOT */
 258 #if defined(CONFIG_TQM5200_B)
 259 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00080000)
 260 #else
 261 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00060000)
 262 #endif /* CONFIG_TQM5200_B */
 263 #endif  /* CONFIG_SYS_LOWBOOT */
 264 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks
 265                                            (= chip selects) */
 266
 267 /* Dynamic MTD partition support */
 268 #define CONFIG_CMD_MTDPARTS
 269 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 270 #define CONFIG_FLASH_CFI_MTD
 271 #define MTDIDS_DEFAULT          "nor0=TQM5200-0"
 272 #if defined(CONFIG_TQM5200_B)
 273 #define MTDPARTS_DEFAULT        "mtdparts=TQM5200-0:768k(firmware),"    \
 274                                                 "1280k(kernel),"        \
 275                                                 "2m(initrd),"           \
 276                                                 "4m(small-fs),"         \
 277                                                 "16m(big-fs),"          \
 278                                                 "8m(misc)"
 279 #else
 280 #define MTDPARTS_DEFAULT        "mtdparts=TQM5200-0:640k(firmware),"    \
 281                                                 "1408k(kernel),"        \
 282                                                 "2m(initrd),"           \
 283                                                 "4m(small-fs),"         \
 284                                                 "16m(big-fs),"          \
 285                                                 "8m(misc)"
 286 #endif /* CONFIG_TQM5200_B */
 287
 288 /*
 289  * Environment settings
 290  */
 291 #define CONFIG_ENV_IS_IN_FLASH  1
 292 #define CONFIG_ENV_SIZE         0x10000
 293 #if defined(CONFIG_TQM5200_B)
 294 #define CONFIG_ENV_SECT_SIZE    0x40000
 295 #else
 296 #define CONFIG_ENV_SECT_SIZE    0x20000
 297 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 298 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 299 #endif /* CONFIG_TQM5200_B */
 300
 301 /*
 302  * Memory map
 303  */
 304 #define CONFIG_SYS_MBAR         0xF0000000
 305 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 306 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 307
 308 /* Use ON-Chip SRAM until RAM will be available */
 309 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 310 #ifdef CONFIG_POST
 311 /* preserve space for the post_word at end of on-chip SRAM */
 312 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_POST_SIZE
 313 #else
 314 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE
 315 #endif
 316
 317
 318 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 319 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 320
 321 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 322 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 323 #   define CONFIG_SYS_RAMBOOT           1
 324 #endif
 325
 326 #if defined(CONFIG_TQM5200_B)
 327 #define CONFIG_SYS_MONITOR_LEN          (512 << 10)     /* Reserve 512 kB for Monitor   */
 328 #else
 329 #define CONFIG_SYS_MONITOR_LEN          (384 << 10)     /* Reserve 384 kB for Monitor   */
 330 #endif /* CONFIG_TQM5200_B */
 331 #define CONFIG_SYS_MALLOC_LEN           (1024 << 10)    /* Reserve 1024 kB for malloc() */
 332 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 333
 334 /*
 335  * Ethernet configuration
 336  */
 337 #define CONFIG_MPC5xxx_FEC      1
 338 #define CONFIG_MPC5xxx_FEC_MII100
 339 /*
 340  * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 341  */
 342 /* #define CONFIG_MPC5xxx_FEC_MII10 */
 343 #define CONFIG_PHY_ADDR         0x00
 344
 345 /*
 346  * GPIO configuration
 347  *
 348  * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
 349  *      Bit 0 (mask: 0x80000000): 1
 350  * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 351  *      00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
 352  *      01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
 353  *            Use for REV200 STK52XX boards. Do not use with REV100 modules
 354  *            (because, there I2C1 is used as I2C bus)
 355  * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 356  * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
 357  *      000 -> All PSC2 pins are GIOPs
 358  *      001 -> CAN1/2 on PSC2 pins
 359  *             Use for REV100 STK52xx boards
 360  * use PSC3: Bits 20:23 (mask: 0x00000300):
 361  *      0001 -> USB2
 362  *      0000 -> GPIO
 363  * use PSC6:
 364  *   on STK52xx:
 365  *      use as UART. Pins PSC6_0 to PSC6_3 are used.
 366  *      Bits 9:11 (mask: 0x00700000):
 367  *         101 -> PSC6 : Extended POST test is not available
 368  *   on MINI-FAP and TQM5200_IB:
 369  *      use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
 370  *         000 -> PSC6 could not be used as UART, CODEC or IrDA
 371  *   GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
 372  *   tests.
 373  */
 374 #define CONFIG_SYS_GPS_PORT_CONFIG      0x81500114
 375
 376 /*
 377  * RTC configuration
 378  */
 379 #define CONFIG_RTC_M41T11       1
 380 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 381 #define CONFIG_SYS_M41T11_BASE_YEAR     1900    /* because Linux uses the same base
 382                                            year */
 383
 384 /*
 385  * Miscellaneous configurable options
 386  */
 387 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 388 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 389 #if defined(CONFIG_CMD_KGDB)
 390 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 391 #else
 392 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 393 #endif
 394 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 395 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 396 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 397
 398 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs */
 399 #if defined(CONFIG_CMD_KGDB)
 400 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 401 #endif
 402
 403 /* Enable an alternate, more extensive memory test */
 404 #define CONFIG_SYS_ALT_MEMTEST
 405
 406 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 407 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 408
 409 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 410
 411 /*
 412  * Enable loopw command.
 413  */
 414 #define CONFIG_LOOPW
 415
 416 /*
 417  * Various low-level settings
 418  */
 419 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 420 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 421
 422 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 423 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 424 #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
 425 #define CONFIG_SYS_BOOTCS_CFG           0x0008DF30 /* for pci_clk  = 66 MHz */
 426 #else
 427 #define CONFIG_SYS_BOOTCS_CFG           0x0004DF30 /* for pci_clk = 33 MHz */
 428 #endif
 429 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 430 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 431
 432 #define CONFIG_LAST_STAGE_INIT
 433
 434 /*
 435  * SRAM - Do not map below 2 GB in address space, because this area is used
 436  * for SDRAM autosizing.
 437  */
 438 #define CONFIG_SYS_CS2_START            0xE5000000
 439 #define CONFIG_SYS_CS2_SIZE             0x100000        /* 1 MByte */
 440 #define CONFIG_SYS_CS2_CFG              0x0004D930
 441
 442 /*
 443  * Grafic controller - Do not map below 2 GB in address space, because this
 444  * area is used for SDRAM autosizing.
 445  */
 446 #define SM501_FB_BASE           0xE0000000
 447 #define CONFIG_SYS_CS1_START            (SM501_FB_BASE)
 448 #define CONFIG_SYS_CS1_SIZE             0x4000000       /* 64 MByte */
 449 #define CONFIG_SYS_CS1_CFG              0x8F48FF70
 450 #define SM501_MMIO_BASE         CONFIG_SYS_CS1_START + 0x03E00000
 451
 452 #define CONFIG_SYS_CS_BURST             0x00000000
 453 #define CONFIG_SYS_CS_DEADCYCLE 0x33333311      /* 1 dead cycle for flash and SM501 */
 454
 455 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
 456
 457 /*-----------------------------------------------------------------------
 458  * USB stuff
 459  *-----------------------------------------------------------------------
 460  */
 461 #define CONFIG_USB_CLOCK        0x0001BBBB
 462 #define CONFIG_USB_CONFIG       0x00001000
 463
 464 /*-----------------------------------------------------------------------
 465  * IDE/ATA stuff Supports IDE harddisk
 466  *-----------------------------------------------------------------------
 467  */
 468
 469 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 470
 471 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 472 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 473
 474 #define CONFIG_IDE_RESET                /* reset for ide supported      */
 475 #define CONFIG_IDE_PREINIT
 476
 477 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 478 #define CONFIG_SYS_IDE_MAXDEVICE        2       /* max. 2 drives per IDE bus    */
 479
 480 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 481
 482 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 483
 484 /* Offset for data I/O                  */
 485 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 486
 487 /* Offset for normal register accesses  */
 488 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 489
 490 /* Offset for alternate registers       */
 491 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 492
 493 /* Interval between registers                                                */
 494 #define CONFIG_SYS_ATA_STRIDE           4
 495
 496 #endif /* __CONFIG_H */