include/configs/TK885D.h

   1 /*
   2  * (C) Copyright 2000-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2006
   6  * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * board/config.h - configuration options, board specific
  29  */
  30
  31 #ifndef __CONFIG_H
  32 #define __CONFIG_H
  33
  34 /*
  35  * High Level Configuration Options
  36  * (easy to change)
  37  */
  38
  39 #define CONFIG_MPC885           1       /* This is a MPC885 CPU         */
  40 #define CONFIG_TQM885D          1       /* ...on a TQM88D module        */
  41 #define CONFIG_TK885D           1       /* ...in a TK885D base board    */
  42
  43 #define CONFIG_SYS_TEXT_BASE    0x40000000
  44
  45 #define CONFIG_8xx_OSCLK                10000000        /*  10 MHz - PLL input clock    */
  46 #define CONFIG_SYS_8xx_CPUCLK_MIN               15000000        /*  15 MHz - CPU minimum clock  */
  47 #define CONFIG_SYS_8xx_CPUCLK_MAX               133000000       /* 133 MHz - CPU maximum clock  */
  48 #define CONFIG_8xx_CPUCLK_DEFAULT       66000000        /*  66 MHz - CPU default clock  */
  49                                                 /* (it will be used if there is no      */
  50                                                 /* 'cpuclk' variable with valid value)  */
  51
  52 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  53 #define CONFIG_SYS_SMC_RXBUFLEN 128
  54 #define CONFIG_SYS_MAXIDLE      10
  55 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  56
  57 #define CONFIG_BOOTCOUNT_LIMIT
  58
  59 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  60
  61 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  62
  63 #define CONFIG_PREBOOT  "echo;" \
  64         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  65         "echo"
  66
  67 #undef  CONFIG_BOOTARGS
  68
  69 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  70         "ethprime=FEC\0"                                                \
  71         "ethact=FEC\0"                                                  \
  72         "netdev=eth0\0"                                                 \
  73         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  74                 "nfsroot=${serverip}:${rootpath}\0"                     \
  75         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  76         "addip=setenv bootargs ${bootargs} "                            \
  77                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  78                 ":${hostname}:${netdev}:off panic=1\0"                  \
  79         "flash_nfs=run nfsargs addip;"                                  \
  80                 "bootm ${kernel_addr}\0"                                \
  81         "flash_self=run ramargs addip;"                                 \
  82                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  83         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  84         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  85         "bootfile=/tftpboot/tk885d/uImage\0"                            \
  86         "u-boot=/tftpboot/tk885d/u-boot.bin\0"                          \
  87         "kernel_addr=40080000\0"                                        \
  88         "ramdisk_addr=40180000\0"                                       \
  89         "load=tftp 200000 ${u-boot}\0"                                  \
  90         "update=protect off 40000000 +${filesize};"                     \
  91                 "erase 40000000 +${filesize};"                          \
  92                 "cp.b 200000 40000000 ${filesize};"                     \
  93                 "protect on 40000000 +${filesize}\0"                    \
  94         ""
  95 #define CONFIG_BOOTCOMMAND      "run flash_self"
  96
  97 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  98 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  99
 100 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 101
 102 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
 103
 104 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
 105
 106 /* enable I2C and select the hardware/software driver */
 107 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 108 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 109
 110 #define CONFIG_SYS_I2C_SPEED            93000   /* 93 kHz is supposed to work   */
 111 #define CONFIG_SYS_I2C_SLAVE            0xFE
 112
 113 #ifdef CONFIG_SOFT_I2C
 114 /*
 115  * Software (bit-bang) I2C driver configuration
 116  */
 117 #define PB_SCL          0x00000020      /* PB 26 */
 118 #define PB_SDA          0x00000010      /* PB 27 */
 119
 120 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 121 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 122 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 123 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 124 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 125                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 126 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 127                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 128 #define I2C_DELAY       udelay(2)       /* 1/4 I2C clock duration */
 129 #endif  /* CONFIG_SOFT_I2C */
 130
 131 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50            /* EEPROM AT24C??       */
 132 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2                /* two byte address     */
 133 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 134 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 135
 136 # define CONFIG_RTC_DS1337 1
 137 # define CONFIG_SYS_I2C_RTC_ADDR 0x68
 138
 139 /*
 140  * BOOTP options
 141  */
 142 #define CONFIG_BOOTP_SUBNETMASK
 143 #define CONFIG_BOOTP_GATEWAY
 144 #define CONFIG_BOOTP_HOSTNAME
 145 #define CONFIG_BOOTP_BOOTPATH
 146 #define CONFIG_BOOTP_BOOTFILESIZE
 147
 148
 149 #define CONFIG_MAC_PARTITION
 150 #define CONFIG_DOS_PARTITION
 151
 152 #undef CONFIG_RTC_MPC8xx                /* MPC885 does not support RTC  */
 153
 154 #define CONFIG_TIMESTAMP                /* but print image timestmps    */
 155
 156
 157 /*
 158  * Command line configuration.
 159  */
 160 #include <config_cmd_default.h>
 161
 162 #define CONFIG_CMD_ASKENV
 163 #define CONFIG_CMD_DATE
 164 #define CONFIG_CMD_DHCP
 165 #define CONFIG_CMD_EEPROM
 166 #define CONFIG_CMD_I2C
 167 #define CONFIG_CMD_IDE
 168 #define CONFIG_CMD_MII
 169 #define CONFIG_CMD_NFS
 170 #define CONFIG_CMD_PING
 171
 172
 173 /*
 174  * Miscellaneous configurable options
 175  */
 176 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 177 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt       */
 178
 179 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 180 #define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser          */
 181 #ifdef  CONFIG_SYS_HUSH_PARSER
 182 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 183 #endif
 184
 185 #if defined(CONFIG_CMD_KGDB)
 186 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 187 #else
 188 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 189 #endif
 190 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 191 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 192 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 193
 194 #define CONFIG_SYS_MEMTEST_START        0x0100000       /* memtest works on     */
 195 #define CONFIG_SYS_MEMTEST_END          0x0300000       /* 1 ... 3 MB in DRAM   */
 196 #define CONFIG_SYS_ALT_MEMTEST                          /* alternate, more extensive
 197                                                    memory test.*/
 198
 199 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 200
 201 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 202
 203 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 204
 205 /*
 206  * Enable loopw command.
 207  */
 208 #define CONFIG_LOOPW
 209
 210 /*
 211  * Low Level Configuration Settings
 212  * (address mappings, register initial values, etc.)
 213  * You should know what you are doing if you make changes here.
 214  */
 215 /*-----------------------------------------------------------------------
 216  * Internal Memory Mapped Register
 217  */
 218 #define CONFIG_SYS_IMMR         0xFFF00000
 219
 220 /*-----------------------------------------------------------------------
 221  * Definitions for initial stack pointer and data area (in DPRAM)
 222  */
 223 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 224 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 225 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 226 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 227
 228 /*-----------------------------------------------------------------------
 229  * Start addresses for the final memory configuration
 230  * (Set up by the startup code)
 231  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 232  */
 233 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 234 #define CONFIG_SYS_FLASH_BASE           0x40000000
 235 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 236 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 237 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)     /* Reserve 128 kB for malloc()  */
 238
 239 /*
 240  * For booting Linux, the board info and command line data
 241  * have to be in the first 8 MB of memory, since this is
 242  * the maximum mapped by the Linux kernel during initialization.
 243  */
 244 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 245
 246 /*-----------------------------------------------------------------------
 247  * FLASH organization
 248  */
 249
 250 /* use CFI flash driver */
 251 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 252 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 253 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 254 #define CONFIG_SYS_FLASH_EMPTY_INFO
 255 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 256 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks */
 257 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip */
 258
 259 #define CONFIG_ENV_IS_IN_FLASH  1
 260 #define CONFIG_ENV_OFFSET               0x40000 /*   Offset   of Environment Sector     */
 261 #define CONFIG_ENV_SIZE         0x08000 /* Total Size of Environment            */
 262 #define CONFIG_ENV_SECT_SIZE    0x40000 /* Total Size of Environment Sector     */
 263
 264 /* Address and size of Redundant Environment Sector     */
 265 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 266 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 267
 268 /*-----------------------------------------------------------------------
 269  * Hardware Information Block
 270  */
 271 #define CONFIG_SYS_HWINFO_OFFSET        0x0003FFC0      /* offset of HW Info block */
 272 #define CONFIG_SYS_HWINFO_SIZE          0x00000040      /* size   of HW Info block */
 273 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38      /* 'TQM8' */
 274
 275 /*-----------------------------------------------------------------------
 276  * Cache Configuration
 277  */
 278 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 279 #if defined(CONFIG_CMD_KGDB)
 280 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 281 #endif
 282
 283 /*-----------------------------------------------------------------------
 284  * SYPCR - System Protection Control                            11-9
 285  * SYPCR can only be written once after reset!
 286  *-----------------------------------------------------------------------
 287  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 288  */
 289 #if defined(CONFIG_WATCHDOG)
 290 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 291                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 292 #else
 293 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 294 #endif
 295
 296 /*-----------------------------------------------------------------------
 297  * SIUMCR - SIU Module Configuration                            11-6
 298  *-----------------------------------------------------------------------
 299  * PCMCIA config., multi-function pin tri-state
 300  */
 301 #ifndef CONFIG_CAN_DRIVER
 302 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 303 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 304 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 305 #endif  /* CONFIG_CAN_DRIVER */
 306
 307 /*-----------------------------------------------------------------------
 308  * TBSCR - Time Base Status and Control                         11-26
 309  *-----------------------------------------------------------------------
 310  * Clear Reference Interrupt Status, Timebase freezing enabled
 311  */
 312 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 313
 314 /*-----------------------------------------------------------------------
 315  * PISCR - Periodic Interrupt Status and Control                11-31
 316  *-----------------------------------------------------------------------
 317  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 318  */
 319 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 320
 321 /*-----------------------------------------------------------------------
 322  * SCCR - System Clock and reset Control Register               15-27
 323  *-----------------------------------------------------------------------
 324  * Set clock output, timebase and RTC source and divider,
 325  * power management and some other internal clocks
 326  */
 327 #define SCCR_MASK       SCCR_EBDF11
 328 #define CONFIG_SYS_SCCR (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 329                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 330                          SCCR_DFALCD00)
 331
 332 /*-----------------------------------------------------------------------
 333  * PCMCIA stuff
 334  *-----------------------------------------------------------------------
 335  *
 336  */
 337 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 338 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 339 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 340 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 341 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 342 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 343 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 344 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 345
 346 /*-----------------------------------------------------------------------
 347  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 348  *-----------------------------------------------------------------------
 349  */
 350
 351 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 352
 353 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 354 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 355 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 356
 357 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 358 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 359
 360 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 361
 362 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 363
 364 /* Offset for data I/O                  */
 365 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 366
 367 /* Offset for normal register accesses  */
 368 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 369
 370 /* Offset for alternate registers       */
 371 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 372
 373 /*-----------------------------------------------------------------------
 374  *
 375  *-----------------------------------------------------------------------
 376  *
 377  */
 378 #define CONFIG_SYS_DER 0
 379
 380 /*
 381  * Init Memory Controller:
 382  *
 383  * BR0/1 and OR0/1 (FLASH)
 384  */
 385
 386 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 387 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 388
 389 /* used to re-map FLASH both when starting from SRAM or FLASH:
 390  * restrict access enough to keep SRAM working (if any)
 391  * but not too much to meddle with FLASH accesses
 392  */
 393 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 394 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 395
 396 /*
 397  * FLASH timing: Default value of OR0 after reset
 398  */
 399 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
 400                                  OR_SCY_6_CLK | OR_TRLX)
 401
 402 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 403 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 404 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 405
 406 #define CONFIG_SYS_OR1_REMAP    CONFIG_SYS_OR0_REMAP
 407 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 408 #define CONFIG_SYS_BR1_PRELIM   ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 409
 410 /*
 411  * BR2/3 and OR2/3 (SDRAM)
 412  *
 413  */
 414 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 415 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 416 #define SDRAM_MAX_SIZE          (256 << 20)     /* max 256 MB per bank  */
 417
 418 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 419 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000A00
 420
 421 #define CONFIG_SYS_OR2_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 422 #define CONFIG_SYS_BR2_PRELIM   ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 423
 424 #ifndef CONFIG_CAN_DRIVER
 425 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 426 #define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 427 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 428 #define CONFIG_SYS_CAN_BASE             0xC0000000      /* CAN mapped at 0xC0000000     */
 429 #define CONFIG_SYS_CAN_OR_AM            0xFFFF8000      /* 32 kB address mask           */
 430 #define CONFIG_SYS_OR3_CAN              (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
 431 #define CONFIG_SYS_BR3_CAN              ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 432                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 433 #endif  /* CONFIG_CAN_DRIVER */
 434
 435 /*
 436  * 4096 Rows from SDRAM example configuration
 437  * 1000 factor s -> ms
 438  * 64   PTP (pre-divider from MPTPR) from SDRAM example configuration
 439  * 4    Number of refresh cycles per period
 440  * 64   Refresh cycle in ms per number of rows
 441  */
 442 #define CONFIG_SYS_PTA_PER_CLK  ((4096 * 64 * 1000) / (4 * 64))
 443
 444 /*
 445  * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
 446  *
 447  *                        CPUclock(MHz) * 31.2
 448  * CONFIG_SYS_MAMR_PTA = -----------------------------------     with DFBRG = 0
 449  *                2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
 450  *
 451  * CPU clock =  15 MHz:  CONFIG_SYS_MAMR_PTA =  29   ->  4 * 7.73 us
 452  * CPU clock =  50 MHz:  CONFIG_SYS_MAMR_PTA =  97   ->  4 * 7.76 us
 453  * CPU clock =  66 MHz:  CONFIG_SYS_MAMR_PTA = 128   ->  4 * 7.75 us
 454  * CPU clock = 133 MHz:  CONFIG_SYS_MAMR_PTA = 255   ->  4 * 7.67 us
 455  *
 456  * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
 457  * be met also in the default configuration, i.e. if environment variable
 458  * 'cpuclk' is not set.
 459  */
 460 #define CONFIG_SYS_MAMR_PTA             128
 461
 462 /*
 463  * Memory Periodic Timer Prescaler Register (MPTPR) values.
 464  */
 465 /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
 466 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16
 467 /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
 468 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8
 469
 470 /*
 471  * MAMR settings for SDRAM
 472  */
 473
 474 /* 8 column SDRAM */
 475 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 476                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 477                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 478 /* 9 column SDRAM */
 479 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 480                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 481                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 482 /* 10 column SDRAM */
 483 #define CONFIG_SYS_MAMR_10COL   ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 484                          MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9  |   \
 485                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 486
 487 /*
 488  * Network configuration
 489  */
 490 #define CONFIG_FEC_ENET                 /* enable ethernet on FEC */
 491 #define CONFIG_ETHER_ON_FEC1            /* ... for FEC1 */
 492 #define CONFIG_ETHER_ON_FEC2            /* ... for FEC2 */
 493
 494 #define CONFIG_LAST_STAGE_INIT          1 /* Have to configure PHYs for Linux */
 495
 496 /* CONFIG_SYS_DISCOVER_PHY only works with FEC if only one interface is enabled */
 497 #if (!defined(CONFIG_ETHER_ON_FEC1) || !defined(CONFIG_ETHER_ON_FEC2))
 498 #define CONFIG_SYS_DISCOVER_PHY
 499 #endif
 500
 501 #ifndef CONFIG_SYS_DISCOVER_PHY
 502 /* PHY addresses - hard wired in hardware */
 503 #define CONFIG_FEC1_PHY 1
 504 #define CONFIG_FEC2_PHY 2
 505 #endif
 506
 507 #define CONFIG_MII_INIT 1
 508
 509 #define CONFIG_NET_RETRY_COUNT  3
 510 #define CONFIG_ETHPRIME         "FEC"
 511
 512 /* pass open firmware flat tree */
 513 #define CONFIG_OF_LIBFDT        1
 514 #define CONFIG_OF_BOARD_SETUP   1
 515 #define CONFIG_HWCONFIG         1
 516
 517 #endif  /* __CONFIG_H */